3,5c3,5
< sim_seconds 0.408037 # Number of seconds simulated
< sim_ticks 408037199500 # Number of ticks simulated
< final_tick 408037199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.409399 # Number of seconds simulated
> sim_ticks 409399480000 # Number of ticks simulated
> final_tick 409399480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 90640 # Simulator instruction rate (inst/s)
< host_op_rate 111590 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 57729920 # Simulator tick rate (ticks/s)
< host_mem_usage 318440 # Number of bytes of host memory used
< host_seconds 7068.04 # Real time elapsed on the host
---
> host_inst_rate 93383 # Simulator instruction rate (inst/s)
> host_op_rate 114967 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 59675446 # Simulator tick rate (ticks/s)
> host_mem_usage 317532 # Number of bytes of host memory used
> host_seconds 6860.43 # Real time elapsed on the host
16,72c16,72
< system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 7008448 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 12940608 # Number of bytes read from this memory
< system.physmem.bytes_read::total 20176256 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4244736 # Number of bytes written to this memory
< system.physmem.bytes_written::total 4244736 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 109507 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 202197 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 315254 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 66324 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 66324 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 556812 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 17176003 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 31714285 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 49447099 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 556812 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 556812 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 10402816 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 10402816 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 10402816 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 556812 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 17176003 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 31714285 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 59849916 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 315254 # Number of read requests accepted
< system.physmem.writeReqs 66324 # Number of write requests accepted
< system.physmem.readBursts 315254 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 66324 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 20157248 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 19008 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4240064 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 20176256 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 4244736 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 297 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 51 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 14 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 19893 # Per bank write bursts
< system.physmem.perBankRdBursts::1 19507 # Per bank write bursts
< system.physmem.perBankRdBursts::2 19696 # Per bank write bursts
< system.physmem.perBankRdBursts::3 19811 # Per bank write bursts
< system.physmem.perBankRdBursts::4 19755 # Per bank write bursts
< system.physmem.perBankRdBursts::5 20266 # Per bank write bursts
< system.physmem.perBankRdBursts::6 19606 # Per bank write bursts
< system.physmem.perBankRdBursts::7 19431 # Per bank write bursts
< system.physmem.perBankRdBursts::8 19468 # Per bank write bursts
< system.physmem.perBankRdBursts::9 19384 # Per bank write bursts
< system.physmem.perBankRdBursts::10 19414 # Per bank write bursts
< system.physmem.perBankRdBursts::11 19672 # Per bank write bursts
< system.physmem.perBankRdBursts::12 19624 # Per bank write bursts
< system.physmem.perBankRdBursts::13 19992 # Per bank write bursts
< system.physmem.perBankRdBursts::14 19481 # Per bank write bursts
< system.physmem.perBankRdBursts::15 19957 # Per bank write bursts
< system.physmem.perBankWrBursts::0 4278 # Per bank write bursts
< system.physmem.perBankWrBursts::1 4105 # Per bank write bursts
---
> system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 7025088 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 12938560 # Number of bytes read from this memory
> system.physmem.bytes_read::total 20195840 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4244864 # Number of bytes written to this memory
> system.physmem.bytes_written::total 4244864 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 109767 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 202165 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 315560 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 66326 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 66326 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 567153 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 17159494 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 31603753 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 49330400 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 567153 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 567153 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 10368513 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 10368513 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 10368513 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 567153 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 17159494 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 31603753 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 59698913 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 315560 # Number of read requests accepted
> system.physmem.writeReqs 66326 # Number of write requests accepted
> system.physmem.readBursts 315560 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 66326 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 20177344 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4238912 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 20195840 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 4244864 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 19910 # Per bank write bursts
> system.physmem.perBankRdBursts::1 19474 # Per bank write bursts
> system.physmem.perBankRdBursts::2 19822 # Per bank write bursts
> system.physmem.perBankRdBursts::3 19845 # Per bank write bursts
> system.physmem.perBankRdBursts::4 19720 # Per bank write bursts
> system.physmem.perBankRdBursts::5 20103 # Per bank write bursts
> system.physmem.perBankRdBursts::6 19622 # Per bank write bursts
> system.physmem.perBankRdBursts::7 19424 # Per bank write bursts
> system.physmem.perBankRdBursts::8 19577 # Per bank write bursts
> system.physmem.perBankRdBursts::9 19501 # Per bank write bursts
> system.physmem.perBankRdBursts::10 19475 # Per bank write bursts
> system.physmem.perBankRdBursts::11 19731 # Per bank write bursts
> system.physmem.perBankRdBursts::12 19558 # Per bank write bursts
> system.physmem.perBankRdBursts::13 20043 # Per bank write bursts
> system.physmem.perBankRdBursts::14 19546 # Per bank write bursts
> system.physmem.perBankRdBursts::15 19920 # Per bank write bursts
> system.physmem.perBankWrBursts::0 4269 # Per bank write bursts
> system.physmem.perBankWrBursts::1 4104 # Per bank write bursts
74,76c74,76
< system.physmem.perBankWrBursts::3 4152 # Per bank write bursts
< system.physmem.perBankWrBursts::4 4250 # Per bank write bursts
< system.physmem.perBankWrBursts::5 4232 # Per bank write bursts
---
> system.physmem.perBankWrBursts::3 4150 # Per bank write bursts
> system.physmem.perBankWrBursts::4 4244 # Per bank write bursts
> system.physmem.perBankWrBursts::5 4227 # Per bank write bursts
81c81
< system.physmem.perBankWrBursts::10 4095 # Per bank write bursts
---
> system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
83c83
< system.physmem.perBankWrBursts::12 4096 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 4097 # Per bank write bursts
86c86
< system.physmem.perBankWrBursts::15 4151 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 4154 # Per bank write bursts
89c89
< system.physmem.totGap 408037145000 # Total gap between requests
---
> system.physmem.totGap 409399425500 # Total gap between requests
96c96
< system.physmem.readPktSize::6 315254 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 315560 # Read request sizes (log2)
103,117c103,117
< system.physmem.writePktSize::6 66324 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 128804 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 111420 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 14471 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 6711 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 6396 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 7547 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 8690 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 8601 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 7182 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 6341 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 3273 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 2426 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1825 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1270 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 66326 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 122658 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 117599 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 14107 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 6797 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 6389 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 7384 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 8395 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 8262 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 10480 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 4277 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 3294 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 2442 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1850 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 1337 # What read queue length does an incoming req see
151,189c151,189
< system.physmem.wrQLenPdf::15 590 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 607 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 986 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 1667 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 2405 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 2934 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 3403 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 3865 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 4344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 4750 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5220 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5565 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5589 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5488 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 4554 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 93 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 93 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 90 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 84 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 94 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 85 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 86 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 82 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 589 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 613 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 1000 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 1788 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 2652 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 3312 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 3720 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 4067 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4646 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 4886 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5091 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5229 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5064 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 4821 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4400 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4072 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 90 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 76 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 83 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 66 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 60 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see
191,192c191,192
< system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see
200,251c200,247
< system.physmem.bytesPerActivate::samples 136345 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 178.922586 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 128.860330 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 198.953379 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 53850 39.50% 39.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 57322 42.04% 81.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 14832 10.88% 92.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1348 0.99% 93.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 1343 0.99% 94.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1322 0.97% 95.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1347 0.99% 96.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1288 0.94% 97.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 3693 2.71% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 136345 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4024 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 74.490060 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 34.867874 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 683.746449 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 4004 99.50% 99.50% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-2047 7 0.17% 99.68% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2048-3071 3 0.07% 99.75% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.80% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::4096-5119 1 0.02% 99.83% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::7168-8191 2 0.05% 99.88% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::8192-9215 2 0.05% 99.93% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 4024 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4024 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.463966 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.422591 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.272940 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3359 83.47% 83.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 14 0.35% 83.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 449 11.16% 94.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 91 2.26% 97.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 36 0.89% 98.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 19 0.47% 98.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 14 0.35% 98.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 17 0.42% 99.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 8 0.20% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 6 0.15% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 4 0.10% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::27 5 0.12% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4024 # Writes before turning the bus around for reads
< system.physmem.totQLat 9384520258 # Total ticks spent queuing
< system.physmem.totMemAccLat 15289964008 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1574785000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 29796.20 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 136638 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 178.677557 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 128.806703 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 198.419690 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 53973 39.50% 39.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 57563 42.13% 81.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 14775 10.81% 92.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 1288 0.94% 93.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 1420 1.04% 94.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1465 1.07% 95.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1207 0.88% 96.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1190 0.87% 97.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 3757 2.75% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 136638 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 68.784581 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 34.732770 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 517.054396 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 4014 99.50% 99.50% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-2047 8 0.20% 99.70% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2048-3071 5 0.12% 99.83% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::7168-8191 3 0.07% 99.93% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.95% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::19456-20479 1 0.02% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.418691 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.384198 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.147646 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3405 84.41% 84.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 7 0.17% 84.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 450 11.16% 95.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 75 1.86% 97.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 34 0.84% 98.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 21 0.52% 98.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 13 0.32% 99.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 12 0.30% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 6 0.15% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 6 0.15% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 3 0.07% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::27 2 0.05% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads
> system.physmem.totQLat 9487812639 # Total ticks spent queuing
> system.physmem.totMemAccLat 15399143889 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1576355000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 30094.15 # Average queueing delay per DRAM burst
253,257c249,253
< system.physmem.avgMemAccLat 48546.20 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 49.40 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 49.45 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 48844.15 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 49.29 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 49.33 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 10.37 # Average system write bandwidth in MiByte/s
263,266c259,262
< system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing
< system.physmem.readRowHits 218395 # Number of row buffer hits during reads
< system.physmem.writeRowHits 26455 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 69.34 # Row buffer hit rate for reads
---
> system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing
> system.physmem.readRowHits 218399 # Number of row buffer hits during reads
> system.physmem.writeRowHits 26454 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads
268,280c264,276
< system.physmem.avgGap 1069341.38 # Average gap between requests
< system.physmem.pageHitRate 64.23 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 517708800 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 282480000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1231869600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 216613440 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 96151044510 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 160475521500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 285525816090 # Total energy per rank (pJ)
< system.physmem_0.averagePower 699.765171 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 266332221673 # Time in different power states
< system.physmem_0.memoryStateTime::REF 13625040000 # Time in different power states
---
> system.physmem.avgGap 1072046.17 # Average gap between requests
> system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 517640760 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 282442875 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1231518600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 216464400 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 96784987680 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 160736987250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 286509617805 # Total energy per rank (pJ)
> system.physmem_0.averagePower 699.839198 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 266762765318 # Time in different power states
> system.physmem_0.memoryStateTime::REF 13670540000 # Time in different power states
282c278
< system.physmem_0.memoryStateTime::ACT 128074629327 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 128960598682 # Time in different power states
284,294c280,290
< system.physmem_1.actEnergy 512870400 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 279840000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1224147600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 212693040 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 96078218175 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 160539404250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 285497751705 # Total energy per rank (pJ)
< system.physmem_1.averagePower 699.696391 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 266439995679 # Time in different power states
< system.physmem_1.memoryStateTime::REF 13625040000 # Time in different power states
---
> system.physmem_1.actEnergy 515168640 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 281094000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1226955600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 96280028955 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 161179933500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 286435482375 # Total energy per rank (pJ)
> system.physmem_1.averagePower 699.658112 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 267502793659 # Time in different power states
> system.physmem_1.memoryStateTime::REF 13670540000 # Time in different power states
296c292
< system.physmem_1.memoryStateTime::ACT 127966985321 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 128220707341 # Time in different power states
298,302c294,298
< system.cpu.branchPred.lookups 233958621 # Number of BP lookups
< system.cpu.branchPred.condPredicted 161821709 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 15514987 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 121572023 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 108258061 # Number of BTB hits
---
> system.cpu.branchPred.lookups 234006176 # Number of BP lookups
> system.cpu.branchPred.condPredicted 161868409 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 15514584 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 121529948 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 108213709 # Number of BTB hits
304,306c300,302
< system.cpu.branchPred.BTBHitPct 89.048498 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 25035636 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1300514 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 89.042833 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 25036783 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1300149 # Number of incorrect RAS predictions.
425c421
< system.cpu.numCycles 816074400 # number of cpu cycles simulated
---
> system.cpu.numCycles 818798961 # number of cpu cycles simulated
428,434c424,430
< system.cpu.fetch.icacheStallCycles 84077011 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 1200073954 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 233958621 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 133293697 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 716167787 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 31064641 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 2347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.icacheStallCycles 84078294 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 1200783068 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 234006176 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 133250492 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 718844861 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 31063585 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 2466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
436,441c432,437
< system.cpu.fetch.IcacheWaitRetryStallCycles 2996 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 370071850 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 652472 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 815782492 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.838759 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.161594 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 3349 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 370656305 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 652882 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 818460793 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.833394 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.163540 # Number of instructions fetched each cycle (Total)
443,446c439,442
< system.cpu.fetch.rateDist::0 134746116 16.52% 16.52% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 222503118 27.27% 43.79% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 98075778 12.02% 55.81% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 360457480 44.19% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 136795118 16.71% 16.71% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 223180654 27.27% 43.98% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 98074923 11.98% 55.96% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 360410098 44.04% 100.00% # Number of instructions fetched each cycle (Total)
450,477c446,473
< system.cpu.fetch.rateDist::total 815782492 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.286688 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.470545 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 119982553 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 156985722 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 484662665 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 38632910 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 15518642 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 25180928 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 13826 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 1248143840 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 39966741 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 15518642 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 176992343 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 77462427 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 207446 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 464957580 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 80644054 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 1190653894 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 25546220 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 24993767 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 2267123 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 40253162 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 1738390 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 1225396904 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 5812470532 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1358186197 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 40876541 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 818460793 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.285792 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.466518 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 119991092 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 159658898 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 484662986 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 38629701 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 15518116 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 25135087 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 13824 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 1248129900 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 39966537 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 15518116 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 176998470 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 78894904 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 210510 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 464956548 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 81882245 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 1190637892 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 25457774 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 24955109 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 2267146 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 41533192 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 1699566 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 1225425199 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 5812490436 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1358169789 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 40876588 # Number of floating rename lookups
479c475
< system.cpu.rename.UndoneMaps 350618674 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 350646969 # Number of HB maps that are undone due to squashing
482,487c478,483
< system.cpu.rename.skidInsts 108147318 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 366118935 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 236099157 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1781337 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 5349105 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 1168566408 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.rename.skidInsts 108140115 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 366205100 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 236096667 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1646330 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 5328678 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 1168639452 # Number of instructions added to the IQ (excludes non-spec)
489,492c485,488
< system.cpu.iq.iqInstsIssued 1017104063 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 18374377 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 379747029 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 1032159170 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 1017122920 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 18523621 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 379819992 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 1032577011 # Number of squashed operands that are examined and possibly removed from graph
494,496c490,492
< system.cpu.iq.issued_per_cycle::samples 815782492 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.246783 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 818460793 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.242727 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.084979 # Number of insts issued each cycle
498,502c494,498
< system.cpu.iq.issued_per_cycle::0 258071655 31.63% 31.63% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 228431382 28.00% 59.64% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 215339964 26.40% 86.03% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 97765220 11.98% 98.02% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 16174262 1.98% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 260810349 31.87% 31.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 227739162 27.83% 59.69% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 216495712 26.45% 86.14% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 97269955 11.88% 98.03% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 16145606 1.97% 100.00% # Number of insts issued each cycle
510c506
< system.cpu.iq.issued_per_cycle::total 815782492 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 818460793 # Number of insts issued each cycle
512,542c508,538
< system.cpu.iq.fu_full::IntAlu 64513595 19.12% 19.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 18145 0.01% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 155496772 46.10% 65.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 116668709 34.59% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 64512117 19.12% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 18144 0.01% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.31% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 155573719 46.11% 65.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 116674794 34.58% 100.00% # attempts to use FU when none available
546,547c542,543
< system.cpu.iq.FU_type_0::IntAlu 456384260 44.87% 44.87% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5195827 0.51% 45.38% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 456371749 44.87% 44.87% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued
571c567
< system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued
575,576c571,572
< system.cpu.iq.FU_type_0::MemRead 322085949 31.67% 78.80% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 215583681 21.20% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 322115143 31.67% 78.80% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 215585851 21.20% 100.00% # Type of FU issued
579,591c575,587
< system.cpu.iq.FU_type_0::total 1017104063 # Type of FU issued
< system.cpu.iq.rate 1.246337 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 337334110 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.331661 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 3143822052 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 1504778489 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 934283929 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 61877053 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 43565817 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 1320627818 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 33810355 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 9960647 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 1017122920 # Type of FU issued
> system.cpu.iq.rate 1.242213 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 337415663 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.331735 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 3146768879 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 1504924384 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 934270592 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 61877038 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 43565805 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 1320728240 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 33810343 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 9960122 # Number of loads that had data forwarded from stores
593,596c589,592
< system.cpu.iew.lsq.thread0.squashedLoads 113877997 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 1254 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 18512 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 107118661 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 113964162 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 1106 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 18388 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 107116171 # Number of stores squashed
599,600c595,596
< system.cpu.iew.lsq.thread0.rescheduledLoads 2065827 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 22129 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 2065787 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 22375 # Number of times an access to memory failed due to the cache being blocked
602,605c598,601
< system.cpu.iew.iewSquashCycles 15518642 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 35326933 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 672265 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 1168584324 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 15518116 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 35326355 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 41902 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 1168657365 # Number of instructions dispatched to IQ
607,608c603,604
< system.cpu.iew.iewDispLoadInsts 366118935 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 236099157 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 366205100 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 236096667 # Number of dispatched store instructions
610,618c606,614
< system.cpu.iew.iewIQFullEvents 110 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 675878 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 18512 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 15437821 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3784778 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 19222599 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 974764839 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 303299768 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 42339224 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewIQFullEvents 109 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 45517 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 18388 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 15437362 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3784555 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 19221917 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 974750423 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 42372497 # Number of squashed instructions skipped in execute
620,628c616,624
< system.cpu.iew.exec_nop 5556 # number of nop insts executed
< system.cpu.iew.exec_refs 497763810 # number of memory reference insts executed
< system.cpu.iew.exec_branches 150614661 # Number of branches executed
< system.cpu.iew.exec_stores 194464042 # Number of stores executed
< system.cpu.iew.exec_rate 1.194456 # Inst execution rate
< system.cpu.iew.wb_sent 963735760 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 960436373 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 536684839 # num instructions producing a value
< system.cpu.iew.wb_consumers 893296754 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 5553 # number of nop insts executed
> system.cpu.iew.exec_refs 497763737 # number of memory reference insts executed
> system.cpu.iew.exec_branches 150613650 # Number of branches executed
> system.cpu.iew.exec_stores 194466026 # Number of stores executed
> system.cpu.iew.exec_rate 1.190464 # Inst execution rate
> system.cpu.iew.wb_sent 963723367 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 960423035 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 536681402 # num instructions producing a value
> system.cpu.iew.wb_consumers 893284482 # num instructions consuming a value
630,631c626,627
< system.cpu.iew.wb_rate 1.176898 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.600791 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.172966 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back
633c629
< system.cpu.commit.commitSquashedInsts 357425480 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 357409752 # The number of squashed insts skipped by commit
635,638c631,634
< system.cpu.commit.branchMispredicts 15501309 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 764959828 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.031074 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.790810 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 15500908 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 767640271 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.027474 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.786859 # Number of insts commited each cycle
640,648c636,644
< system.cpu.commit.committed_per_cycle::0 428887379 56.07% 56.07% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 171843268 22.46% 78.53% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 73566556 9.62% 88.15% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 31622898 4.13% 92.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 7902308 1.03% 93.32% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 14889162 1.95% 95.26% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 7268582 0.95% 96.21% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 6618939 0.87% 97.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 22360736 2.92% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 430932808 56.14% 56.14% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 172476946 22.47% 78.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 73566678 9.58% 88.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 31624021 4.12% 92.31% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 8540196 1.11% 93.42% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 14250754 1.86% 95.28% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 7269409 0.95% 96.22% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 6618976 0.86% 97.09% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 22360483 2.91% 100.00% # Number of insts commited each cycle
652c648
< system.cpu.commit.committed_per_cycle::total 764959828 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 767640271 # Number of insts commited each cycle
698c694
< system.cpu.commit.bw_lim_events 22360736 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 22360483 # number cycles where commit BW limit reached
700,703c696,699
< system.cpu.rob.rob_reads 1888745890 # The number of ROB reads
< system.cpu.rob.rob_writes 2343137518 # The number of ROB writes
< system.cpu.timesIdled 647360 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 291908 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 1891410858 # The number of ROB reads
> system.cpu.rob.rob_writes 2343104087 # The number of ROB writes
> system.cpu.timesIdled 647398 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 338168 # Total number of cycles that the CPU has spent unscheduled due to idling
706,712c702,708
< system.cpu.cpi 1.273824 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.273824 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.785038 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.785038 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 995816176 # number of integer regfile reads
< system.cpu.int_regfile_writes 567918829 # number of integer regfile writes
< system.cpu.fp_regfile_reads 31889844 # number of floating regfile reads
---
> system.cpu.cpi 1.278077 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.278077 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.782426 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.782426 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 995803851 # number of integer regfile reads
> system.cpu.int_regfile_writes 567906934 # number of integer regfile writes
> system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads
714,716c710,712
< system.cpu.cc_regfile_reads 3794477294 # number of cc regfile reads
< system.cpu.cc_regfile_writes 384905750 # number of cc regfile writes
< system.cpu.misc_regfile_reads 715814324 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 3794434058 # number of cc regfile reads
> system.cpu.cc_regfile_writes 384899317 # number of cc regfile writes
> system.cpu.misc_regfile_reads 715816288 # number of misc regfile reads
718,726c714,722
< system.cpu.dcache.tags.replacements 2756166 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.936576 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 414250087 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 2756678 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 150.271481 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 246939500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.936576 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999876 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999876 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.replacements 2756182 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.932940 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 414226912 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 2756694 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 150.262202 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.932940 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy
728,730c724,726
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 189 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id
733,740c729,736
< system.cpu.dcache.tags.tag_accesses 839347788 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 839347788 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 286297988 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 286297988 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 127937398 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 127937398 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 3156 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 3156 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 839344268 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 839344268 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 286295518 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 286295518 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 127916671 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 127916671 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 3177 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 3177 # number of SoftPFReq hits
745,754c741,750
< system.cpu.dcache.demand_hits::cpu.data 414235386 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 414235386 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 414238542 # number of overall hits
< system.cpu.dcache.overall_hits::total 414238542 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 3030809 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 3030809 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1014079 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1014079 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 414212189 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 414212189 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 414215366 # number of overall hits
> system.cpu.dcache.overall_hits::total 414215366 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 3031489 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 3031489 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1034806 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1034806 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses
757,772c753,768
< system.cpu.dcache.demand_misses::cpu.data 4044888 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4044888 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4045534 # number of overall misses
< system.cpu.dcache.overall_misses::total 4045534 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 33766010929 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 33766010929 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9872401734 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9872401734 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 175500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 175500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 43638412663 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 43638412663 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 43638412663 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 43638412663 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 289328797 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 289328797 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 4066295 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4066295 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4066942 # number of overall misses
> system.cpu.dcache.overall_misses::total 4066942 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 35316006617 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 35316006617 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10004118304 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10004118304 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 202750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 202750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 45320124921 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 45320124921 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 45320124921 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 45320124921 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 289327007 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 289327007 # number of ReadReq accesses(hits+misses)
775,776c771,772
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 3802 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 3802 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 3824 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 3824 # number of SoftPFReq accesses(hits+misses)
781,790c777,786
< system.cpu.dcache.demand_accesses::cpu.data 418280274 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 418280274 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 418284076 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 418284076 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010475 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.010475 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007864 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.007864 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169911 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.169911 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 418278484 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 418278484 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 418282308 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 418282308 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.008025 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169195 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.169195 # miss rate for SoftPFReq accesses
793,806c789,802
< system.cpu.dcache.demand_miss_rate::cpu.data 0.009670 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.009670 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.009672 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.009672 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11140.923407 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 11140.923407 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9735.337912 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 9735.337912 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58500 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58500 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 10788.534235 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 10788.534235 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 10786.811497 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 10786.811497 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11649.722832 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 11649.722832 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9667.626883 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 9667.626883 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67583.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67583.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 11145.311622 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 11145.311622 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 11143.538541 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 11143.538541 # average overall miss latency
808c804
< system.cpu.dcache.blocked_cycles::no_targets 383706 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 349732 # number of cycles access was blocked
810c806
< system.cpu.dcache.blocked::no_targets 5260 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_targets 5194 # number of cycles access was blocked
812c808
< system.cpu.dcache.avg_blocked_cycles::no_targets 72.947909 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 67.333847 # average number of cycles each access was blocked
815,820c811,816
< system.cpu.dcache.writebacks::writebacks 735128 # number of writebacks
< system.cpu.dcache.writebacks::total 735128 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995619 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 995619 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293215 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 293215 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 735277 # number of writebacks
> system.cpu.dcache.writebacks::total 735277 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996280 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 996280 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313945 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 313945 # number of WriteReq MSHR hits
823,830c819,826
< system.cpu.dcache.demand_mshr_hits::cpu.data 1288834 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1288834 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1288834 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1288834 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035190 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 2035190 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720864 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 720864 # number of WriteReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 1310225 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1310225 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1310225 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1310225 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720861 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 720861 # number of WriteReq MSHR misses
833,846c829,842
< system.cpu.dcache.demand_mshr_misses::cpu.data 2756054 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2756054 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2756695 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2756695 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21052594116 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 21052594116 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5256752100 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5256752100 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5684476 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5684476 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26309346216 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26309346216 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26315030692 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26315030692 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 2756070 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2756070 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2756711 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2756711 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23121613833 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 23121613833 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5599042571 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5599042571 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5366500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5366500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28720656404 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 28720656404 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28726022904 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28726022904 # number of overall MSHR miss cycles
851,852c847,848
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168595 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168595 # mshr miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167626 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167626 # mshr miss rate for SoftPFReq accesses
855,866c851,862
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10344.289288 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10344.289288 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7292.293831 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7292.293831 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8868.137285 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8868.137285 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9546.019859 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 9546.019859 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9545.862234 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 9545.862234 # average overall mshr miss latency
---
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11360.805614 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11360.805614 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7767.159787 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7767.159787 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8372.074883 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8372.074883 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10420.873346 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 10420.873346 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10420.396953 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 10420.396953 # average overall mshr miss latency
868,876c864,872
< system.cpu.icache.tags.replacements 5169210 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.721915 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 364899992 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 5169720 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 70.584092 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 237857250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.721915 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.997504 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.997504 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 5169874 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.641329 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 365482216 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 5170384 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 70.687635 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 247770250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.641329 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.997346 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.997346 # Average percentage of cache occupancy
878c874
< system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
881c877
< system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id
883,926c879,922
< system.cpu.icache.tags.tag_accesses 745313375 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 745313375 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 364900028 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 364900028 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 364900028 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 364900028 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 364900028 # number of overall hits
< system.cpu.icache.overall_hits::total 364900028 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 5171791 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 5171791 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 5171791 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 5171791 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 5171791 # number of overall misses
< system.cpu.icache.overall_misses::total 5171791 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 41611685167 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 41611685167 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 41611685167 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 41611685167 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 41611685167 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 41611685167 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 370071819 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 370071819 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 370071819 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 370071819 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 370071819 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 370071819 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8045.894578 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 8045.894578 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 8045.894578 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 8045.894578 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 67339 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 2239 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 30.075480 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 9.750000 # average number of cycles each access was blocked
---
> system.cpu.icache.tags.tag_accesses 746482947 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 746482947 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 365482251 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 365482251 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 365482251 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 365482251 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 365482251 # number of overall hits
> system.cpu.icache.overall_hits::total 365482251 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 5174022 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 5174022 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 5174022 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 5174022 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 5174022 # number of overall misses
> system.cpu.icache.overall_misses::total 5174022 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 41654200685 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 41654200685 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 41654200685 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 41654200685 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 41654200685 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 41654200685 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 370656273 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 370656273 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 370656273 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 370656273 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 370656273 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 370656273 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013959 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.013959 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.013959 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.013959 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.013959 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.013959 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8050.642360 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 8050.642360 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 8050.642360 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 8050.642360 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 76485 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 24.358280 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
929,958c925,954
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169737 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 5169737 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 5169737 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 5169737 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 5169737 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 5169737 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33819004202 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 33819004202 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33819004202 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 33819004202 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33819004202 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 33819004202 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6541.726243 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6541.726243 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6541.726243 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 6541.726243 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6541.726243 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 6541.726243 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3620 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 3620 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 3620 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 3620 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 3620 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 3620 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170402 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 5170402 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 5170402 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 5170402 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 5170402 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 5170402 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36439121179 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 36439121179 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36439121179 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 36439121179 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36439121179 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 36439121179 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013949 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.013949 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.013949 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7047.637917 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7047.637917 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7047.637917 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 7047.637917 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7047.637917 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 7047.637917 # average overall mshr miss latency
960,962c956,958
< system.cpu.l2cache.prefetcher.num_hwpf_issued 1345350 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 1355301 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 8714 # number of redundant prefetches already in prefetch queue
---
> system.cpu.l2cache.prefetcher.num_hwpf_issued 1347058 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 1355234 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 7153 # number of redundant prefetches already in prefetch queue
965,1039c961,1035
< system.cpu.l2cache.prefetcher.pfSpanPage 4790331 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.replacements 298968 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 16361.863198 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 7823723 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 315332 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 24.811066 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 13372026000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 741.351492 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 129.669964 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 8767.936523 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6722.905220 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.045249 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007914 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.535152 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410334 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.998649 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 6534 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 9830 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1473 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4885 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2092 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7253 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.398804 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.599976 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 139620886 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 139620886 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 5166160 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1926359 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 7092519 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 735128 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 735128 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 717996 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 717996 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 5166160 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 2644355 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 7810515 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 5166160 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 2644355 # number of overall hits
< system.cpu.l2cache.overall_hits::total 7810515 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 3561 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 109472 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 113033 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 2851 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 2851 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 3561 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 112323 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 115884 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3561 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 112323 # number of overall misses
< system.cpu.l2cache.overall_misses::total 115884 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 237049229 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7458222067 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 7695271296 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 224011514 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 224011514 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 237049229 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7682233581 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 7919282810 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 237049229 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7682233581 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 7919282810 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 5169721 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 2035831 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 7205552 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 735128 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 735128 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.prefetcher.pfSpanPage 4790478 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.replacements 299258 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 16361.552831 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 7824313 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 315622 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 24.790138 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 13409363000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 738.976811 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 129.067019 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 8785.583028 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6707.925973 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.045104 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007878 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.536229 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.409419 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.998630 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 6482 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 9882 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 155 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1470 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4840 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2079 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7315 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.395630 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.603149 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 139634451 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 139634451 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 5166743 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1926167 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 7092910 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 735277 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 735277 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 718012 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 718012 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 5166743 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 2644179 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 7810922 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 5166743 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 2644179 # number of overall hits
> system.cpu.l2cache.overall_hits::total 7810922 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 3643 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 109683 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 113326 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 2832 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 2832 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 112515 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 116158 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 112515 # number of overall misses
> system.cpu.l2cache.overall_misses::total 116158 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 270029959 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8565404562 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 8835434521 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 207607487 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 207607487 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 270029959 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8773012049 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 9043042008 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 270029959 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8773012049 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 9043042008 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170386 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 2035850 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 7206236 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 735277 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 735277 # number of Writeback accesses(hits+misses)
1042,1073c1038,1069
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 5169721 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 2756678 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 7926399 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 5169721 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 2756678 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 7926399 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053773 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.015687 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823529 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823529 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003955 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.003955 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.040746 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.014620 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.040746 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.014620 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66568.163156 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68129.038174 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68079.864252 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78572.961768 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78572.961768 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68338.017414 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68338.017414 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 720844 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 720844 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 5170386 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 2756694 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 7927080 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 5170386 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 2756694 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 7927080 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000705 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053876 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.015726 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.941176 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.941176 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003929 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.003929 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000705 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.040815 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.014653 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000705 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.040815 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.014653 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74122.964315 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.362189 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 77964.761140 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73307.728460 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73307.728460 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77851.219959 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77851.219959 # average overall miss latency
1082,1129c1078,1125
< system.cpu.l2cache.writebacks::writebacks 66324 # number of writebacks
< system.cpu.l2cache.writebacks::total 66324 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1342 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 1353 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1474 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 1474 # number of ReadExReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 2816 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 2816 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 2827 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3550 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108130 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 111680 # number of ReadReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202272 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 202272 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1377 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 1377 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3550 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 109507 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 113057 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3550 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 109507 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202272 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 315329 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205967021 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6469574626 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6675541647 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18462254833 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 84014 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 84014 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126131000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126131000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205967021 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6595705626 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6801672647 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205967021 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6595705626 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 25263927480 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053113 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015499 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.writebacks::writebacks 66326 # number of writebacks
> system.cpu.l2cache.writebacks::total 66326 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1303 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 1318 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1445 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 1445 # number of ReadExReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 2748 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 2763 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 2748 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 2763 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3628 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108380 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 112008 # number of ReadReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202241 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 202241 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3628 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 109767 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 113395 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3628 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 109767 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202241 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 315636 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 238098541 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7611970750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7850069291 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17087057356 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 219516 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 219516 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114561754 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114561754 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238098541 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7726532504 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 7964631045 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238098541 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7726532504 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 25051688401 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053236 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses
1132,1140c1128,1136
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823529 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823529 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.014305 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for overall accesses
1142,1158c1138,1154
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.039782 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58018.879155 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59831.449422 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59773.832799 # average ReadReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91274.397015 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91598.402324 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91598.402324 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60161.446412 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80119.264261 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.039817 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65628.043275 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70234.090699 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70084.898320 # average ReadReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84488.592105 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13719.750000 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13719.750000 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82596.794521 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82596.794521 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.938578 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79368.919898 # average overall mshr miss latency
1160,1163c1156,1159
< system.cpu.toL2Bus.trans_dist::ReadReq 7205568 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 7205568 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 735128 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 316987 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 7206252 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 7206251 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 735277 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 248818 # Transaction distribution
1166,1177c1162,1173
< system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339458 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248518 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 16587976 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330862144 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475584 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 554337728 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 317003 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 8978547 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.035305 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.184549 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 720844 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 720844 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340787 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248699 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 16589486 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330904640 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223486144 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 554390784 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 248834 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 8911208 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.027922 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.164749 # Request fanout histogram
1182,1185c1178,1179
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 8661560 96.47% 96.47% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 316987 3.53% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 8662390 97.21% 97.21% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 248818 2.79% 100.00% # Request fanout histogram
1187,1190c1181,1184
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 8978547 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 5065908000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 8911208 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 5066472000 # Layer occupancy (ticks)
1192c1186
< system.cpu.toL2Bus.respLayer0.occupancy 7755114990 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 7756152507 # Layer occupancy (ticks)
1194c1188
< system.cpu.toL2Bus.respLayer1.occupancy 4143326908 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 4138701196 # Layer occupancy (ticks)
1196,1206c1190,1200
< system.membus.trans_dist::ReadReq 313877 # Transaction distribution
< system.membus.trans_dist::ReadResp 313877 # Transaction distribution
< system.membus.trans_dist::Writeback 66324 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 14 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 14 # Transaction distribution
< system.membus.trans_dist::ReadExReq 1377 # Transaction distribution
< system.membus.trans_dist::ReadExResp 1377 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 696860 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 696860 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24420992 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 24420992 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadReq 314173 # Transaction distribution
> system.membus.trans_dist::ReadResp 314173 # Transaction distribution
> system.membus.trans_dist::Writeback 66326 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 16 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
> system.membus.trans_dist::ReadExReq 1387 # Transaction distribution
> system.membus.trans_dist::ReadExResp 1387 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697478 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 697478 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24440704 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 24440704 # Cumulative packet size per connected master and slave (bytes)
1208c1202
< system.membus.snoop_fanout::samples 381592 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 381902 # Request fanout histogram
1212c1206
< system.membus.snoop_fanout::0 381592 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 381902 100.00% 100.00% # Request fanout histogram
1217,1218c1211,1212
< system.membus.snoop_fanout::total 381592 # Request fanout histogram
< system.membus.reqLayer0.occupancy 993954700 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 381902 # Request fanout histogram
> system.membus.reqLayer0.occupancy 746879857 # Layer occupancy (ticks)
1220,1221c1214,1215
< system.membus.respLayer1.occupancy 2896150900 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 1648874306 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.4 # Layer utilization (%)