7,11c7,11
< host_inst_rate 111054 # Simulator instruction rate (inst/s)
< host_op_rate 151240 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 50501117 # Simulator tick rate (ticks/s)
< host_mem_usage 257896 # Number of bytes of host memory used
< host_seconds 12465.77 # Real time elapsed on the host
---
> host_inst_rate 106173 # Simulator instruction rate (inst/s)
> host_op_rate 144593 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 48281629 # Simulator tick rate (ticks/s)
> host_mem_usage 278772 # Number of bytes of host memory used
> host_seconds 13038.82 # Real time elapsed on the host
267,268c267,268
< system.physmem.totQLat 3804882250 # Total ticks spent queuing
< system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3804806750 # Total ticks spent queuing
> system.physmem.totMemAccLat 15248020500 # Total ticks spent from burst creation until serviced by the DRAM
271c271
< system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8012.65 # Average queueing delay per DRAM burst
274c274
< system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 32111.24 # Average memory access latency per DRAM burst
306c306
< system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1215457500 # Layer occupancy (ticks)
308c308
< system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4442862738 # Layer occupancy (ticks)
311,312c311,312
< system.cpu.branchPred.lookups 438247561 # Number of BP lookups
< system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 438247722 # Number of BP lookups
> system.cpu.branchPred.condPredicted 350864471 # Number of conditional branches predicted
314,315c314,315
< system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 248480162 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 229339460 # Number of BTB hits
317c317
< system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 92.296889 # BTB Hit Percentage
319a320,340
> system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
340a362,382
> system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
366,372c408,414
< system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.icacheStallCycles 354141020 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 2279761292 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 438247722 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 282255131 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 601258233 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 157188182 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 134732573 # Number of cycles fetch has spent blocked
377,379c419,421
< system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheSquashes 11658358 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 1216659303 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.575913 # Number of instructions fetched each cycle (Total)
382c424
< system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 615445842 50.58% 50.58% # Number of instructions fetched each cycle (Total)
387c429
< system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::5 44699403 3.67% 76.27% # Number of instructions fetched each cycle (Total)
394c436
< system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 1216659303 # Number of instructions fetched each cycle (Total)
396,402c438,444
< system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch
---
> system.cpu.fetch.rate 1.810670 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 405371770 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 106745247 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 560687148 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 17351012 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 126504126 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 44828011 # Number of times decode resolved a branch
404c446
< system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 3022924000 # Number of instructions handled by decode
406,412c448,454
< system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename
---
> system.cpu.rename.SquashCycles 126504126 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 441422956 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 38086039 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 457739 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 539750713 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 70437730 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 2941757147 # Number of instructions processed by rename
415,419c457,461
< system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups
---
> system.cpu.rename.LSQFullEvents 54385461 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 740 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 2930215043 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 14237570542 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 12151139431 # Number of integer rename lookups
422c464
< system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 937074953 # Number of HB maps that are undone due to squashing
425c467
< system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 179296103 # count of insts added to the skid buffer
430c472
< system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 2792666387 # Number of instructions added to the IQ (excludes non-spec)
432c474
< system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 2435151733 # Number of instructions issued
434,435c476,477
< system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 894813074 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 2341267254 # Number of squashed operands that are examined and possibly removed from graph
437c479
< system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 1216659303 # Number of insts issued each cycle
439c481
< system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::stdev 1.873340 # Number of insts issued each cycle
441,446c483,488
< system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 380682463 31.29% 31.29% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 183043299 15.04% 46.33% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 204121257 16.78% 63.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 169552429 13.94% 77.05% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 132904836 10.92% 87.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 92976040 7.64% 95.61% # Number of insts issued each cycle
448c490
< system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::7 12393775 1.02% 99.75% # Number of insts issued each cycle
453c495
< system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1216659303 # Number of insts issued each cycle
489c531
< system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 1104245990 45.35% 45.35% # Type of FU issued
522,523c564,565
< system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued
< system.cpu.iq.rate 1.934087 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 2435151733 # Type of FU issued
> system.cpu.iq.rate 1.934086 # Inst issue rate
526,528c568,570
< system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_reads 6065394864 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 3604907210 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 2250139818 # Number of integer instruction queue wakeup accesses
532c574
< system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 2459502901 # Number of integer alu accesses
543c585
< system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked
545c587
< system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing
---
> system.cpu.iew.iewSquashCycles 126504126 # Number of cycles IEW is squashing
548,549c590,591
< system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispatchedInsts 2792706809 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 1386483 # Number of squashed instructions skipped by dispatch
559,561c601,603
< system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 2359934527 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 794158761 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 75217206 # Number of squashed instructions skipped in execute
564c606
< system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 1217435347 # number of memory reference insts executed
568,571c610,613
< system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 1349155886 # num instructions producing a value
< system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value
---
> system.cpu.iew.wb_sent 2332318600 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 2306572921 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 1349155649 # num instructions producing a value
> system.cpu.iew.wb_consumers 2527421878 # num instructions consuming a value
573c615
< system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 1.831964 # insts written-back per cycle
576c618
< system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 907370579 # The number of squashed insts skipped by commit
579c621
< system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 1090155177 # Number of insts commited each cycle
583,587c625,629
< system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 449868742 41.27% 41.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 288583282 26.47% 67.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 95106533 8.72% 76.46% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 70222065 6.44% 82.90% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 46473839 4.26% 87.17% # Number of insts commited each cycle
589,590c631,632
< system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::6 15848509 1.45% 90.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 10986576 1.01% 91.66% # Number of insts commited each cycle
595c637
< system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 1090155177 # Number of insts commited each cycle
608,609c650,651
< system.cpu.rob.rob_reads 3791959297 # The number of ROB reads
< system.cpu.rob.rob_writes 5711929091 # The number of ROB writes
---
> system.cpu.rob.rob_reads 3791959363 # The number of ROB reads
> system.cpu.rob.rob_writes 5711929117 # The number of ROB writes
611c653
< system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 42411525 # Total number of cycles that the CPU has spent unscheduled due to idling
619,620c661,662
< system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads
< system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 11767673388 # number of integer regfile reads
> system.cpu.int_regfile_writes 2220511965 # number of integer regfile writes
623c665
< system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 1678583418 # number of misc regfile reads
746c788
< system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536897 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536898 # Average occupied blocks per requestor
791,792c833,834
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746587000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 30922805750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746506500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 30922725250 # number of ReadReq miss cycles
796,797c838,839
< system.cpu.l2cache.demand_miss_latency::cpu.data 35503981750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 35680200500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 35503901250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 35680120000 # number of demand (read+write) miss cycles
799,800c841,842
< system.cpu.l2cache.overall_miss_latency::cpu.data 35503981750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 35680200500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 35503901250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 35680120000 # number of overall miss cycles
830,831c872,873
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.965460 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 75622.152810 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.767421 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75621.955947 # average ReadReq miss latency
835,836c877,878
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75117.951153 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75117.781675 # average overall miss latency
838,839c880,881
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75117.951153 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75117.781675 # average overall miss latency
873,874c915,916
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686513500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832151250 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686438000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832075750 # number of ReadReq MSHR miss cycles
880,881c922,923
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611492250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29757130000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611416750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29757054500 # number of demand (read+write) MSHR miss cycles
883,884c925,926
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611492250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 29757130000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611416750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 29757054500 # number of overall MSHR miss cycles
899,900c941,942
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.362666 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.903220 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.176917 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.718572 # average ReadReq mshr miss latency
906,907c948,949
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency
909,910c951,952
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency
914c956
< system.cpu.dcache.tags.total_refs 971409274 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 971409331 # Total number of references to valid blocks.
916c958
< system.cpu.dcache.tags.avg_refs 631.989306 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 631.989343 # Average number of references to valid blocks.
928,931c970,973
< system.cpu.dcache.tags.tag_accesses 1949922006 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1949922006 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 1949922120 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1949922120 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 695282746 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 695282746 # number of ReadReq hits
938,941c980,983
< system.cpu.dcache.demand_hits::cpu.data 971375738 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 971375738 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 971375738 # number of overall hits
< system.cpu.dcache.overall_hits::total 971375738 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 971375795 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 971375795 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 971375795 # number of overall hits
> system.cpu.dcache.overall_hits::total 971375795 # number of overall hits
952,955c994,997
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415300557 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 80415300557 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619884416 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 58619884416 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415220057 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 80415220057 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619966916 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 58619966916 # number of WriteReq miss cycles
958,963c1000,1005
< system.cpu.dcache.demand_miss_latency::cpu.data 139035184973 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 139035184973 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 139035184973 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 139035184973 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 697236804 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 697236804 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 139035186973 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 139035186973 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 139035186973 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 139035186973 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 697236861 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 697236861 # number of ReadReq accesses(hits+misses)
970,973c1012,1015
< system.cpu.dcache.demand_accesses::cpu.data 974172482 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 974172482 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 974172482 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 974172482 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 974172539 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 974172539 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 974172539 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 974172539 # number of overall (read+write) accesses
984,987c1026,1029
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.774874 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.774874 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.845892 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.845892 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800 # average WriteReq miss latency
990,993c1032,1035
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 49713.232592 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 49713.232592 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 49713.233307 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 49713.233307 # average overall miss latency
1022,1023c1064,1065
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792151524 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792151524 # number of ReadReq MSHR miss cycles
1026,1029c1068,1071
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785646012 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 47785646012 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785646012 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 47785646012 # number of overall MSHR miss cycles
1038,1039c1080,1081
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800 # average ReadReq mshr miss latency
1042,1045c1084,1087
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency
< host_inst_rate 111054 # Simulator instruction rate (inst/s)
< host_op_rate 151240 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 50501117 # Simulator tick rate (ticks/s)
< host_mem_usage 257896 # Number of bytes of host memory used
< host_seconds 12465.77 # Real time elapsed on the host
---
> host_inst_rate 106173 # Simulator instruction rate (inst/s)
> host_op_rate 144593 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 48281629 # Simulator tick rate (ticks/s)
> host_mem_usage 278772 # Number of bytes of host memory used
> host_seconds 13038.82 # Real time elapsed on the host
267,268c267,268
< system.physmem.totQLat 3804882250 # Total ticks spent queuing
< system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3804806750 # Total ticks spent queuing
> system.physmem.totMemAccLat 15248020500 # Total ticks spent from burst creation until serviced by the DRAM
271c271
< system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8012.65 # Average queueing delay per DRAM burst
274c274
< system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 32111.24 # Average memory access latency per DRAM burst
306c306
< system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1215457500 # Layer occupancy (ticks)
308c308
< system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4442862738 # Layer occupancy (ticks)
311,312c311,312
< system.cpu.branchPred.lookups 438247561 # Number of BP lookups
< system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 438247722 # Number of BP lookups
> system.cpu.branchPred.condPredicted 350864471 # Number of conditional branches predicted
314,315c314,315
< system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 248480162 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 229339460 # Number of BTB hits
317c317
< system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 92.296889 # BTB Hit Percentage
319a320,340
> system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
340a362,382
> system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
366,372c408,414
< system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.icacheStallCycles 354141020 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 2279761292 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 438247722 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 282255131 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 601258233 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 157188182 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 134732573 # Number of cycles fetch has spent blocked
377,379c419,421
< system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheSquashes 11658358 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 1216659303 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.575913 # Number of instructions fetched each cycle (Total)
382c424
< system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 615445842 50.58% 50.58% # Number of instructions fetched each cycle (Total)
387c429
< system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::5 44699403 3.67% 76.27% # Number of instructions fetched each cycle (Total)
394c436
< system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 1216659303 # Number of instructions fetched each cycle (Total)
396,402c438,444
< system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch
---
> system.cpu.fetch.rate 1.810670 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 405371770 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 106745247 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 560687148 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 17351012 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 126504126 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 44828011 # Number of times decode resolved a branch
404c446
< system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 3022924000 # Number of instructions handled by decode
406,412c448,454
< system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename
---
> system.cpu.rename.SquashCycles 126504126 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 441422956 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 38086039 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 457739 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 539750713 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 70437730 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 2941757147 # Number of instructions processed by rename
415,419c457,461
< system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups
---
> system.cpu.rename.LSQFullEvents 54385461 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 740 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 2930215043 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 14237570542 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 12151139431 # Number of integer rename lookups
422c464
< system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 937074953 # Number of HB maps that are undone due to squashing
425c467
< system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 179296103 # count of insts added to the skid buffer
430c472
< system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 2792666387 # Number of instructions added to the IQ (excludes non-spec)
432c474
< system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 2435151733 # Number of instructions issued
434,435c476,477
< system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 894813074 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 2341267254 # Number of squashed operands that are examined and possibly removed from graph
437c479
< system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 1216659303 # Number of insts issued each cycle
439c481
< system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::stdev 1.873340 # Number of insts issued each cycle
441,446c483,488
< system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 380682463 31.29% 31.29% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 183043299 15.04% 46.33% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 204121257 16.78% 63.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 169552429 13.94% 77.05% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 132904836 10.92% 87.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 92976040 7.64% 95.61% # Number of insts issued each cycle
448c490
< system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::7 12393775 1.02% 99.75% # Number of insts issued each cycle
453c495
< system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1216659303 # Number of insts issued each cycle
489c531
< system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 1104245990 45.35% 45.35% # Type of FU issued
522,523c564,565
< system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued
< system.cpu.iq.rate 1.934087 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 2435151733 # Type of FU issued
> system.cpu.iq.rate 1.934086 # Inst issue rate
526,528c568,570
< system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_reads 6065394864 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 3604907210 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 2250139818 # Number of integer instruction queue wakeup accesses
532c574
< system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 2459502901 # Number of integer alu accesses
543c585
< system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked
545c587
< system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing
---
> system.cpu.iew.iewSquashCycles 126504126 # Number of cycles IEW is squashing
548,549c590,591
< system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispatchedInsts 2792706809 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 1386483 # Number of squashed instructions skipped by dispatch
559,561c601,603
< system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 2359934527 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 794158761 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 75217206 # Number of squashed instructions skipped in execute
564c606
< system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 1217435347 # number of memory reference insts executed
568,571c610,613
< system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 1349155886 # num instructions producing a value
< system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value
---
> system.cpu.iew.wb_sent 2332318600 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 2306572921 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 1349155649 # num instructions producing a value
> system.cpu.iew.wb_consumers 2527421878 # num instructions consuming a value
573c615
< system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 1.831964 # insts written-back per cycle
576c618
< system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 907370579 # The number of squashed insts skipped by commit
579c621
< system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 1090155177 # Number of insts commited each cycle
583,587c625,629
< system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 449868742 41.27% 41.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 288583282 26.47% 67.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 95106533 8.72% 76.46% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 70222065 6.44% 82.90% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 46473839 4.26% 87.17% # Number of insts commited each cycle
589,590c631,632
< system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::6 15848509 1.45% 90.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 10986576 1.01% 91.66% # Number of insts commited each cycle
595c637
< system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 1090155177 # Number of insts commited each cycle
608,609c650,651
< system.cpu.rob.rob_reads 3791959297 # The number of ROB reads
< system.cpu.rob.rob_writes 5711929091 # The number of ROB writes
---
> system.cpu.rob.rob_reads 3791959363 # The number of ROB reads
> system.cpu.rob.rob_writes 5711929117 # The number of ROB writes
611c653
< system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 42411525 # Total number of cycles that the CPU has spent unscheduled due to idling
619,620c661,662
< system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads
< system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 11767673388 # number of integer regfile reads
> system.cpu.int_regfile_writes 2220511965 # number of integer regfile writes
623c665
< system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 1678583418 # number of misc regfile reads
746c788
< system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536897 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536898 # Average occupied blocks per requestor
791,792c833,834
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746587000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 30922805750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746506500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 30922725250 # number of ReadReq miss cycles
796,797c838,839
< system.cpu.l2cache.demand_miss_latency::cpu.data 35503981750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 35680200500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 35503901250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 35680120000 # number of demand (read+write) miss cycles
799,800c841,842
< system.cpu.l2cache.overall_miss_latency::cpu.data 35503981750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 35680200500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 35503901250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 35680120000 # number of overall miss cycles
830,831c872,873
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.965460 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 75622.152810 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.767421 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75621.955947 # average ReadReq miss latency
835,836c877,878
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75117.951153 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75117.781675 # average overall miss latency
838,839c880,881
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75117.951153 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75117.781675 # average overall miss latency
873,874c915,916
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686513500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832151250 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686438000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832075750 # number of ReadReq MSHR miss cycles
880,881c922,923
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611492250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29757130000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611416750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29757054500 # number of demand (read+write) MSHR miss cycles
883,884c925,926
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611492250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 29757130000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611416750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 29757054500 # number of overall MSHR miss cycles
899,900c941,942
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.362666 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.903220 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.176917 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.718572 # average ReadReq mshr miss latency
906,907c948,949
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency
909,910c951,952
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency
914c956
< system.cpu.dcache.tags.total_refs 971409274 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 971409331 # Total number of references to valid blocks.
916c958
< system.cpu.dcache.tags.avg_refs 631.989306 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 631.989343 # Average number of references to valid blocks.
928,931c970,973
< system.cpu.dcache.tags.tag_accesses 1949922006 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1949922006 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 1949922120 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1949922120 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 695282746 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 695282746 # number of ReadReq hits
938,941c980,983
< system.cpu.dcache.demand_hits::cpu.data 971375738 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 971375738 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 971375738 # number of overall hits
< system.cpu.dcache.overall_hits::total 971375738 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 971375795 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 971375795 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 971375795 # number of overall hits
> system.cpu.dcache.overall_hits::total 971375795 # number of overall hits
952,955c994,997
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415300557 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 80415300557 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619884416 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 58619884416 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415220057 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 80415220057 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619966916 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 58619966916 # number of WriteReq miss cycles
958,963c1000,1005
< system.cpu.dcache.demand_miss_latency::cpu.data 139035184973 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 139035184973 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 139035184973 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 139035184973 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 697236804 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 697236804 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 139035186973 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 139035186973 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 139035186973 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 139035186973 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 697236861 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 697236861 # number of ReadReq accesses(hits+misses)
970,973c1012,1015
< system.cpu.dcache.demand_accesses::cpu.data 974172482 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 974172482 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 974172482 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 974172482 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 974172539 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 974172539 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 974172539 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 974172539 # number of overall (read+write) accesses
984,987c1026,1029
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.774874 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.774874 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.845892 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.845892 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800 # average WriteReq miss latency
990,993c1032,1035
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 49713.232592 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 49713.232592 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 49713.233307 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 49713.233307 # average overall miss latency
1022,1023c1064,1065
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792151524 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792151524 # number of ReadReq MSHR miss cycles
1026,1029c1068,1071
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785646012 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 47785646012 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785646012 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 47785646012 # number of overall MSHR miss cycles
1038,1039c1080,1081
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800 # average ReadReq mshr miss latency
1042,1045c1084,1087
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency