1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.640648 # Number of seconds simulated
4sim_ticks 640648369500 # Number of ticks simulated
5final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.640648 # Number of seconds simulated
4sim_ticks 640648369500 # Number of ticks simulated
5final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 107808 # Simulator instruction rate (inst/s)
8host_op_rate 146820 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 49890421 # Simulator tick rate (ticks/s)
10host_mem_usage 251704 # Number of bytes of host memory used
11host_seconds 12841.11 # Real time elapsed on the host
| 7host_inst_rate 92518 # Simulator instruction rate (inst/s)
8host_op_rate 125998 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 42814979 # Simulator tick rate (ticks/s)
10host_mem_usage 256100 # Number of bytes of host memory used
11host_seconds 14963.18 # Real time elapsed on the host
|
12sim_insts 1384370590 # Number of instructions simulated
13sim_ops 1885325342 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory
16system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
20system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 2432 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 472560 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 242954 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 47208174 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 47451128 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 474992 # Total number of read requests accepted by DRAM controller
38system.physmem.writeReqs 66098 # Total number of write requests accepted by DRAM controller
39system.physmem.readBursts 474992 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
40system.physmem.writeBursts 66098 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
41system.physmem.bytesRead 30399488 # Total number of bytes read from memory
42system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
43system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize()
44system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
45system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by write Q
46system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed
47system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::7 29441 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::8 29488 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::9 29488 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::10 29538 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::11 29646 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::12 29708 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::13 29815 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::14 29628 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::15 29804 # Track reads on a per bank basis
63system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::3 4148 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::4 4226 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::5 4225 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::6 4174 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::7 4096 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::8 4096 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::9 4096 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::10 4096 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::13 4096 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis
79system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
80system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
81system.physmem.totGap 640648293500 # Total gap between requests
82system.physmem.readPktSize::0 0 # Categorize read packet sizes
83system.physmem.readPktSize::1 0 # Categorize read packet sizes
84system.physmem.readPktSize::2 0 # Categorize read packet sizes
85system.physmem.readPktSize::3 0 # Categorize read packet sizes
86system.physmem.readPktSize::4 0 # Categorize read packet sizes
87system.physmem.readPktSize::5 0 # Categorize read packet sizes
88system.physmem.readPktSize::6 474992 # Categorize read packet sizes
89system.physmem.writePktSize::0 0 # Categorize write packet sizes
90system.physmem.writePktSize::1 0 # Categorize write packet sizes
91system.physmem.writePktSize::2 0 # Categorize write packet sizes
92system.physmem.writePktSize::3 0 # Categorize write packet sizes
93system.physmem.writePktSize::4 0 # Categorize write packet sizes
94system.physmem.writePktSize::5 0 # Categorize write packet sizes
95system.physmem.writePktSize::6 66098 # Categorize write packet sizes
96system.physmem.rdQLenPdf::0 407729 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::1 66641 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
128system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
160system.physmem.bytesPerActivate::samples 173268 # Bytes accessed per row activation
161system.physmem.bytesPerActivate::mean 199.789644 # Bytes accessed per row activation
162system.physmem.bytesPerActivate::gmean 132.514067 # Bytes accessed per row activation
163system.physmem.bytesPerActivate::stdev 508.333416 # Bytes accessed per row activation
164system.physmem.bytesPerActivate::64-65 59669 34.44% 34.44% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::128-129 42666 24.62% 59.06% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::192-193 39942 23.05% 82.11% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::256-257 25325 14.62% 96.73% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::320-321 291 0.17% 96.90% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::384-385 110 0.06% 96.96% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::448-449 103 0.06% 97.02% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::512-513 89 0.05% 97.07% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::576-577 94 0.05% 97.13% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::640-641 79 0.05% 97.17% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::704-705 78 0.05% 97.22% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::768-769 80 0.05% 97.26% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::832-833 70 0.04% 97.30% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::896-897 76 0.04% 97.35% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::960-961 80 0.05% 97.39% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::1024-1025 77 0.04% 97.44% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1216-1217 81 0.05% 97.57% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1280-1281 72 0.04% 97.61% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.66% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1408-1409 72 0.04% 97.70% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1472-1473 3310 1.91% 99.61% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1536-1537 3 0.00% 99.61% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1600-1601 3 0.00% 99.61% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.61% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::2240-2241 3 0.00% 99.62% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::2432-2433 4 0.00% 99.62% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::2560-2561 1 0.00% 99.62% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::2688-2689 3 0.00% 99.62% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::3136-3137 1 0.00% 99.63% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::3456-3457 1 0.00% 99.63% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::3648-3649 1 0.00% 99.63% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.68% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::total 173268 # Bytes accessed per row activation
219system.physmem.totQLat 1888421000 # Total cycles spent in queuing delays
220system.physmem.totMemAccLat 14966831000 # Sum of mem lat for all requests
221system.physmem.totBusLat 2374200000 # Total cycles spent in databus access
222system.physmem.totBankLat 10704210000 # Total cycles spent in bank access
223system.physmem.avgQLat 3976.96 # Average queueing delay per request
224system.physmem.avgBankLat 22542.77 # Average bank access latency per request
225system.physmem.avgBusLat 5000.00 # Average bus latency per request
226system.physmem.avgMemAccLat 31519.74 # Average memory access latency
227system.physmem.avgRdBW 47.45 # Average achieved read bandwidth in MB/s
228system.physmem.avgWrBW 6.60 # Average achieved write bandwidth in MB/s
229system.physmem.avgConsumedRdBW 47.45 # Average consumed read bandwidth in MB/s
230system.physmem.avgConsumedWrBW 6.60 # Average consumed write bandwidth in MB/s
231system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
232system.physmem.busUtil 0.42 # Data bus utilization in percentage
233system.physmem.avgRdQLen 0.02 # Average read queue length over time
234system.physmem.avgWrQLen 17.45 # Average write queue length over time
235system.physmem.readRowHits 318007 # Number of row buffer hits during reads
236system.physmem.writeRowHits 49644 # Number of row buffer hits during writes
237system.physmem.readRowHitRate 66.97 # Row buffer hit rate for reads
238system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes
239system.physmem.avgGap 1183995.81 # Average gap between requests
240system.membus.throughput 54054139 # Throughput (bytes/s)
241system.membus.trans_dist::ReadReq 408917 # Transaction distribution
242system.membus.trans_dist::ReadResp 408916 # Transaction distribution
243system.membus.trans_dist::Writeback 66098 # Transaction distribution
244system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution
245system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution
246system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
247system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
248system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024803 # Packet count per connected master and slave (bytes)
249system.membus.pkt_count::total 1024803 # Packet count per connected master and slave (bytes)
250system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629696 # Cumulative packet size per connected master and slave (bytes)
251system.membus.tot_pkt_size::total 34629696 # Cumulative packet size per connected master and slave (bytes)
252system.membus.data_through_bus 34629696 # Total data (bytes)
253system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
254system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks)
255system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
256system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks)
257system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
258system.cpu.branchPred.lookups 451070712 # Number of BP lookups
259system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted
260system.cpu.branchPred.condIncorrect 31575662 # Number of conditional branches incorrect
261system.cpu.branchPred.BTBLookups 266989928 # Number of BTB lookups
262system.cpu.branchPred.BTBHits 238695746 # Number of BTB hits
263system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
264system.cpu.branchPred.BTBHitPct 89.402528 # BTB Hit Percentage
265system.cpu.branchPred.usedRAS 53258278 # Number of times the RAS was used to get a target.
266system.cpu.branchPred.RASInCorrect 2806364 # Number of incorrect RAS predictions.
267system.cpu.dtb.inst_hits 0 # ITB inst hits
268system.cpu.dtb.inst_misses 0 # ITB inst misses
269system.cpu.dtb.read_hits 0 # DTB read hits
270system.cpu.dtb.read_misses 0 # DTB read misses
271system.cpu.dtb.write_hits 0 # DTB write hits
272system.cpu.dtb.write_misses 0 # DTB write misses
273system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
274system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
275system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
276system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
277system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
278system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
279system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
280system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
281system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
282system.cpu.dtb.read_accesses 0 # DTB read accesses
283system.cpu.dtb.write_accesses 0 # DTB write accesses
284system.cpu.dtb.inst_accesses 0 # ITB inst accesses
285system.cpu.dtb.hits 0 # DTB hits
286system.cpu.dtb.misses 0 # DTB misses
287system.cpu.dtb.accesses 0 # DTB accesses
288system.cpu.itb.inst_hits 0 # ITB inst hits
289system.cpu.itb.inst_misses 0 # ITB inst misses
290system.cpu.itb.read_hits 0 # DTB read hits
291system.cpu.itb.read_misses 0 # DTB read misses
292system.cpu.itb.write_hits 0 # DTB write hits
293system.cpu.itb.write_misses 0 # DTB write misses
294system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
295system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
296system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
297system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
298system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
299system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
300system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
301system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
302system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
303system.cpu.itb.read_accesses 0 # DTB read accesses
304system.cpu.itb.write_accesses 0 # DTB write accesses
305system.cpu.itb.inst_accesses 0 # ITB inst accesses
306system.cpu.itb.hits 0 # DTB hits
307system.cpu.itb.misses 0 # DTB misses
308system.cpu.itb.accesses 0 # DTB accesses
309system.cpu.workload.num_syscalls 1411 # Number of system calls
310system.cpu.numCycles 1281296740 # number of cpu cycles simulated
311system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
312system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
313system.cpu.fetch.icacheStallCycles 365834433 # Number of cycles fetch is stalled on an Icache miss
314system.cpu.fetch.Insts 2312845521 # Number of instructions fetch has processed
315system.cpu.fetch.Branches 451070712 # Number of branches that fetch encountered
316system.cpu.fetch.predictedBranches 291954024 # Number of branches that fetch has predicted taken
317system.cpu.fetch.Cycles 613483563 # Number of cycles fetch has run and was not squashing or blocked
318system.cpu.fetch.SquashCycles 162414515 # Number of cycles fetch has spent squashing
319system.cpu.fetch.BlockedCycles 128244265 # Number of cycles fetch has spent blocked
320system.cpu.fetch.MiscStallCycles 613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
321system.cpu.fetch.PendingTrapStallCycles 11411 # Number of stall cycles due to pending traps
322system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR
323system.cpu.fetch.CacheLines 346004157 # Number of cache lines fetched
324system.cpu.fetch.IcacheSquashes 12181247 # Number of outstanding Icache misses that were squashed
325system.cpu.fetch.rateDist::samples 1238361342 # Number of instructions fetched each cycle (Total)
326system.cpu.fetch.rateDist::mean 2.567207 # Number of instructions fetched each cycle (Total)
327system.cpu.fetch.rateDist::stdev 3.166964 # Number of instructions fetched each cycle (Total)
328system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
329system.cpu.fetch.rateDist::0 624922537 50.46% 50.46% # Number of instructions fetched each cycle (Total)
330system.cpu.fetch.rateDist::1 43984122 3.55% 54.02% # Number of instructions fetched each cycle (Total)
331system.cpu.fetch.rateDist::2 100783073 8.14% 62.15% # Number of instructions fetched each cycle (Total)
332system.cpu.fetch.rateDist::3 58015364 4.68% 66.84% # Number of instructions fetched each cycle (Total)
333system.cpu.fetch.rateDist::4 73986941 5.97% 72.81% # Number of instructions fetched each cycle (Total)
334system.cpu.fetch.rateDist::5 44117238 3.56% 76.38% # Number of instructions fetched each cycle (Total)
335system.cpu.fetch.rateDist::6 31886448 2.57% 78.95% # Number of instructions fetched each cycle (Total)
336system.cpu.fetch.rateDist::7 33644071 2.72% 81.67% # Number of instructions fetched each cycle (Total)
337system.cpu.fetch.rateDist::8 227021548 18.33% 100.00% # Number of instructions fetched each cycle (Total)
338system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
339system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
340system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
341system.cpu.fetch.rateDist::total 1238361342 # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.branchRate 0.352042 # Number of branch fetches per cycle
343system.cpu.fetch.rate 1.805082 # Number of inst fetches per cycle
344system.cpu.decode.IdleCycles 416001710 # Number of cycles decode is idle
345system.cpu.decode.BlockedCycles 101876756 # Number of cycles decode is blocked
346system.cpu.decode.RunCycles 574960463 # Number of cycles decode is running
347system.cpu.decode.UnblockCycles 14748325 # Number of cycles decode is unblocking
348system.cpu.decode.SquashCycles 130774088 # Number of cycles decode is squashing
349system.cpu.decode.BranchResolved 46845433 # Number of times decode resolved a branch
350system.cpu.decode.BranchMispred 13115 # Number of times decode detected a branch misprediction
351system.cpu.decode.DecodedInsts 3066767432 # Number of instructions handled by decode
352system.cpu.decode.SquashedInsts 27354 # Number of squashed instructions handled by decode
353system.cpu.rename.SquashCycles 130774088 # Number of cycles rename is squashing
354system.cpu.rename.IdleCycles 450873553 # Number of cycles rename is idle
355system.cpu.rename.BlockCycles 37362667 # Number of cycles rename is blocking
356system.cpu.rename.serializeStallCycles 459915 # count of cycles rename stalled for serializing inst
357system.cpu.rename.RunCycles 552824643 # Number of cycles rename is running
358system.cpu.rename.UnblockCycles 66066476 # Number of cycles rename is unblocking
359system.cpu.rename.RenamedInsts 2984722482 # Number of instructions processed by rename
360system.cpu.rename.ROBFullEvents 106 # Number of times rename has blocked due to ROB full
361system.cpu.rename.IQFullEvents 4345913 # Number of times rename has blocked due to IQ full
362system.cpu.rename.LSQFullEvents 52259250 # Number of times rename has blocked due to LSQ full
363system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers
364system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed
365system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made
| 12sim_insts 1384370590 # Number of instructions simulated
13sim_ops 1885325342 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory
16system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
20system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 2432 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 472560 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 242954 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 47208174 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 47451128 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 474992 # Total number of read requests accepted by DRAM controller
38system.physmem.writeReqs 66098 # Total number of write requests accepted by DRAM controller
39system.physmem.readBursts 474992 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
40system.physmem.writeBursts 66098 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
41system.physmem.bytesRead 30399488 # Total number of bytes read from memory
42system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
43system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize()
44system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
45system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by write Q
46system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed
47system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::7 29441 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::8 29488 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::9 29488 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::10 29538 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::11 29646 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::12 29708 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::13 29815 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::14 29628 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::15 29804 # Track reads on a per bank basis
63system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::3 4148 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::4 4226 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::5 4225 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::6 4174 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::7 4096 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::8 4096 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::9 4096 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::10 4096 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::13 4096 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis
79system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
80system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
81system.physmem.totGap 640648293500 # Total gap between requests
82system.physmem.readPktSize::0 0 # Categorize read packet sizes
83system.physmem.readPktSize::1 0 # Categorize read packet sizes
84system.physmem.readPktSize::2 0 # Categorize read packet sizes
85system.physmem.readPktSize::3 0 # Categorize read packet sizes
86system.physmem.readPktSize::4 0 # Categorize read packet sizes
87system.physmem.readPktSize::5 0 # Categorize read packet sizes
88system.physmem.readPktSize::6 474992 # Categorize read packet sizes
89system.physmem.writePktSize::0 0 # Categorize write packet sizes
90system.physmem.writePktSize::1 0 # Categorize write packet sizes
91system.physmem.writePktSize::2 0 # Categorize write packet sizes
92system.physmem.writePktSize::3 0 # Categorize write packet sizes
93system.physmem.writePktSize::4 0 # Categorize write packet sizes
94system.physmem.writePktSize::5 0 # Categorize write packet sizes
95system.physmem.writePktSize::6 66098 # Categorize write packet sizes
96system.physmem.rdQLenPdf::0 407729 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::1 66641 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
128system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
160system.physmem.bytesPerActivate::samples 173268 # Bytes accessed per row activation
161system.physmem.bytesPerActivate::mean 199.789644 # Bytes accessed per row activation
162system.physmem.bytesPerActivate::gmean 132.514067 # Bytes accessed per row activation
163system.physmem.bytesPerActivate::stdev 508.333416 # Bytes accessed per row activation
164system.physmem.bytesPerActivate::64-65 59669 34.44% 34.44% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::128-129 42666 24.62% 59.06% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::192-193 39942 23.05% 82.11% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::256-257 25325 14.62% 96.73% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::320-321 291 0.17% 96.90% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::384-385 110 0.06% 96.96% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::448-449 103 0.06% 97.02% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::512-513 89 0.05% 97.07% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::576-577 94 0.05% 97.13% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::640-641 79 0.05% 97.17% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::704-705 78 0.05% 97.22% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::768-769 80 0.05% 97.26% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::832-833 70 0.04% 97.30% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::896-897 76 0.04% 97.35% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::960-961 80 0.05% 97.39% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::1024-1025 77 0.04% 97.44% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1216-1217 81 0.05% 97.57% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1280-1281 72 0.04% 97.61% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.66% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1408-1409 72 0.04% 97.70% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1472-1473 3310 1.91% 99.61% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1536-1537 3 0.00% 99.61% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1600-1601 3 0.00% 99.61% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.61% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::2240-2241 3 0.00% 99.62% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::2432-2433 4 0.00% 99.62% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::2560-2561 1 0.00% 99.62% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::2688-2689 3 0.00% 99.62% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::3136-3137 1 0.00% 99.63% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::3456-3457 1 0.00% 99.63% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::3648-3649 1 0.00% 99.63% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.68% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::total 173268 # Bytes accessed per row activation
219system.physmem.totQLat 1888421000 # Total cycles spent in queuing delays
220system.physmem.totMemAccLat 14966831000 # Sum of mem lat for all requests
221system.physmem.totBusLat 2374200000 # Total cycles spent in databus access
222system.physmem.totBankLat 10704210000 # Total cycles spent in bank access
223system.physmem.avgQLat 3976.96 # Average queueing delay per request
224system.physmem.avgBankLat 22542.77 # Average bank access latency per request
225system.physmem.avgBusLat 5000.00 # Average bus latency per request
226system.physmem.avgMemAccLat 31519.74 # Average memory access latency
227system.physmem.avgRdBW 47.45 # Average achieved read bandwidth in MB/s
228system.physmem.avgWrBW 6.60 # Average achieved write bandwidth in MB/s
229system.physmem.avgConsumedRdBW 47.45 # Average consumed read bandwidth in MB/s
230system.physmem.avgConsumedWrBW 6.60 # Average consumed write bandwidth in MB/s
231system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
232system.physmem.busUtil 0.42 # Data bus utilization in percentage
233system.physmem.avgRdQLen 0.02 # Average read queue length over time
234system.physmem.avgWrQLen 17.45 # Average write queue length over time
235system.physmem.readRowHits 318007 # Number of row buffer hits during reads
236system.physmem.writeRowHits 49644 # Number of row buffer hits during writes
237system.physmem.readRowHitRate 66.97 # Row buffer hit rate for reads
238system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes
239system.physmem.avgGap 1183995.81 # Average gap between requests
240system.membus.throughput 54054139 # Throughput (bytes/s)
241system.membus.trans_dist::ReadReq 408917 # Transaction distribution
242system.membus.trans_dist::ReadResp 408916 # Transaction distribution
243system.membus.trans_dist::Writeback 66098 # Transaction distribution
244system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution
245system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution
246system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
247system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
248system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024803 # Packet count per connected master and slave (bytes)
249system.membus.pkt_count::total 1024803 # Packet count per connected master and slave (bytes)
250system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629696 # Cumulative packet size per connected master and slave (bytes)
251system.membus.tot_pkt_size::total 34629696 # Cumulative packet size per connected master and slave (bytes)
252system.membus.data_through_bus 34629696 # Total data (bytes)
253system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
254system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks)
255system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
256system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks)
257system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
258system.cpu.branchPred.lookups 451070712 # Number of BP lookups
259system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted
260system.cpu.branchPred.condIncorrect 31575662 # Number of conditional branches incorrect
261system.cpu.branchPred.BTBLookups 266989928 # Number of BTB lookups
262system.cpu.branchPred.BTBHits 238695746 # Number of BTB hits
263system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
264system.cpu.branchPred.BTBHitPct 89.402528 # BTB Hit Percentage
265system.cpu.branchPred.usedRAS 53258278 # Number of times the RAS was used to get a target.
266system.cpu.branchPred.RASInCorrect 2806364 # Number of incorrect RAS predictions.
267system.cpu.dtb.inst_hits 0 # ITB inst hits
268system.cpu.dtb.inst_misses 0 # ITB inst misses
269system.cpu.dtb.read_hits 0 # DTB read hits
270system.cpu.dtb.read_misses 0 # DTB read misses
271system.cpu.dtb.write_hits 0 # DTB write hits
272system.cpu.dtb.write_misses 0 # DTB write misses
273system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
274system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
275system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
276system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
277system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
278system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
279system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
280system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
281system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
282system.cpu.dtb.read_accesses 0 # DTB read accesses
283system.cpu.dtb.write_accesses 0 # DTB write accesses
284system.cpu.dtb.inst_accesses 0 # ITB inst accesses
285system.cpu.dtb.hits 0 # DTB hits
286system.cpu.dtb.misses 0 # DTB misses
287system.cpu.dtb.accesses 0 # DTB accesses
288system.cpu.itb.inst_hits 0 # ITB inst hits
289system.cpu.itb.inst_misses 0 # ITB inst misses
290system.cpu.itb.read_hits 0 # DTB read hits
291system.cpu.itb.read_misses 0 # DTB read misses
292system.cpu.itb.write_hits 0 # DTB write hits
293system.cpu.itb.write_misses 0 # DTB write misses
294system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
295system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
296system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
297system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
298system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
299system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
300system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
301system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
302system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
303system.cpu.itb.read_accesses 0 # DTB read accesses
304system.cpu.itb.write_accesses 0 # DTB write accesses
305system.cpu.itb.inst_accesses 0 # ITB inst accesses
306system.cpu.itb.hits 0 # DTB hits
307system.cpu.itb.misses 0 # DTB misses
308system.cpu.itb.accesses 0 # DTB accesses
309system.cpu.workload.num_syscalls 1411 # Number of system calls
310system.cpu.numCycles 1281296740 # number of cpu cycles simulated
311system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
312system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
313system.cpu.fetch.icacheStallCycles 365834433 # Number of cycles fetch is stalled on an Icache miss
314system.cpu.fetch.Insts 2312845521 # Number of instructions fetch has processed
315system.cpu.fetch.Branches 451070712 # Number of branches that fetch encountered
316system.cpu.fetch.predictedBranches 291954024 # Number of branches that fetch has predicted taken
317system.cpu.fetch.Cycles 613483563 # Number of cycles fetch has run and was not squashing or blocked
318system.cpu.fetch.SquashCycles 162414515 # Number of cycles fetch has spent squashing
319system.cpu.fetch.BlockedCycles 128244265 # Number of cycles fetch has spent blocked
320system.cpu.fetch.MiscStallCycles 613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
321system.cpu.fetch.PendingTrapStallCycles 11411 # Number of stall cycles due to pending traps
322system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR
323system.cpu.fetch.CacheLines 346004157 # Number of cache lines fetched
324system.cpu.fetch.IcacheSquashes 12181247 # Number of outstanding Icache misses that were squashed
325system.cpu.fetch.rateDist::samples 1238361342 # Number of instructions fetched each cycle (Total)
326system.cpu.fetch.rateDist::mean 2.567207 # Number of instructions fetched each cycle (Total)
327system.cpu.fetch.rateDist::stdev 3.166964 # Number of instructions fetched each cycle (Total)
328system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
329system.cpu.fetch.rateDist::0 624922537 50.46% 50.46% # Number of instructions fetched each cycle (Total)
330system.cpu.fetch.rateDist::1 43984122 3.55% 54.02% # Number of instructions fetched each cycle (Total)
331system.cpu.fetch.rateDist::2 100783073 8.14% 62.15% # Number of instructions fetched each cycle (Total)
332system.cpu.fetch.rateDist::3 58015364 4.68% 66.84% # Number of instructions fetched each cycle (Total)
333system.cpu.fetch.rateDist::4 73986941 5.97% 72.81% # Number of instructions fetched each cycle (Total)
334system.cpu.fetch.rateDist::5 44117238 3.56% 76.38% # Number of instructions fetched each cycle (Total)
335system.cpu.fetch.rateDist::6 31886448 2.57% 78.95% # Number of instructions fetched each cycle (Total)
336system.cpu.fetch.rateDist::7 33644071 2.72% 81.67% # Number of instructions fetched each cycle (Total)
337system.cpu.fetch.rateDist::8 227021548 18.33% 100.00% # Number of instructions fetched each cycle (Total)
338system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
339system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
340system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
341system.cpu.fetch.rateDist::total 1238361342 # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.branchRate 0.352042 # Number of branch fetches per cycle
343system.cpu.fetch.rate 1.805082 # Number of inst fetches per cycle
344system.cpu.decode.IdleCycles 416001710 # Number of cycles decode is idle
345system.cpu.decode.BlockedCycles 101876756 # Number of cycles decode is blocked
346system.cpu.decode.RunCycles 574960463 # Number of cycles decode is running
347system.cpu.decode.UnblockCycles 14748325 # Number of cycles decode is unblocking
348system.cpu.decode.SquashCycles 130774088 # Number of cycles decode is squashing
349system.cpu.decode.BranchResolved 46845433 # Number of times decode resolved a branch
350system.cpu.decode.BranchMispred 13115 # Number of times decode detected a branch misprediction
351system.cpu.decode.DecodedInsts 3066767432 # Number of instructions handled by decode
352system.cpu.decode.SquashedInsts 27354 # Number of squashed instructions handled by decode
353system.cpu.rename.SquashCycles 130774088 # Number of cycles rename is squashing
354system.cpu.rename.IdleCycles 450873553 # Number of cycles rename is idle
355system.cpu.rename.BlockCycles 37362667 # Number of cycles rename is blocking
356system.cpu.rename.serializeStallCycles 459915 # count of cycles rename stalled for serializing inst
357system.cpu.rename.RunCycles 552824643 # Number of cycles rename is running
358system.cpu.rename.UnblockCycles 66066476 # Number of cycles rename is unblocking
359system.cpu.rename.RenamedInsts 2984722482 # Number of instructions processed by rename
360system.cpu.rename.ROBFullEvents 106 # Number of times rename has blocked due to ROB full
361system.cpu.rename.IQFullEvents 4345913 # Number of times rename has blocked due to IQ full
362system.cpu.rename.LSQFullEvents 52259250 # Number of times rename has blocked due to LSQ full
363system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers
364system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed
365system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made
|
366system.cpu.rename.int_rename_lookups 13600947598 # Number of integer rename lookups
367system.cpu.rename.fp_rename_lookups 607723883 # Number of floating rename lookups
| 366system.cpu.rename.int_rename_lookups 12321480350 # Number of integer rename lookups
367system.cpu.rename.fp_rename_lookups 90240197 # Number of floating rename lookups
|
368system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
369system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing
370system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed
371system.cpu.rename.tempSerializingInsts 18729 # count of temporary serializing insts renamed
372system.cpu.rename.skidInsts 172024073 # count of insts added to the skid buffer
373system.cpu.memDep0.insertedLoads 975055963 # Number of loads inserted to the mem dependence unit.
374system.cpu.memDep0.insertedStores 496398991 # Number of stores inserted to the mem dependence unit.
375system.cpu.memDep0.conflictingLoads 36275443 # Number of conflicting loads.
376system.cpu.memDep0.conflictingStores 40590257 # Number of conflicting stores.
377system.cpu.iq.iqInstsAdded 2826416078 # Number of instructions added to the IQ (excludes non-spec)
378system.cpu.iq.iqNonSpecInstsAdded 28152 # Number of non-speculative instructions added to the IQ
379system.cpu.iq.iqInstsIssued 2457324643 # Number of instructions issued
380system.cpu.iq.iqSquashedInstsIssued 15915709 # Number of squashed instructions issued
381system.cpu.iq.iqSquashedInstsExamined 928556403 # Number of squashed instructions iterated over during squash; mainly for profiling
382system.cpu.iq.iqSquashedOperandsExamined 2380098621 # Number of squashed operands that are examined and possibly removed from graph
383system.cpu.iq.iqSquashedNonSpecRemoved 6768 # Number of squashed non-spec instructions that were removed
384system.cpu.iq.issued_per_cycle::samples 1238361342 # Number of insts issued each cycle
385system.cpu.iq.issued_per_cycle::mean 1.984336 # Number of insts issued each cycle
386system.cpu.iq.issued_per_cycle::stdev 1.868331 # Number of insts issued each cycle
387system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
388system.cpu.iq.issued_per_cycle::0 394006079 31.82% 31.82% # Number of insts issued each cycle
389system.cpu.iq.issued_per_cycle::1 183256590 14.80% 46.62% # Number of insts issued each cycle
390system.cpu.iq.issued_per_cycle::2 205523874 16.60% 63.21% # Number of insts issued each cycle
391system.cpu.iq.issued_per_cycle::3 174394872 14.08% 77.29% # Number of insts issued each cycle
392system.cpu.iq.issued_per_cycle::4 137878376 11.13% 88.43% # Number of insts issued each cycle
393system.cpu.iq.issued_per_cycle::5 90899666 7.34% 95.77% # Number of insts issued each cycle
394system.cpu.iq.issued_per_cycle::6 36275985 2.93% 98.70% # Number of insts issued each cycle
395system.cpu.iq.issued_per_cycle::7 12839255 1.04% 99.73% # Number of insts issued each cycle
396system.cpu.iq.issued_per_cycle::8 3286645 0.27% 100.00% # Number of insts issued each cycle
397system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
398system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
399system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
400system.cpu.iq.issued_per_cycle::total 1238361342 # Number of insts issued each cycle
401system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
402system.cpu.iq.fu_full::IntAlu 691696 0.78% 0.78% # attempts to use FU when none available
403system.cpu.iq.fu_full::IntMult 24382 0.03% 0.81% # attempts to use FU when none available
404system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available
405system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available
406system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available
407system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available
408system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available
409system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available
410system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
411system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available
412system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available
413system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available
414system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available
415system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available
416system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available
417system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available
418system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available
419system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available
420system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available
421system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available
422system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available
423system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available
424system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available
425system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available
426system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available
427system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
431system.cpu.iq.fu_full::MemRead 55024342 62.24% 63.05% # attempts to use FU when none available
432system.cpu.iq.fu_full::MemWrite 32666949 36.95% 100.00% # attempts to use FU when none available
433system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
434system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
435system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
436system.cpu.iq.FU_type_0::IntAlu 1118619814 45.52% 45.52% # Type of FU issued
437system.cpu.iq.FU_type_0::IntMult 11223087 0.46% 45.98% # Type of FU issued
438system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued
439system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued
440system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued
441system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued
442system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued
443system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued
444system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued
445system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued
446system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued
447system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued
448system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued
449system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued
450system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued
451system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued
452system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued
453system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued
454system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued
455system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued
456system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.03% # Type of FU issued
457system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.03% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 46.31% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdFloatCvt 5501669 0.22% 46.54% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.54% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdFloatMisc 23389012 0.95% 47.49% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.49% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.49% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.49% # Type of FU issued
465system.cpu.iq.FU_type_0::MemRead 843037947 34.31% 81.80% # Type of FU issued
466system.cpu.iq.FU_type_0::MemWrite 447301347 18.20% 100.00% # Type of FU issued
467system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
468system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
469system.cpu.iq.FU_type_0::total 2457324643 # Type of FU issued
470system.cpu.iq.rate 1.917842 # Inst issue rate
471system.cpu.iq.fu_busy_cnt 88407369 # FU busy when requested
472system.cpu.iq.fu_busy_rate 0.035977 # FU busy rate (busy events/executed inst)
473system.cpu.iq.int_inst_queue_reads 6133604202 # Number of integer instruction queue reads
474system.cpu.iq.int_inst_queue_writes 3666175191 # Number of integer instruction queue writes
475system.cpu.iq.int_inst_queue_wakeup_accesses 2269813505 # Number of integer instruction queue wakeup accesses
476system.cpu.iq.fp_inst_queue_reads 123729504 # Number of floating instruction queue reads
477system.cpu.iq.fp_inst_queue_writes 88892403 # Number of floating instruction queue writes
478system.cpu.iq.fp_inst_queue_wakeup_accesses 56421926 # Number of floating instruction queue wakeup accesses
479system.cpu.iq.int_alu_accesses 2481804628 # Number of integer alu accesses
480system.cpu.iq.fp_alu_accesses 63927384 # Number of floating point alu accesses
481system.cpu.iew.lsq.thread0.forwLoads 85672552 # Number of loads that had data forwarded from stores
482system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
483system.cpu.iew.lsq.thread0.squashedLoads 343668782 # Number of loads squashed
484system.cpu.iew.lsq.thread0.ignoredResponses 27729 # Number of memory responses ignored because the instruction is squashed
485system.cpu.iew.lsq.thread0.memOrderViolation 1429255 # Number of memory ordering violations
486system.cpu.iew.lsq.thread0.squashedStores 219403694 # Number of stores squashed
487system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
488system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
489system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
490system.cpu.iew.lsq.thread0.cacheBlocked 304 # Number of times an access to memory failed due to the cache being blocked
491system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
492system.cpu.iew.iewSquashCycles 130774088 # Number of cycles IEW is squashing
493system.cpu.iew.iewBlockCycles 15649984 # Number of cycles IEW is blocking
494system.cpu.iew.iewUnblockCycles 1558990 # Number of cycles IEW is unblocking
495system.cpu.iew.iewDispatchedInsts 2826456693 # Number of instructions dispatched to IQ
496system.cpu.iew.iewDispSquashedInsts 641968 # Number of squashed instructions skipped by dispatch
497system.cpu.iew.iewDispLoadInsts 975055963 # Number of dispatched load instructions
498system.cpu.iew.iewDispStoreInsts 496398991 # Number of dispatched store instructions
499system.cpu.iew.iewDispNonSpecInsts 18166 # Number of dispatched non-speculative instructions
500system.cpu.iew.iewIQFullEvents 1553675 # Number of times the IQ has become full, causing a stall
501system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall
502system.cpu.iew.memOrderViolationEvents 1429255 # Number of memory order violations
503system.cpu.iew.predictedTakenIncorrect 33789507 # Number of branches that were predicted taken incorrectly
504system.cpu.iew.predictedNotTakenIncorrect 2118647 # Number of branches that were predicted not taken incorrectly
505system.cpu.iew.branchMispredicts 35908154 # Number of branch mispredicts detected at execute
506system.cpu.iew.iewExecutedInsts 2378923796 # Number of executed instructions
507system.cpu.iew.iewExecLoadInsts 796860173 # Number of load instructions executed
508system.cpu.iew.iewExecSquashedInsts 78400847 # Number of squashed instructions skipped in execute
509system.cpu.iew.exec_swp 0 # number of swp insts executed
510system.cpu.iew.exec_nop 12463 # number of nop insts executed
511system.cpu.iew.exec_refs 1223764024 # number of memory reference insts executed
512system.cpu.iew.exec_branches 324680497 # Number of branches executed
513system.cpu.iew.exec_stores 426903851 # Number of stores executed
514system.cpu.iew.exec_rate 1.856653 # Inst execution rate
515system.cpu.iew.wb_sent 2351973532 # cumulative count of insts sent to commit
516system.cpu.iew.wb_count 2326235431 # cumulative count of insts written-back
517system.cpu.iew.wb_producers 1354756756 # num instructions producing a value
518system.cpu.iew.wb_consumers 2530303455 # num instructions consuming a value
519system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
520system.cpu.iew.wb_rate 1.815532 # insts written-back per cycle
521system.cpu.iew.wb_fanout 0.535413 # average fanout of values written-back
522system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
523system.cpu.commit.commitSquashedInsts 941120455 # The number of squashed insts skipped by commit
524system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
525system.cpu.commit.branchMispredicts 31562826 # The number of times a branch was mispredicted
526system.cpu.commit.committed_per_cycle::samples 1107587254 # Number of insts commited each cycle
527system.cpu.commit.committed_per_cycle::mean 1.702201 # Number of insts commited each cycle
528system.cpu.commit.committed_per_cycle::stdev 2.378361 # Number of insts commited each cycle
529system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
530system.cpu.commit.committed_per_cycle::0 463154673 41.82% 41.82% # Number of insts commited each cycle
531system.cpu.commit.committed_per_cycle::1 291887882 26.35% 68.17% # Number of insts commited each cycle
532system.cpu.commit.committed_per_cycle::2 96478924 8.71% 76.88% # Number of insts commited each cycle
533system.cpu.commit.committed_per_cycle::3 70059146 6.33% 83.21% # Number of insts commited each cycle
534system.cpu.commit.committed_per_cycle::4 46846853 4.23% 87.44% # Number of insts commited each cycle
535system.cpu.commit.committed_per_cycle::5 22330225 2.02% 89.45% # Number of insts commited each cycle
536system.cpu.commit.committed_per_cycle::6 15798039 1.43% 90.88% # Number of insts commited each cycle
537system.cpu.commit.committed_per_cycle::7 11765677 1.06% 91.94% # Number of insts commited each cycle
538system.cpu.commit.committed_per_cycle::8 89265835 8.06% 100.00% # Number of insts commited each cycle
539system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
540system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
541system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
542system.cpu.commit.committed_per_cycle::total 1107587254 # Number of insts commited each cycle
543system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
544system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
545system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
546system.cpu.commit.refs 908382478 # Number of memory references committed
547system.cpu.commit.loads 631387181 # Number of loads committed
548system.cpu.commit.membars 9986 # Number of memory barriers committed
549system.cpu.commit.branches 298259106 # Number of branches committed
550system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
551system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
552system.cpu.commit.function_calls 41577833 # Number of function calls committed.
553system.cpu.commit.bw_lim_events 89265835 # number cycles where commit BW limit reached
554system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
555system.cpu.rob.rob_reads 3844759887 # The number of ROB reads
556system.cpu.rob.rob_writes 5783698867 # The number of ROB writes
557system.cpu.timesIdled 353367 # Number of times that the entire CPU went into an idle state and unscheduled itself
558system.cpu.idleCycles 42935398 # Total number of cycles that the CPU has spent unscheduled due to idling
559system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
560system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
561system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
562system.cpu.cpi 0.925545 # CPI: Cycles Per Instruction
563system.cpu.cpi_total 0.925545 # CPI: Total CPI of All Threads
564system.cpu.ipc 1.080445 # IPC: Instructions Per Cycle
565system.cpu.ipc_total 1.080445 # IPC: Total IPC of All Threads
566system.cpu.int_regfile_reads 11851555490 # number of integer regfile reads
567system.cpu.int_regfile_writes 2239006966 # number of integer regfile writes
568system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads
569system.cpu.fp_regfile_writes 49533000 # number of floating regfile writes
570system.cpu.misc_regfile_reads 1371543913 # number of misc regfile reads
571system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
572system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s)
573system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution
574system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution
575system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution
576system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution
577system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution
578system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution
579system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution
580system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52387 # Packet count per connected master and slave (bytes)
581system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178835 # Packet count per connected master and slave (bytes)
582system.cpu.toL2Bus.pkt_count::total 3231222 # Packet count per connected master and slave (bytes)
583system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1536768 # Cumulative packet size per connected master and slave (bytes)
584system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104525120 # Cumulative packet size per connected master and slave (bytes)
585system.cpu.toL2Bus.tot_pkt_size::total 106061888 # Cumulative packet size per connected master and slave (bytes)
586system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes)
587system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes)
588system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks)
589system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
590system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks)
591system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
592system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks)
593system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
594system.cpu.icache.tags.replacements 22329 # number of replacements
595system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use
596system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks.
597system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks.
598system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks.
599system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
600system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor
601system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy
602system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy
603system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits
604system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits
605system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits
606system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits
607system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits
608system.cpu.icache.overall_hits::total 345973619 # number of overall hits
609system.cpu.icache.ReadReq_misses::cpu.inst 30537 # number of ReadReq misses
610system.cpu.icache.ReadReq_misses::total 30537 # number of ReadReq misses
611system.cpu.icache.demand_misses::cpu.inst 30537 # number of demand (read+write) misses
612system.cpu.icache.demand_misses::total 30537 # number of demand (read+write) misses
613system.cpu.icache.overall_misses::cpu.inst 30537 # number of overall misses
614system.cpu.icache.overall_misses::total 30537 # number of overall misses
615system.cpu.icache.ReadReq_miss_latency::cpu.inst 527751245 # number of ReadReq miss cycles
616system.cpu.icache.ReadReq_miss_latency::total 527751245 # number of ReadReq miss cycles
617system.cpu.icache.demand_miss_latency::cpu.inst 527751245 # number of demand (read+write) miss cycles
618system.cpu.icache.demand_miss_latency::total 527751245 # number of demand (read+write) miss cycles
619system.cpu.icache.overall_miss_latency::cpu.inst 527751245 # number of overall miss cycles
620system.cpu.icache.overall_miss_latency::total 527751245 # number of overall miss cycles
621system.cpu.icache.ReadReq_accesses::cpu.inst 346004156 # number of ReadReq accesses(hits+misses)
622system.cpu.icache.ReadReq_accesses::total 346004156 # number of ReadReq accesses(hits+misses)
623system.cpu.icache.demand_accesses::cpu.inst 346004156 # number of demand (read+write) accesses
624system.cpu.icache.demand_accesses::total 346004156 # number of demand (read+write) accesses
625system.cpu.icache.overall_accesses::cpu.inst 346004156 # number of overall (read+write) accesses
626system.cpu.icache.overall_accesses::total 346004156 # number of overall (read+write) accesses
627system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses
628system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses
629system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses
630system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses
631system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses
632system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses
633system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17282.354030 # average ReadReq miss latency
634system.cpu.icache.ReadReq_avg_miss_latency::total 17282.354030 # average ReadReq miss latency
635system.cpu.icache.demand_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency
636system.cpu.icache.demand_avg_miss_latency::total 17282.354030 # average overall miss latency
637system.cpu.icache.overall_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency
638system.cpu.icache.overall_avg_miss_latency::total 17282.354030 # average overall miss latency
639system.cpu.icache.blocked_cycles::no_mshrs 1734 # number of cycles access was blocked
640system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
641system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked
642system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
643system.cpu.icache.avg_blocked_cycles::no_mshrs 54.187500 # average number of cycles each access was blocked
644system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
645system.cpu.icache.fast_writes 0 # number of fast writes performed
646system.cpu.icache.cache_copies 0 # number of cache copies performed
647system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2162 # number of ReadReq MSHR hits
648system.cpu.icache.ReadReq_mshr_hits::total 2162 # number of ReadReq MSHR hits
649system.cpu.icache.demand_mshr_hits::cpu.inst 2162 # number of demand (read+write) MSHR hits
650system.cpu.icache.demand_mshr_hits::total 2162 # number of demand (read+write) MSHR hits
651system.cpu.icache.overall_mshr_hits::cpu.inst 2162 # number of overall MSHR hits
652system.cpu.icache.overall_mshr_hits::total 2162 # number of overall MSHR hits
653system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28375 # number of ReadReq MSHR misses
654system.cpu.icache.ReadReq_mshr_misses::total 28375 # number of ReadReq MSHR misses
655system.cpu.icache.demand_mshr_misses::cpu.inst 28375 # number of demand (read+write) MSHR misses
656system.cpu.icache.demand_mshr_misses::total 28375 # number of demand (read+write) MSHR misses
657system.cpu.icache.overall_mshr_misses::cpu.inst 28375 # number of overall MSHR misses
658system.cpu.icache.overall_mshr_misses::total 28375 # number of overall MSHR misses
659system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 422292499 # number of ReadReq MSHR miss cycles
660system.cpu.icache.ReadReq_mshr_miss_latency::total 422292499 # number of ReadReq MSHR miss cycles
661system.cpu.icache.demand_mshr_miss_latency::cpu.inst 422292499 # number of demand (read+write) MSHR miss cycles
662system.cpu.icache.demand_mshr_miss_latency::total 422292499 # number of demand (read+write) MSHR miss cycles
663system.cpu.icache.overall_mshr_miss_latency::cpu.inst 422292499 # number of overall MSHR miss cycles
664system.cpu.icache.overall_mshr_miss_latency::total 422292499 # number of overall MSHR miss cycles
665system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses
666system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses
667system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses
668system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses
669system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses
670system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses
671system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14882.555031 # average ReadReq mshr miss latency
672system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14882.555031 # average ReadReq mshr miss latency
673system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency
674system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency
675system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency
676system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency
677system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
678system.cpu.l2cache.tags.replacements 442208 # number of replacements
679system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use
680system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks.
681system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks.
682system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks.
683system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
684system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor
685system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor
686system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor
687system.cpu.l2cache.tags.occ_percent::writebacks 0.039423 # Average percentage of cache occupancy
688system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001529 # Average percentage of cache occupancy
689system.cpu.l2cache.tags.occ_percent::cpu.data 0.956378 # Average percentage of cache occupancy
690system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy
691system.cpu.l2cache.ReadReq_hits::cpu.inst 21578 # number of ReadReq hits
692system.cpu.l2cache.ReadReq_hits::cpu.data 1057872 # number of ReadReq hits
693system.cpu.l2cache.ReadReq_hits::total 1079450 # number of ReadReq hits
694system.cpu.l2cache.Writeback_hits::writebacks 96304 # number of Writeback hits
695system.cpu.l2cache.Writeback_hits::total 96304 # number of Writeback hits
696system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
697system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
698system.cpu.l2cache.ReadExReq_hits::cpu.data 6444 # number of ReadExReq hits
699system.cpu.l2cache.ReadExReq_hits::total 6444 # number of ReadExReq hits
700system.cpu.l2cache.demand_hits::cpu.inst 21578 # number of demand (read+write) hits
701system.cpu.l2cache.demand_hits::cpu.data 1064316 # number of demand (read+write) hits
702system.cpu.l2cache.demand_hits::total 1085894 # number of demand (read+write) hits
703system.cpu.l2cache.overall_hits::cpu.inst 21578 # number of overall hits
704system.cpu.l2cache.overall_hits::cpu.data 1064316 # number of overall hits
705system.cpu.l2cache.overall_hits::total 1085894 # number of overall hits
706system.cpu.l2cache.ReadReq_misses::cpu.inst 2434 # number of ReadReq misses
707system.cpu.l2cache.ReadReq_misses::cpu.data 406511 # number of ReadReq misses
708system.cpu.l2cache.ReadReq_misses::total 408945 # number of ReadReq misses
709system.cpu.l2cache.UpgradeReq_misses::cpu.data 4361 # number of UpgradeReq misses
710system.cpu.l2cache.UpgradeReq_misses::total 4361 # number of UpgradeReq misses
711system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
712system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
713system.cpu.l2cache.demand_misses::cpu.inst 2434 # number of demand (read+write) misses
714system.cpu.l2cache.demand_misses::cpu.data 472586 # number of demand (read+write) misses
715system.cpu.l2cache.demand_misses::total 475020 # number of demand (read+write) misses
716system.cpu.l2cache.overall_misses::cpu.inst 2434 # number of overall misses
717system.cpu.l2cache.overall_misses::cpu.data 472586 # number of overall misses
718system.cpu.l2cache.overall_misses::total 475020 # number of overall misses
719system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 173732500 # number of ReadReq miss cycles
720system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30711118250 # number of ReadReq miss cycles
721system.cpu.l2cache.ReadReq_miss_latency::total 30884850750 # number of ReadReq miss cycles
722system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4593677250 # number of ReadExReq miss cycles
723system.cpu.l2cache.ReadExReq_miss_latency::total 4593677250 # number of ReadExReq miss cycles
724system.cpu.l2cache.demand_miss_latency::cpu.inst 173732500 # number of demand (read+write) miss cycles
725system.cpu.l2cache.demand_miss_latency::cpu.data 35304795500 # number of demand (read+write) miss cycles
726system.cpu.l2cache.demand_miss_latency::total 35478528000 # number of demand (read+write) miss cycles
727system.cpu.l2cache.overall_miss_latency::cpu.inst 173732500 # number of overall miss cycles
728system.cpu.l2cache.overall_miss_latency::cpu.data 35304795500 # number of overall miss cycles
729system.cpu.l2cache.overall_miss_latency::total 35478528000 # number of overall miss cycles
730system.cpu.l2cache.ReadReq_accesses::cpu.inst 24012 # number of ReadReq accesses(hits+misses)
731system.cpu.l2cache.ReadReq_accesses::cpu.data 1464383 # number of ReadReq accesses(hits+misses)
732system.cpu.l2cache.ReadReq_accesses::total 1488395 # number of ReadReq accesses(hits+misses)
733system.cpu.l2cache.Writeback_accesses::writebacks 96304 # number of Writeback accesses(hits+misses)
734system.cpu.l2cache.Writeback_accesses::total 96304 # number of Writeback accesses(hits+misses)
735system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4364 # number of UpgradeReq accesses(hits+misses)
736system.cpu.l2cache.UpgradeReq_accesses::total 4364 # number of UpgradeReq accesses(hits+misses)
737system.cpu.l2cache.ReadExReq_accesses::cpu.data 72519 # number of ReadExReq accesses(hits+misses)
738system.cpu.l2cache.ReadExReq_accesses::total 72519 # number of ReadExReq accesses(hits+misses)
739system.cpu.l2cache.demand_accesses::cpu.inst 24012 # number of demand (read+write) accesses
740system.cpu.l2cache.demand_accesses::cpu.data 1536902 # number of demand (read+write) accesses
741system.cpu.l2cache.demand_accesses::total 1560914 # number of demand (read+write) accesses
742system.cpu.l2cache.overall_accesses::cpu.inst 24012 # number of overall (read+write) accesses
743system.cpu.l2cache.overall_accesses::cpu.data 1536902 # number of overall (read+write) accesses
744system.cpu.l2cache.overall_accesses::total 1560914 # number of overall (read+write) accesses
745system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101366 # miss rate for ReadReq accesses
746system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277599 # miss rate for ReadReq accesses
747system.cpu.l2cache.ReadReq_miss_rate::total 0.274756 # miss rate for ReadReq accesses
748system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999313 # miss rate for UpgradeReq accesses
749system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999313 # miss rate for UpgradeReq accesses
750system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911141 # miss rate for ReadExReq accesses
751system.cpu.l2cache.ReadExReq_miss_rate::total 0.911141 # miss rate for ReadExReq accesses
752system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101366 # miss rate for demand accesses
753system.cpu.l2cache.demand_miss_rate::cpu.data 0.307493 # miss rate for demand accesses
754system.cpu.l2cache.demand_miss_rate::total 0.304322 # miss rate for demand accesses
755system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101366 # miss rate for overall accesses
756system.cpu.l2cache.overall_miss_rate::cpu.data 0.307493 # miss rate for overall accesses
757system.cpu.l2cache.overall_miss_rate::total 0.304322 # miss rate for overall accesses
758system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71377.362366 # average ReadReq miss latency
759system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75548.062045 # average ReadReq miss latency
760system.cpu.l2cache.ReadReq_avg_miss_latency::total 75523.238455 # average ReadReq miss latency
761system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69522.167991 # average ReadExReq miss latency
762system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69522.167991 # average ReadExReq miss latency
763system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency
764system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency
765system.cpu.l2cache.demand_avg_miss_latency::total 74688.493116 # average overall miss latency
766system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency
767system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency
768system.cpu.l2cache.overall_avg_miss_latency::total 74688.493116 # average overall miss latency
769system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
770system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
771system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
772system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
773system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
774system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
775system.cpu.l2cache.fast_writes 0 # number of fast writes performed
776system.cpu.l2cache.cache_copies 0 # number of cache copies performed
777system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
778system.cpu.l2cache.writebacks::total 66098 # number of writebacks
779system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
780system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits
781system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
782system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
783system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits
784system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
785system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
786system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits
787system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
788system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2432 # number of ReadReq MSHR misses
789system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406485 # number of ReadReq MSHR misses
790system.cpu.l2cache.ReadReq_mshr_misses::total 408917 # number of ReadReq MSHR misses
791system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4361 # number of UpgradeReq MSHR misses
792system.cpu.l2cache.UpgradeReq_mshr_misses::total 4361 # number of UpgradeReq MSHR misses
793system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
794system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses
795system.cpu.l2cache.demand_mshr_misses::cpu.inst 2432 # number of demand (read+write) MSHR misses
796system.cpu.l2cache.demand_mshr_misses::cpu.data 472560 # number of demand (read+write) MSHR misses
797system.cpu.l2cache.demand_mshr_misses::total 474992 # number of demand (read+write) MSHR misses
798system.cpu.l2cache.overall_mshr_misses::cpu.inst 2432 # number of overall MSHR misses
799system.cpu.l2cache.overall_mshr_misses::cpu.data 472560 # number of overall MSHR misses
800system.cpu.l2cache.overall_mshr_misses::total 474992 # number of overall MSHR misses
801system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 142964000 # number of ReadReq MSHR miss cycles
802system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25574268250 # number of ReadReq MSHR miss cycles
803system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25717232250 # number of ReadReq MSHR miss cycles
804system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43614361 # number of UpgradeReq MSHR miss cycles
805system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43614361 # number of UpgradeReq MSHR miss cycles
806system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3760538250 # number of ReadExReq MSHR miss cycles
807system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3760538250 # number of ReadExReq MSHR miss cycles
808system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 142964000 # number of demand (read+write) MSHR miss cycles
809system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29334806500 # number of demand (read+write) MSHR miss cycles
810system.cpu.l2cache.demand_mshr_miss_latency::total 29477770500 # number of demand (read+write) MSHR miss cycles
811system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 142964000 # number of overall MSHR miss cycles
812system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29334806500 # number of overall MSHR miss cycles
813system.cpu.l2cache.overall_mshr_miss_latency::total 29477770500 # number of overall MSHR miss cycles
814system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for ReadReq accesses
815system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277581 # mshr miss rate for ReadReq accesses
816system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274737 # mshr miss rate for ReadReq accesses
817system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999313 # mshr miss rate for UpgradeReq accesses
818system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999313 # mshr miss rate for UpgradeReq accesses
819system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911141 # mshr miss rate for ReadExReq accesses
820system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911141 # mshr miss rate for ReadExReq accesses
821system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for demand accesses
822system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307476 # mshr miss rate for demand accesses
823system.cpu.l2cache.demand_mshr_miss_rate::total 0.304304 # mshr miss rate for demand accesses
824system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for overall accesses
825system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307476 # mshr miss rate for overall accesses
826system.cpu.l2cache.overall_mshr_miss_rate::total 0.304304 # mshr miss rate for overall accesses
827system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58784.539474 # average ReadReq mshr miss latency
828system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62915.650639 # average ReadReq mshr miss latency
829system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62891.081197 # average ReadReq mshr miss latency
830system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
831system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
832system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56913.178207 # average ReadExReq mshr miss latency
833system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56913.178207 # average ReadExReq mshr miss latency
834system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency
835system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency
836system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency
837system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency
838system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency
839system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency
840system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
841system.cpu.dcache.tags.replacements 1532805 # number of replacements
842system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use
843system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks.
844system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks.
845system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks.
846system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit.
847system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor
848system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy
849system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy
850system.cpu.dcache.ReadReq_hits::cpu.data 696790485 # number of ReadReq hits
851system.cpu.dcache.ReadReq_hits::total 696790485 # number of ReadReq hits
852system.cpu.dcache.WriteReq_hits::cpu.data 276093216 # number of WriteReq hits
853system.cpu.dcache.WriteReq_hits::total 276093216 # number of WriteReq hits
854system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits
855system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits
856system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
857system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
858system.cpu.dcache.demand_hits::cpu.data 972883701 # number of demand (read+write) hits
859system.cpu.dcache.demand_hits::total 972883701 # number of demand (read+write) hits
860system.cpu.dcache.overall_hits::cpu.data 972883701 # number of overall hits
861system.cpu.dcache.overall_hits::total 972883701 # number of overall hits
862system.cpu.dcache.ReadReq_misses::cpu.data 1953888 # number of ReadReq misses
863system.cpu.dcache.ReadReq_misses::total 1953888 # number of ReadReq misses
864system.cpu.dcache.WriteReq_misses::cpu.data 842462 # number of WriteReq misses
865system.cpu.dcache.WriteReq_misses::total 842462 # number of WriteReq misses
866system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
867system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
868system.cpu.dcache.demand_misses::cpu.data 2796350 # number of demand (read+write) misses
869system.cpu.dcache.demand_misses::total 2796350 # number of demand (read+write) misses
870system.cpu.dcache.overall_misses::cpu.data 2796350 # number of overall misses
871system.cpu.dcache.overall_misses::total 2796350 # number of overall misses
872system.cpu.dcache.ReadReq_miss_latency::cpu.data 79173694807 # number of ReadReq miss cycles
873system.cpu.dcache.ReadReq_miss_latency::total 79173694807 # number of ReadReq miss cycles
874system.cpu.dcache.WriteReq_miss_latency::cpu.data 56852278531 # number of WriteReq miss cycles
875system.cpu.dcache.WriteReq_miss_latency::total 56852278531 # number of WriteReq miss cycles
876system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204750 # number of LoadLockedReq miss cycles
877system.cpu.dcache.LoadLockedReq_miss_latency::total 204750 # number of LoadLockedReq miss cycles
878system.cpu.dcache.demand_miss_latency::cpu.data 136025973338 # number of demand (read+write) miss cycles
879system.cpu.dcache.demand_miss_latency::total 136025973338 # number of demand (read+write) miss cycles
880system.cpu.dcache.overall_miss_latency::cpu.data 136025973338 # number of overall miss cycles
881system.cpu.dcache.overall_miss_latency::total 136025973338 # number of overall miss cycles
882system.cpu.dcache.ReadReq_accesses::cpu.data 698744373 # number of ReadReq accesses(hits+misses)
883system.cpu.dcache.ReadReq_accesses::total 698744373 # number of ReadReq accesses(hits+misses)
884system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
885system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
886system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses)
887system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses)
888system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
889system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
890system.cpu.dcache.demand_accesses::cpu.data 975680051 # number of demand (read+write) accesses
891system.cpu.dcache.demand_accesses::total 975680051 # number of demand (read+write) accesses
892system.cpu.dcache.overall_accesses::cpu.data 975680051 # number of overall (read+write) accesses
893system.cpu.dcache.overall_accesses::total 975680051 # number of overall (read+write) accesses
894system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002796 # miss rate for ReadReq accesses
895system.cpu.dcache.ReadReq_miss_rate::total 0.002796 # miss rate for ReadReq accesses
896system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses
897system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses
898system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
899system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
900system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
901system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
902system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
903system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
904system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40521.101930 # average ReadReq miss latency
905system.cpu.dcache.ReadReq_avg_miss_latency::total 40521.101930 # average ReadReq miss latency
906system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67483.493061 # average WriteReq miss latency
907system.cpu.dcache.WriteReq_avg_miss_latency::total 67483.493061 # average WriteReq miss latency
908system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 68250 # average LoadLockedReq miss latency
909system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 68250 # average LoadLockedReq miss latency
910system.cpu.dcache.demand_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency
911system.cpu.dcache.demand_avg_miss_latency::total 48644.115843 # average overall miss latency
912system.cpu.dcache.overall_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency
913system.cpu.dcache.overall_avg_miss_latency::total 48644.115843 # average overall miss latency
914system.cpu.dcache.blocked_cycles::no_mshrs 2745 # number of cycles access was blocked
915system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked
916system.cpu.dcache.blocked::no_mshrs 62 # number of cycles access was blocked
917system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
918system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.274194 # average number of cycles each access was blocked
919system.cpu.dcache.avg_blocked_cycles::no_targets 9.584270 # average number of cycles each access was blocked
920system.cpu.dcache.fast_writes 0 # number of fast writes performed
921system.cpu.dcache.cache_copies 0 # number of cache copies performed
922system.cpu.dcache.writebacks::writebacks 96304 # number of writebacks
923system.cpu.dcache.writebacks::total 96304 # number of writebacks
924system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489504 # number of ReadReq MSHR hits
925system.cpu.dcache.ReadReq_mshr_hits::total 489504 # number of ReadReq MSHR hits
926system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765580 # number of WriteReq MSHR hits
927system.cpu.dcache.WriteReq_mshr_hits::total 765580 # number of WriteReq MSHR hits
928system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
929system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
930system.cpu.dcache.demand_mshr_hits::cpu.data 1255084 # number of demand (read+write) MSHR hits
931system.cpu.dcache.demand_mshr_hits::total 1255084 # number of demand (read+write) MSHR hits
932system.cpu.dcache.overall_mshr_hits::cpu.data 1255084 # number of overall MSHR hits
933system.cpu.dcache.overall_mshr_hits::total 1255084 # number of overall MSHR hits
934system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464384 # number of ReadReq MSHR misses
935system.cpu.dcache.ReadReq_mshr_misses::total 1464384 # number of ReadReq MSHR misses
936system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76882 # number of WriteReq MSHR misses
937system.cpu.dcache.WriteReq_mshr_misses::total 76882 # number of WriteReq MSHR misses
938system.cpu.dcache.demand_mshr_misses::cpu.data 1541266 # number of demand (read+write) MSHR misses
939system.cpu.dcache.demand_mshr_misses::total 1541266 # number of demand (read+write) MSHR misses
940system.cpu.dcache.overall_mshr_misses::cpu.data 1541266 # number of overall MSHR misses
941system.cpu.dcache.overall_mshr_misses::total 1541266 # number of overall MSHR misses
942system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42754567776 # number of ReadReq MSHR miss cycles
943system.cpu.dcache.ReadReq_mshr_miss_latency::total 42754567776 # number of ReadReq MSHR miss cycles
944system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4832230139 # number of WriteReq MSHR miss cycles
945system.cpu.dcache.WriteReq_mshr_miss_latency::total 4832230139 # number of WriteReq MSHR miss cycles
946system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47586797915 # number of demand (read+write) MSHR miss cycles
947system.cpu.dcache.demand_mshr_miss_latency::total 47586797915 # number of demand (read+write) MSHR miss cycles
948system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47586797915 # number of overall MSHR miss cycles
949system.cpu.dcache.overall_mshr_miss_latency::total 47586797915 # number of overall MSHR miss cycles
950system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002096 # mshr miss rate for ReadReq accesses
951system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002096 # mshr miss rate for ReadReq accesses
952system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
953system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
954system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for demand accesses
955system.cpu.dcache.demand_mshr_miss_rate::total 0.001580 # mshr miss rate for demand accesses
956system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for overall accesses
957system.cpu.dcache.overall_mshr_miss_rate::total 0.001580 # mshr miss rate for overall accesses
958system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29196.281697 # average ReadReq mshr miss latency
959system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29196.281697 # average ReadReq mshr miss latency
960system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62852.555071 # average WriteReq mshr miss latency
961system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62852.555071 # average WriteReq mshr miss latency
962system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency
963system.cpu.dcache.demand_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency
964system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency
965system.cpu.dcache.overall_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency
966system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
967
968---------- End Simulation Statistics ----------
| 368system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
369system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing
370system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed
371system.cpu.rename.tempSerializingInsts 18729 # count of temporary serializing insts renamed
372system.cpu.rename.skidInsts 172024073 # count of insts added to the skid buffer
373system.cpu.memDep0.insertedLoads 975055963 # Number of loads inserted to the mem dependence unit.
374system.cpu.memDep0.insertedStores 496398991 # Number of stores inserted to the mem dependence unit.
375system.cpu.memDep0.conflictingLoads 36275443 # Number of conflicting loads.
376system.cpu.memDep0.conflictingStores 40590257 # Number of conflicting stores.
377system.cpu.iq.iqInstsAdded 2826416078 # Number of instructions added to the IQ (excludes non-spec)
378system.cpu.iq.iqNonSpecInstsAdded 28152 # Number of non-speculative instructions added to the IQ
379system.cpu.iq.iqInstsIssued 2457324643 # Number of instructions issued
380system.cpu.iq.iqSquashedInstsIssued 15915709 # Number of squashed instructions issued
381system.cpu.iq.iqSquashedInstsExamined 928556403 # Number of squashed instructions iterated over during squash; mainly for profiling
382system.cpu.iq.iqSquashedOperandsExamined 2380098621 # Number of squashed operands that are examined and possibly removed from graph
383system.cpu.iq.iqSquashedNonSpecRemoved 6768 # Number of squashed non-spec instructions that were removed
384system.cpu.iq.issued_per_cycle::samples 1238361342 # Number of insts issued each cycle
385system.cpu.iq.issued_per_cycle::mean 1.984336 # Number of insts issued each cycle
386system.cpu.iq.issued_per_cycle::stdev 1.868331 # Number of insts issued each cycle
387system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
388system.cpu.iq.issued_per_cycle::0 394006079 31.82% 31.82% # Number of insts issued each cycle
389system.cpu.iq.issued_per_cycle::1 183256590 14.80% 46.62% # Number of insts issued each cycle
390system.cpu.iq.issued_per_cycle::2 205523874 16.60% 63.21% # Number of insts issued each cycle
391system.cpu.iq.issued_per_cycle::3 174394872 14.08% 77.29% # Number of insts issued each cycle
392system.cpu.iq.issued_per_cycle::4 137878376 11.13% 88.43% # Number of insts issued each cycle
393system.cpu.iq.issued_per_cycle::5 90899666 7.34% 95.77% # Number of insts issued each cycle
394system.cpu.iq.issued_per_cycle::6 36275985 2.93% 98.70% # Number of insts issued each cycle
395system.cpu.iq.issued_per_cycle::7 12839255 1.04% 99.73% # Number of insts issued each cycle
396system.cpu.iq.issued_per_cycle::8 3286645 0.27% 100.00% # Number of insts issued each cycle
397system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
398system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
399system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
400system.cpu.iq.issued_per_cycle::total 1238361342 # Number of insts issued each cycle
401system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
402system.cpu.iq.fu_full::IntAlu 691696 0.78% 0.78% # attempts to use FU when none available
403system.cpu.iq.fu_full::IntMult 24382 0.03% 0.81% # attempts to use FU when none available
404system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available
405system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available
406system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available
407system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available
408system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available
409system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available
410system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
411system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available
412system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available
413system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available
414system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available
415system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available
416system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available
417system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available
418system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available
419system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available
420system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available
421system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available
422system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available
423system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available
424system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available
425system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available
426system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available
427system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
431system.cpu.iq.fu_full::MemRead 55024342 62.24% 63.05% # attempts to use FU when none available
432system.cpu.iq.fu_full::MemWrite 32666949 36.95% 100.00% # attempts to use FU when none available
433system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
434system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
435system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
436system.cpu.iq.FU_type_0::IntAlu 1118619814 45.52% 45.52% # Type of FU issued
437system.cpu.iq.FU_type_0::IntMult 11223087 0.46% 45.98% # Type of FU issued
438system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued
439system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued
440system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued
441system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued
442system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued
443system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued
444system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued
445system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued
446system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued
447system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued
448system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued
449system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued
450system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued
451system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued
452system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued
453system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued
454system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued
455system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued
456system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.03% # Type of FU issued
457system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.03% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 46.31% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdFloatCvt 5501669 0.22% 46.54% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.54% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdFloatMisc 23389012 0.95% 47.49% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.49% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.49% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.49% # Type of FU issued
465system.cpu.iq.FU_type_0::MemRead 843037947 34.31% 81.80% # Type of FU issued
466system.cpu.iq.FU_type_0::MemWrite 447301347 18.20% 100.00% # Type of FU issued
467system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
468system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
469system.cpu.iq.FU_type_0::total 2457324643 # Type of FU issued
470system.cpu.iq.rate 1.917842 # Inst issue rate
471system.cpu.iq.fu_busy_cnt 88407369 # FU busy when requested
472system.cpu.iq.fu_busy_rate 0.035977 # FU busy rate (busy events/executed inst)
473system.cpu.iq.int_inst_queue_reads 6133604202 # Number of integer instruction queue reads
474system.cpu.iq.int_inst_queue_writes 3666175191 # Number of integer instruction queue writes
475system.cpu.iq.int_inst_queue_wakeup_accesses 2269813505 # Number of integer instruction queue wakeup accesses
476system.cpu.iq.fp_inst_queue_reads 123729504 # Number of floating instruction queue reads
477system.cpu.iq.fp_inst_queue_writes 88892403 # Number of floating instruction queue writes
478system.cpu.iq.fp_inst_queue_wakeup_accesses 56421926 # Number of floating instruction queue wakeup accesses
479system.cpu.iq.int_alu_accesses 2481804628 # Number of integer alu accesses
480system.cpu.iq.fp_alu_accesses 63927384 # Number of floating point alu accesses
481system.cpu.iew.lsq.thread0.forwLoads 85672552 # Number of loads that had data forwarded from stores
482system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
483system.cpu.iew.lsq.thread0.squashedLoads 343668782 # Number of loads squashed
484system.cpu.iew.lsq.thread0.ignoredResponses 27729 # Number of memory responses ignored because the instruction is squashed
485system.cpu.iew.lsq.thread0.memOrderViolation 1429255 # Number of memory ordering violations
486system.cpu.iew.lsq.thread0.squashedStores 219403694 # Number of stores squashed
487system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
488system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
489system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
490system.cpu.iew.lsq.thread0.cacheBlocked 304 # Number of times an access to memory failed due to the cache being blocked
491system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
492system.cpu.iew.iewSquashCycles 130774088 # Number of cycles IEW is squashing
493system.cpu.iew.iewBlockCycles 15649984 # Number of cycles IEW is blocking
494system.cpu.iew.iewUnblockCycles 1558990 # Number of cycles IEW is unblocking
495system.cpu.iew.iewDispatchedInsts 2826456693 # Number of instructions dispatched to IQ
496system.cpu.iew.iewDispSquashedInsts 641968 # Number of squashed instructions skipped by dispatch
497system.cpu.iew.iewDispLoadInsts 975055963 # Number of dispatched load instructions
498system.cpu.iew.iewDispStoreInsts 496398991 # Number of dispatched store instructions
499system.cpu.iew.iewDispNonSpecInsts 18166 # Number of dispatched non-speculative instructions
500system.cpu.iew.iewIQFullEvents 1553675 # Number of times the IQ has become full, causing a stall
501system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall
502system.cpu.iew.memOrderViolationEvents 1429255 # Number of memory order violations
503system.cpu.iew.predictedTakenIncorrect 33789507 # Number of branches that were predicted taken incorrectly
504system.cpu.iew.predictedNotTakenIncorrect 2118647 # Number of branches that were predicted not taken incorrectly
505system.cpu.iew.branchMispredicts 35908154 # Number of branch mispredicts detected at execute
506system.cpu.iew.iewExecutedInsts 2378923796 # Number of executed instructions
507system.cpu.iew.iewExecLoadInsts 796860173 # Number of load instructions executed
508system.cpu.iew.iewExecSquashedInsts 78400847 # Number of squashed instructions skipped in execute
509system.cpu.iew.exec_swp 0 # number of swp insts executed
510system.cpu.iew.exec_nop 12463 # number of nop insts executed
511system.cpu.iew.exec_refs 1223764024 # number of memory reference insts executed
512system.cpu.iew.exec_branches 324680497 # Number of branches executed
513system.cpu.iew.exec_stores 426903851 # Number of stores executed
514system.cpu.iew.exec_rate 1.856653 # Inst execution rate
515system.cpu.iew.wb_sent 2351973532 # cumulative count of insts sent to commit
516system.cpu.iew.wb_count 2326235431 # cumulative count of insts written-back
517system.cpu.iew.wb_producers 1354756756 # num instructions producing a value
518system.cpu.iew.wb_consumers 2530303455 # num instructions consuming a value
519system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
520system.cpu.iew.wb_rate 1.815532 # insts written-back per cycle
521system.cpu.iew.wb_fanout 0.535413 # average fanout of values written-back
522system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
523system.cpu.commit.commitSquashedInsts 941120455 # The number of squashed insts skipped by commit
524system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
525system.cpu.commit.branchMispredicts 31562826 # The number of times a branch was mispredicted
526system.cpu.commit.committed_per_cycle::samples 1107587254 # Number of insts commited each cycle
527system.cpu.commit.committed_per_cycle::mean 1.702201 # Number of insts commited each cycle
528system.cpu.commit.committed_per_cycle::stdev 2.378361 # Number of insts commited each cycle
529system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
530system.cpu.commit.committed_per_cycle::0 463154673 41.82% 41.82% # Number of insts commited each cycle
531system.cpu.commit.committed_per_cycle::1 291887882 26.35% 68.17% # Number of insts commited each cycle
532system.cpu.commit.committed_per_cycle::2 96478924 8.71% 76.88% # Number of insts commited each cycle
533system.cpu.commit.committed_per_cycle::3 70059146 6.33% 83.21% # Number of insts commited each cycle
534system.cpu.commit.committed_per_cycle::4 46846853 4.23% 87.44% # Number of insts commited each cycle
535system.cpu.commit.committed_per_cycle::5 22330225 2.02% 89.45% # Number of insts commited each cycle
536system.cpu.commit.committed_per_cycle::6 15798039 1.43% 90.88% # Number of insts commited each cycle
537system.cpu.commit.committed_per_cycle::7 11765677 1.06% 91.94% # Number of insts commited each cycle
538system.cpu.commit.committed_per_cycle::8 89265835 8.06% 100.00% # Number of insts commited each cycle
539system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
540system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
541system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
542system.cpu.commit.committed_per_cycle::total 1107587254 # Number of insts commited each cycle
543system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
544system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
545system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
546system.cpu.commit.refs 908382478 # Number of memory references committed
547system.cpu.commit.loads 631387181 # Number of loads committed
548system.cpu.commit.membars 9986 # Number of memory barriers committed
549system.cpu.commit.branches 298259106 # Number of branches committed
550system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
551system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
552system.cpu.commit.function_calls 41577833 # Number of function calls committed.
553system.cpu.commit.bw_lim_events 89265835 # number cycles where commit BW limit reached
554system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
555system.cpu.rob.rob_reads 3844759887 # The number of ROB reads
556system.cpu.rob.rob_writes 5783698867 # The number of ROB writes
557system.cpu.timesIdled 353367 # Number of times that the entire CPU went into an idle state and unscheduled itself
558system.cpu.idleCycles 42935398 # Total number of cycles that the CPU has spent unscheduled due to idling
559system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
560system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
561system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
562system.cpu.cpi 0.925545 # CPI: Cycles Per Instruction
563system.cpu.cpi_total 0.925545 # CPI: Total CPI of All Threads
564system.cpu.ipc 1.080445 # IPC: Instructions Per Cycle
565system.cpu.ipc_total 1.080445 # IPC: Total IPC of All Threads
566system.cpu.int_regfile_reads 11851555490 # number of integer regfile reads
567system.cpu.int_regfile_writes 2239006966 # number of integer regfile writes
568system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads
569system.cpu.fp_regfile_writes 49533000 # number of floating regfile writes
570system.cpu.misc_regfile_reads 1371543913 # number of misc regfile reads
571system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
572system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s)
573system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution
574system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution
575system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution
576system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution
577system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution
578system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution
579system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution
580system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52387 # Packet count per connected master and slave (bytes)
581system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178835 # Packet count per connected master and slave (bytes)
582system.cpu.toL2Bus.pkt_count::total 3231222 # Packet count per connected master and slave (bytes)
583system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1536768 # Cumulative packet size per connected master and slave (bytes)
584system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104525120 # Cumulative packet size per connected master and slave (bytes)
585system.cpu.toL2Bus.tot_pkt_size::total 106061888 # Cumulative packet size per connected master and slave (bytes)
586system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes)
587system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes)
588system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks)
589system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
590system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks)
591system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
592system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks)
593system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
594system.cpu.icache.tags.replacements 22329 # number of replacements
595system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use
596system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks.
597system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks.
598system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks.
599system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
600system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor
601system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy
602system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy
603system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits
604system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits
605system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits
606system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits
607system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits
608system.cpu.icache.overall_hits::total 345973619 # number of overall hits
609system.cpu.icache.ReadReq_misses::cpu.inst 30537 # number of ReadReq misses
610system.cpu.icache.ReadReq_misses::total 30537 # number of ReadReq misses
611system.cpu.icache.demand_misses::cpu.inst 30537 # number of demand (read+write) misses
612system.cpu.icache.demand_misses::total 30537 # number of demand (read+write) misses
613system.cpu.icache.overall_misses::cpu.inst 30537 # number of overall misses
614system.cpu.icache.overall_misses::total 30537 # number of overall misses
615system.cpu.icache.ReadReq_miss_latency::cpu.inst 527751245 # number of ReadReq miss cycles
616system.cpu.icache.ReadReq_miss_latency::total 527751245 # number of ReadReq miss cycles
617system.cpu.icache.demand_miss_latency::cpu.inst 527751245 # number of demand (read+write) miss cycles
618system.cpu.icache.demand_miss_latency::total 527751245 # number of demand (read+write) miss cycles
619system.cpu.icache.overall_miss_latency::cpu.inst 527751245 # number of overall miss cycles
620system.cpu.icache.overall_miss_latency::total 527751245 # number of overall miss cycles
621system.cpu.icache.ReadReq_accesses::cpu.inst 346004156 # number of ReadReq accesses(hits+misses)
622system.cpu.icache.ReadReq_accesses::total 346004156 # number of ReadReq accesses(hits+misses)
623system.cpu.icache.demand_accesses::cpu.inst 346004156 # number of demand (read+write) accesses
624system.cpu.icache.demand_accesses::total 346004156 # number of demand (read+write) accesses
625system.cpu.icache.overall_accesses::cpu.inst 346004156 # number of overall (read+write) accesses
626system.cpu.icache.overall_accesses::total 346004156 # number of overall (read+write) accesses
627system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses
628system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses
629system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses
630system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses
631system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses
632system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses
633system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17282.354030 # average ReadReq miss latency
634system.cpu.icache.ReadReq_avg_miss_latency::total 17282.354030 # average ReadReq miss latency
635system.cpu.icache.demand_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency
636system.cpu.icache.demand_avg_miss_latency::total 17282.354030 # average overall miss latency
637system.cpu.icache.overall_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency
638system.cpu.icache.overall_avg_miss_latency::total 17282.354030 # average overall miss latency
639system.cpu.icache.blocked_cycles::no_mshrs 1734 # number of cycles access was blocked
640system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
641system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked
642system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
643system.cpu.icache.avg_blocked_cycles::no_mshrs 54.187500 # average number of cycles each access was blocked
644system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
645system.cpu.icache.fast_writes 0 # number of fast writes performed
646system.cpu.icache.cache_copies 0 # number of cache copies performed
647system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2162 # number of ReadReq MSHR hits
648system.cpu.icache.ReadReq_mshr_hits::total 2162 # number of ReadReq MSHR hits
649system.cpu.icache.demand_mshr_hits::cpu.inst 2162 # number of demand (read+write) MSHR hits
650system.cpu.icache.demand_mshr_hits::total 2162 # number of demand (read+write) MSHR hits
651system.cpu.icache.overall_mshr_hits::cpu.inst 2162 # number of overall MSHR hits
652system.cpu.icache.overall_mshr_hits::total 2162 # number of overall MSHR hits
653system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28375 # number of ReadReq MSHR misses
654system.cpu.icache.ReadReq_mshr_misses::total 28375 # number of ReadReq MSHR misses
655system.cpu.icache.demand_mshr_misses::cpu.inst 28375 # number of demand (read+write) MSHR misses
656system.cpu.icache.demand_mshr_misses::total 28375 # number of demand (read+write) MSHR misses
657system.cpu.icache.overall_mshr_misses::cpu.inst 28375 # number of overall MSHR misses
658system.cpu.icache.overall_mshr_misses::total 28375 # number of overall MSHR misses
659system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 422292499 # number of ReadReq MSHR miss cycles
660system.cpu.icache.ReadReq_mshr_miss_latency::total 422292499 # number of ReadReq MSHR miss cycles
661system.cpu.icache.demand_mshr_miss_latency::cpu.inst 422292499 # number of demand (read+write) MSHR miss cycles
662system.cpu.icache.demand_mshr_miss_latency::total 422292499 # number of demand (read+write) MSHR miss cycles
663system.cpu.icache.overall_mshr_miss_latency::cpu.inst 422292499 # number of overall MSHR miss cycles
664system.cpu.icache.overall_mshr_miss_latency::total 422292499 # number of overall MSHR miss cycles
665system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses
666system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses
667system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses
668system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses
669system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses
670system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses
671system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14882.555031 # average ReadReq mshr miss latency
672system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14882.555031 # average ReadReq mshr miss latency
673system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency
674system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency
675system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency
676system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency
677system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
678system.cpu.l2cache.tags.replacements 442208 # number of replacements
679system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use
680system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks.
681system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks.
682system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks.
683system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
684system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor
685system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor
686system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor
687system.cpu.l2cache.tags.occ_percent::writebacks 0.039423 # Average percentage of cache occupancy
688system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001529 # Average percentage of cache occupancy
689system.cpu.l2cache.tags.occ_percent::cpu.data 0.956378 # Average percentage of cache occupancy
690system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy
691system.cpu.l2cache.ReadReq_hits::cpu.inst 21578 # number of ReadReq hits
692system.cpu.l2cache.ReadReq_hits::cpu.data 1057872 # number of ReadReq hits
693system.cpu.l2cache.ReadReq_hits::total 1079450 # number of ReadReq hits
694system.cpu.l2cache.Writeback_hits::writebacks 96304 # number of Writeback hits
695system.cpu.l2cache.Writeback_hits::total 96304 # number of Writeback hits
696system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
697system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
698system.cpu.l2cache.ReadExReq_hits::cpu.data 6444 # number of ReadExReq hits
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704system.cpu.l2cache.overall_hits::cpu.data 1064316 # number of overall hits
705system.cpu.l2cache.overall_hits::total 1085894 # number of overall hits
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710system.cpu.l2cache.UpgradeReq_misses::total 4361 # number of UpgradeReq misses
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712system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
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717system.cpu.l2cache.overall_misses::cpu.data 472586 # number of overall misses
718system.cpu.l2cache.overall_misses::total 475020 # number of overall misses
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720system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30711118250 # number of ReadReq miss cycles
721system.cpu.l2cache.ReadReq_miss_latency::total 30884850750 # number of ReadReq miss cycles
722system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4593677250 # number of ReadExReq miss cycles
723system.cpu.l2cache.ReadExReq_miss_latency::total 4593677250 # number of ReadExReq miss cycles
724system.cpu.l2cache.demand_miss_latency::cpu.inst 173732500 # number of demand (read+write) miss cycles
725system.cpu.l2cache.demand_miss_latency::cpu.data 35304795500 # number of demand (read+write) miss cycles
726system.cpu.l2cache.demand_miss_latency::total 35478528000 # number of demand (read+write) miss cycles
727system.cpu.l2cache.overall_miss_latency::cpu.inst 173732500 # number of overall miss cycles
728system.cpu.l2cache.overall_miss_latency::cpu.data 35304795500 # number of overall miss cycles
729system.cpu.l2cache.overall_miss_latency::total 35478528000 # number of overall miss cycles
730system.cpu.l2cache.ReadReq_accesses::cpu.inst 24012 # number of ReadReq accesses(hits+misses)
731system.cpu.l2cache.ReadReq_accesses::cpu.data 1464383 # number of ReadReq accesses(hits+misses)
732system.cpu.l2cache.ReadReq_accesses::total 1488395 # number of ReadReq accesses(hits+misses)
733system.cpu.l2cache.Writeback_accesses::writebacks 96304 # number of Writeback accesses(hits+misses)
734system.cpu.l2cache.Writeback_accesses::total 96304 # number of Writeback accesses(hits+misses)
735system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4364 # number of UpgradeReq accesses(hits+misses)
736system.cpu.l2cache.UpgradeReq_accesses::total 4364 # number of UpgradeReq accesses(hits+misses)
737system.cpu.l2cache.ReadExReq_accesses::cpu.data 72519 # number of ReadExReq accesses(hits+misses)
738system.cpu.l2cache.ReadExReq_accesses::total 72519 # number of ReadExReq accesses(hits+misses)
739system.cpu.l2cache.demand_accesses::cpu.inst 24012 # number of demand (read+write) accesses
740system.cpu.l2cache.demand_accesses::cpu.data 1536902 # number of demand (read+write) accesses
741system.cpu.l2cache.demand_accesses::total 1560914 # number of demand (read+write) accesses
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743system.cpu.l2cache.overall_accesses::cpu.data 1536902 # number of overall (read+write) accesses
744system.cpu.l2cache.overall_accesses::total 1560914 # number of overall (read+write) accesses
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746system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277599 # miss rate for ReadReq accesses
747system.cpu.l2cache.ReadReq_miss_rate::total 0.274756 # miss rate for ReadReq accesses
748system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999313 # miss rate for UpgradeReq accesses
749system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999313 # miss rate for UpgradeReq accesses
750system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911141 # miss rate for ReadExReq accesses
751system.cpu.l2cache.ReadExReq_miss_rate::total 0.911141 # miss rate for ReadExReq accesses
752system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101366 # miss rate for demand accesses
753system.cpu.l2cache.demand_miss_rate::cpu.data 0.307493 # miss rate for demand accesses
754system.cpu.l2cache.demand_miss_rate::total 0.304322 # miss rate for demand accesses
755system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101366 # miss rate for overall accesses
756system.cpu.l2cache.overall_miss_rate::cpu.data 0.307493 # miss rate for overall accesses
757system.cpu.l2cache.overall_miss_rate::total 0.304322 # miss rate for overall accesses
758system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71377.362366 # average ReadReq miss latency
759system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75548.062045 # average ReadReq miss latency
760system.cpu.l2cache.ReadReq_avg_miss_latency::total 75523.238455 # average ReadReq miss latency
761system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69522.167991 # average ReadExReq miss latency
762system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69522.167991 # average ReadExReq miss latency
763system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency
764system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency
765system.cpu.l2cache.demand_avg_miss_latency::total 74688.493116 # average overall miss latency
766system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency
767system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency
768system.cpu.l2cache.overall_avg_miss_latency::total 74688.493116 # average overall miss latency
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770system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
771system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
772system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
773system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
774system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
775system.cpu.l2cache.fast_writes 0 # number of fast writes performed
776system.cpu.l2cache.cache_copies 0 # number of cache copies performed
777system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
778system.cpu.l2cache.writebacks::total 66098 # number of writebacks
779system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
780system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits
781system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
782system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
783system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits
784system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
785system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
786system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits
787system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
788system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2432 # number of ReadReq MSHR misses
789system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406485 # number of ReadReq MSHR misses
790system.cpu.l2cache.ReadReq_mshr_misses::total 408917 # number of ReadReq MSHR misses
791system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4361 # number of UpgradeReq MSHR misses
792system.cpu.l2cache.UpgradeReq_mshr_misses::total 4361 # number of UpgradeReq MSHR misses
793system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
794system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses
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799system.cpu.l2cache.overall_mshr_misses::cpu.data 472560 # number of overall MSHR misses
800system.cpu.l2cache.overall_mshr_misses::total 474992 # number of overall MSHR misses
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802system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25574268250 # number of ReadReq MSHR miss cycles
803system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25717232250 # number of ReadReq MSHR miss cycles
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805system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43614361 # number of UpgradeReq MSHR miss cycles
806system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3760538250 # number of ReadExReq MSHR miss cycles
807system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3760538250 # number of ReadExReq MSHR miss cycles
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809system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29334806500 # number of demand (read+write) MSHR miss cycles
810system.cpu.l2cache.demand_mshr_miss_latency::total 29477770500 # number of demand (read+write) MSHR miss cycles
811system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 142964000 # number of overall MSHR miss cycles
812system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29334806500 # number of overall MSHR miss cycles
813system.cpu.l2cache.overall_mshr_miss_latency::total 29477770500 # number of overall MSHR miss cycles
814system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for ReadReq accesses
815system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277581 # mshr miss rate for ReadReq accesses
816system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274737 # mshr miss rate for ReadReq accesses
817system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999313 # mshr miss rate for UpgradeReq accesses
818system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999313 # mshr miss rate for UpgradeReq accesses
819system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911141 # mshr miss rate for ReadExReq accesses
820system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911141 # mshr miss rate for ReadExReq accesses
821system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for demand accesses
822system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307476 # mshr miss rate for demand accesses
823system.cpu.l2cache.demand_mshr_miss_rate::total 0.304304 # mshr miss rate for demand accesses
824system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for overall accesses
825system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307476 # mshr miss rate for overall accesses
826system.cpu.l2cache.overall_mshr_miss_rate::total 0.304304 # mshr miss rate for overall accesses
827system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58784.539474 # average ReadReq mshr miss latency
828system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62915.650639 # average ReadReq mshr miss latency
829system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62891.081197 # average ReadReq mshr miss latency
830system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
831system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
832system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56913.178207 # average ReadExReq mshr miss latency
833system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56913.178207 # average ReadExReq mshr miss latency
834system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency
835system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency
836system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency
837system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency
838system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency
839system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency
840system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
841system.cpu.dcache.tags.replacements 1532805 # number of replacements
842system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use
843system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks.
844system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks.
845system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks.
846system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit.
847system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor
848system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy
849system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy
850system.cpu.dcache.ReadReq_hits::cpu.data 696790485 # number of ReadReq hits
851system.cpu.dcache.ReadReq_hits::total 696790485 # number of ReadReq hits
852system.cpu.dcache.WriteReq_hits::cpu.data 276093216 # number of WriteReq hits
853system.cpu.dcache.WriteReq_hits::total 276093216 # number of WriteReq hits
854system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits
855system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits
856system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
857system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
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859system.cpu.dcache.demand_hits::total 972883701 # number of demand (read+write) hits
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861system.cpu.dcache.overall_hits::total 972883701 # number of overall hits
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863system.cpu.dcache.ReadReq_misses::total 1953888 # number of ReadReq misses
864system.cpu.dcache.WriteReq_misses::cpu.data 842462 # number of WriteReq misses
865system.cpu.dcache.WriteReq_misses::total 842462 # number of WriteReq misses
866system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
867system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
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869system.cpu.dcache.demand_misses::total 2796350 # number of demand (read+write) misses
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871system.cpu.dcache.overall_misses::total 2796350 # number of overall misses
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873system.cpu.dcache.ReadReq_miss_latency::total 79173694807 # number of ReadReq miss cycles
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875system.cpu.dcache.WriteReq_miss_latency::total 56852278531 # number of WriteReq miss cycles
876system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204750 # number of LoadLockedReq miss cycles
877system.cpu.dcache.LoadLockedReq_miss_latency::total 204750 # number of LoadLockedReq miss cycles
878system.cpu.dcache.demand_miss_latency::cpu.data 136025973338 # number of demand (read+write) miss cycles
879system.cpu.dcache.demand_miss_latency::total 136025973338 # number of demand (read+write) miss cycles
880system.cpu.dcache.overall_miss_latency::cpu.data 136025973338 # number of overall miss cycles
881system.cpu.dcache.overall_miss_latency::total 136025973338 # number of overall miss cycles
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883system.cpu.dcache.ReadReq_accesses::total 698744373 # number of ReadReq accesses(hits+misses)
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885system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
886system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses)
887system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses)
888system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
889system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
890system.cpu.dcache.demand_accesses::cpu.data 975680051 # number of demand (read+write) accesses
891system.cpu.dcache.demand_accesses::total 975680051 # number of demand (read+write) accesses
892system.cpu.dcache.overall_accesses::cpu.data 975680051 # number of overall (read+write) accesses
893system.cpu.dcache.overall_accesses::total 975680051 # number of overall (read+write) accesses
894system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002796 # miss rate for ReadReq accesses
895system.cpu.dcache.ReadReq_miss_rate::total 0.002796 # miss rate for ReadReq accesses
896system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses
897system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses
898system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
899system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
900system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
901system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
902system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
903system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
904system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40521.101930 # average ReadReq miss latency
905system.cpu.dcache.ReadReq_avg_miss_latency::total 40521.101930 # average ReadReq miss latency
906system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67483.493061 # average WriteReq miss latency
907system.cpu.dcache.WriteReq_avg_miss_latency::total 67483.493061 # average WriteReq miss latency
908system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 68250 # average LoadLockedReq miss latency
909system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 68250 # average LoadLockedReq miss latency
910system.cpu.dcache.demand_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency
911system.cpu.dcache.demand_avg_miss_latency::total 48644.115843 # average overall miss latency
912system.cpu.dcache.overall_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency
913system.cpu.dcache.overall_avg_miss_latency::total 48644.115843 # average overall miss latency
914system.cpu.dcache.blocked_cycles::no_mshrs 2745 # number of cycles access was blocked
915system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked
916system.cpu.dcache.blocked::no_mshrs 62 # number of cycles access was blocked
917system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
918system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.274194 # average number of cycles each access was blocked
919system.cpu.dcache.avg_blocked_cycles::no_targets 9.584270 # average number of cycles each access was blocked
920system.cpu.dcache.fast_writes 0 # number of fast writes performed
921system.cpu.dcache.cache_copies 0 # number of cache copies performed
922system.cpu.dcache.writebacks::writebacks 96304 # number of writebacks
923system.cpu.dcache.writebacks::total 96304 # number of writebacks
924system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489504 # number of ReadReq MSHR hits
925system.cpu.dcache.ReadReq_mshr_hits::total 489504 # number of ReadReq MSHR hits
926system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765580 # number of WriteReq MSHR hits
927system.cpu.dcache.WriteReq_mshr_hits::total 765580 # number of WriteReq MSHR hits
928system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
929system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
930system.cpu.dcache.demand_mshr_hits::cpu.data 1255084 # number of demand (read+write) MSHR hits
931system.cpu.dcache.demand_mshr_hits::total 1255084 # number of demand (read+write) MSHR hits
932system.cpu.dcache.overall_mshr_hits::cpu.data 1255084 # number of overall MSHR hits
933system.cpu.dcache.overall_mshr_hits::total 1255084 # number of overall MSHR hits
934system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464384 # number of ReadReq MSHR misses
935system.cpu.dcache.ReadReq_mshr_misses::total 1464384 # number of ReadReq MSHR misses
936system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76882 # number of WriteReq MSHR misses
937system.cpu.dcache.WriteReq_mshr_misses::total 76882 # number of WriteReq MSHR misses
938system.cpu.dcache.demand_mshr_misses::cpu.data 1541266 # number of demand (read+write) MSHR misses
939system.cpu.dcache.demand_mshr_misses::total 1541266 # number of demand (read+write) MSHR misses
940system.cpu.dcache.overall_mshr_misses::cpu.data 1541266 # number of overall MSHR misses
941system.cpu.dcache.overall_mshr_misses::total 1541266 # number of overall MSHR misses
942system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42754567776 # number of ReadReq MSHR miss cycles
943system.cpu.dcache.ReadReq_mshr_miss_latency::total 42754567776 # number of ReadReq MSHR miss cycles
944system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4832230139 # number of WriteReq MSHR miss cycles
945system.cpu.dcache.WriteReq_mshr_miss_latency::total 4832230139 # number of WriteReq MSHR miss cycles
946system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47586797915 # number of demand (read+write) MSHR miss cycles
947system.cpu.dcache.demand_mshr_miss_latency::total 47586797915 # number of demand (read+write) MSHR miss cycles
948system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47586797915 # number of overall MSHR miss cycles
949system.cpu.dcache.overall_mshr_miss_latency::total 47586797915 # number of overall MSHR miss cycles
950system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002096 # mshr miss rate for ReadReq accesses
951system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002096 # mshr miss rate for ReadReq accesses
952system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
953system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
954system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for demand accesses
955system.cpu.dcache.demand_mshr_miss_rate::total 0.001580 # mshr miss rate for demand accesses
956system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for overall accesses
957system.cpu.dcache.overall_mshr_miss_rate::total 0.001580 # mshr miss rate for overall accesses
958system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29196.281697 # average ReadReq mshr miss latency
959system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29196.281697 # average ReadReq mshr miss latency
960system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62852.555071 # average WriteReq mshr miss latency
961system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62852.555071 # average WriteReq mshr miss latency
962system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency
963system.cpu.dcache.demand_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency
964system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency
965system.cpu.dcache.overall_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency
966system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
967
968---------- End Simulation Statistics ----------
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