Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

Deleted Added

sdiff udiff text old ( 10726:8a20e2a1562d ) new ( 10736:4433fb00fa7d )

full compact

stats.txt (10726:8a20e2a1562d)	stats.txt (10736:4433fb00fa7d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.409399 # Number of seconds simulated 4sim_ticks 409399480000 # Number of ticks simulated 5final_tick 409399480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 93383 # Simulator instruction rate (inst/s) 8host_op_rate 114967 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59675446 # Simulator tick rate (ticks/s) 10host_mem_usage 317532 # Number of bytes of host memory used 11host_seconds 6860.43 # Real time elapsed on the host 12sim_insts 640649298 # Number of instructions simulated 13sim_ops 788724957 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7025088 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 12938560 # Number of bytes read from this memory 19system.physmem.bytes_read::total 20195840 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4244864 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4244864 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 109767 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 202165 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 315560 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 66326 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 66326 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 567153 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 17159494 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 31603753 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 49330400 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 567153 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 567153 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 10368513 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 10368513 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 10368513 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 567153 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 17159494 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 31603753 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 59698913 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 315560 # Number of read requests accepted 44system.physmem.writeReqs 66326 # Number of write requests accepted 45system.physmem.readBursts 315560 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 66326 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 20177344 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue 49system.physmem.bytesWritten 4238912 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 20195840 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 4244864 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 19910 # Per bank write bursts 56system.physmem.perBankRdBursts::1 19474 # Per bank write bursts 57system.physmem.perBankRdBursts::2 19822 # Per bank write bursts 58system.physmem.perBankRdBursts::3 19845 # Per bank write bursts 59system.physmem.perBankRdBursts::4 19720 # Per bank write bursts 60system.physmem.perBankRdBursts::5 20103 # Per bank write bursts 61system.physmem.perBankRdBursts::6 19622 # Per bank write bursts 62system.physmem.perBankRdBursts::7 19424 # Per bank write bursts 63system.physmem.perBankRdBursts::8 19577 # Per bank write bursts 64system.physmem.perBankRdBursts::9 19501 # Per bank write bursts 65system.physmem.perBankRdBursts::10 19475 # Per bank write bursts 66system.physmem.perBankRdBursts::11 19731 # Per bank write bursts 67system.physmem.perBankRdBursts::12 19558 # Per bank write bursts 68system.physmem.perBankRdBursts::13 20043 # Per bank write bursts 69system.physmem.perBankRdBursts::14 19546 # Per bank write bursts 70system.physmem.perBankRdBursts::15 19920 # Per bank write bursts 71system.physmem.perBankWrBursts::0 4269 # Per bank write bursts 72system.physmem.perBankWrBursts::1 4104 # Per bank write bursts 73system.physmem.perBankWrBursts::2 4141 # Per bank write bursts 74system.physmem.perBankWrBursts::3 4150 # Per bank write bursts 75system.physmem.perBankWrBursts::4 4244 # Per bank write bursts 76system.physmem.perBankWrBursts::5 4227 # Per bank write bursts 77system.physmem.perBankWrBursts::6 4174 # Per bank write bursts 78system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 83system.physmem.perBankWrBursts::12 4097 # Per bank write bursts 84system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 85system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 86system.physmem.perBankWrBursts::15 4154 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 409399425500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 315560 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 66326 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 122658 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 117599 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 14107 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 6797 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6389 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 7384 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 8395 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 8262 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 10480 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 4277 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 3294 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2442 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1850 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1337 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 589 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 613 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1000 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 1788 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2652 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 3312 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 3720 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4067 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4646 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 4886 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5091 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5229 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 5064 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 4821 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 4400 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 4184 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 4072 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 90 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 76 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 83 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 66 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 60 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 136638 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 178.677557 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 128.806703 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 198.419690 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 53973 39.50% 39.50% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 57563 42.13% 81.63% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 14775 10.81% 92.44% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1288 0.94% 93.38% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1420 1.04% 94.42% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1465 1.07% 95.50% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1207 0.88% 96.38% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1190 0.87% 97.25% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 3757 2.75% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 136638 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 68.784581 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 34.732770 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 517.054396 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-1023 4014 99.50% 99.50% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::1024-2047 8 0.20% 99.70% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::2048-3071 5 0.12% 99.83% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::7168-8191 3 0.07% 99.93% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.95% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::19456-20479 1 0.02% 100.00% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes 227system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::mean 16.418691 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::gmean 16.384198 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::stdev 1.147646 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::16 3405 84.41% 84.41% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::17 7 0.17% 84.58% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::18 450 11.16% 95.74% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::19 75 1.86% 97.60% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::20 34 0.84% 98.44% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::21 21 0.52% 98.96% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::22 13 0.32% 99.28% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::23 12 0.30% 99.58% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24 6 0.15% 99.73% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::25 6 0.15% 99.88% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::26 3 0.07% 99.95% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::27 2 0.05% 100.00% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads 244system.physmem.totQLat 9487812639 # Total ticks spent queuing 245system.physmem.totMemAccLat 15399143889 # Total ticks spent from burst creation until serviced by the DRAM 246system.physmem.totBusLat 1576355000 # Total ticks spent in databus transfers 247system.physmem.avgQLat 30094.15 # Average queueing delay per DRAM burst 248system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 249system.physmem.avgMemAccLat 48844.15 # Average memory access latency per DRAM burst 250system.physmem.avgRdBW 49.29 # Average DRAM read bandwidth in MiByte/s 251system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s 252system.physmem.avgRdBWSys 49.33 # Average system read bandwidth in MiByte/s 253system.physmem.avgWrBWSys 10.37 # Average system write bandwidth in MiByte/s 254system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 255system.physmem.busUtil 0.47 # Data bus utilization in percentage 256system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads 257system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes 258system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing 259system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing 260system.physmem.readRowHits 218399 # Number of row buffer hits during reads 261system.physmem.writeRowHits 26454 # Number of row buffer hits during writes 262system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads 263system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes 264system.physmem.avgGap 1072046.17 # Average gap between requests 265system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined 266system.physmem_0.actEnergy 517640760 # Energy for activate commands per rank (pJ) 267system.physmem_0.preEnergy 282442875 # Energy for precharge commands per rank (pJ) 268system.physmem_0.readEnergy 1231518600 # Energy for read commands per rank (pJ) 269system.physmem_0.writeEnergy 216464400 # Energy for write commands per rank (pJ) 270system.physmem_0.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) 271system.physmem_0.actBackEnergy 96784987680 # Energy for active background per rank (pJ) 272system.physmem_0.preBackEnergy 160736987250 # Energy for precharge background per rank (pJ) 273system.physmem_0.totalEnergy 286509617805 # Total energy per rank (pJ) 274system.physmem_0.averagePower 699.839198 # Core power per rank (mW) 275system.physmem_0.memoryStateTime::IDLE 266762765318 # Time in different power states 276system.physmem_0.memoryStateTime::REF 13670540000 # Time in different power states 277system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 278system.physmem_0.memoryStateTime::ACT 128960598682 # Time in different power states 279system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 280system.physmem_1.actEnergy 515168640 # Energy for activate commands per rank (pJ) 281system.physmem_1.preEnergy 281094000 # Energy for precharge commands per rank (pJ) 282system.physmem_1.readEnergy 1226955600 # Energy for read commands per rank (pJ) 283system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) 284system.physmem_1.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) 285system.physmem_1.actBackEnergy 96280028955 # Energy for active background per rank (pJ) 286system.physmem_1.preBackEnergy 161179933500 # Energy for precharge background per rank (pJ) 287system.physmem_1.totalEnergy 286435482375 # Total energy per rank (pJ) 288system.physmem_1.averagePower 699.658112 # Core power per rank (mW) 289system.physmem_1.memoryStateTime::IDLE 267502793659 # Time in different power states 290system.physmem_1.memoryStateTime::REF 13670540000 # Time in different power states 291system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 292system.physmem_1.memoryStateTime::ACT 128220707341 # Time in different power states 293system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 294system.cpu.branchPred.lookups 234006176 # Number of BP lookups 295system.cpu.branchPred.condPredicted 161868409 # Number of conditional branches predicted 296system.cpu.branchPred.condIncorrect 15514584 # Number of conditional branches incorrect 297system.cpu.branchPred.BTBLookups 121529948 # Number of BTB lookups 298system.cpu.branchPred.BTBHits 108213709 # Number of BTB hits 299system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 300system.cpu.branchPred.BTBHitPct 89.042833 # BTB Hit Percentage 301system.cpu.branchPred.usedRAS 25036783 # Number of times the RAS was used to get a target. 302system.cpu.branchPred.RASInCorrect 1300149 # Number of incorrect RAS predictions. 303system.cpu_clk_domain.clock 500 # Clock period in ticks 304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 313system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 314system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 315system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 316system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 317system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 322system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 323system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 324system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 333system.cpu.dtb.walker.walks 0 # Table walker walks requested 334system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.inst_hits 0 # ITB inst hits 342system.cpu.dtb.inst_misses 0 # ITB inst misses 343system.cpu.dtb.read_hits 0 # DTB read hits 344system.cpu.dtb.read_misses 0 # DTB read misses 345system.cpu.dtb.write_hits 0 # DTB write hits 346system.cpu.dtb.write_misses 0 # DTB write misses 347system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 348system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 349system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 350system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 351system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 352system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 353system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 354system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 355system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 356system.cpu.dtb.read_accesses 0 # DTB read accesses 357system.cpu.dtb.write_accesses 0 # DTB write accesses 358system.cpu.dtb.inst_accesses 0 # ITB inst accesses 359system.cpu.dtb.hits 0 # DTB hits 360system.cpu.dtb.misses 0 # DTB misses 361system.cpu.dtb.accesses 0 # DTB accesses 362system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 371system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 372system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 373system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 374system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 375system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 376system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 377system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 378system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 379system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 380system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 381system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 382system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 383system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 384system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 386system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 387system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 388system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 389system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 390system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 391system.cpu.itb.walker.walks 0 # Table walker walks requested 392system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.inst_hits 0 # ITB inst hits 400system.cpu.itb.inst_misses 0 # ITB inst misses 401system.cpu.itb.read_hits 0 # DTB read hits 402system.cpu.itb.read_misses 0 # DTB read misses 403system.cpu.itb.write_hits 0 # DTB write hits 404system.cpu.itb.write_misses 0 # DTB write misses 405system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 406system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 408system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 409system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 410system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu.itb.read_accesses 0 # DTB read accesses 415system.cpu.itb.write_accesses 0 # DTB write accesses 416system.cpu.itb.inst_accesses 0 # ITB inst accesses 417system.cpu.itb.hits 0 # DTB hits 418system.cpu.itb.misses 0 # DTB misses 419system.cpu.itb.accesses 0 # DTB accesses 420system.cpu.workload.num_syscalls 673 # Number of system calls 421system.cpu.numCycles 818798961 # number of cpu cycles simulated 422system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 423system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 424system.cpu.fetch.icacheStallCycles 84078294 # Number of cycles fetch is stalled on an Icache miss 425system.cpu.fetch.Insts 1200783068 # Number of instructions fetch has processed 426system.cpu.fetch.Branches 234006176 # Number of branches that fetch encountered 427system.cpu.fetch.predictedBranches 133250492 # Number of branches that fetch has predicted taken 428system.cpu.fetch.Cycles 718844861 # Number of cycles fetch has run and was not squashing or blocked 429system.cpu.fetch.SquashCycles 31063585 # Number of cycles fetch has spent squashing 430system.cpu.fetch.MiscStallCycles 2466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 431system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps 432system.cpu.fetch.IcacheWaitRetryStallCycles 3349 # Number of stall cycles due to full MSHR 433system.cpu.fetch.CacheLines 370656305 # Number of cache lines fetched 434system.cpu.fetch.IcacheSquashes 652882 # Number of outstanding Icache misses that were squashed 435system.cpu.fetch.rateDist::samples 818460793 # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::mean 1.833394 # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::stdev 1.163540 # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::0 136795118 16.71% 16.71% # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::1 223180654 27.27% 43.98% # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::2 98074923 11.98% 55.96% # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::3 360410098 44.04% 100.00% # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::total 818460793 # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.branchRate 0.285792 # Number of branch fetches per cycle 448system.cpu.fetch.rate 1.466518 # Number of inst fetches per cycle 449system.cpu.decode.IdleCycles 119991092 # Number of cycles decode is idle 450system.cpu.decode.BlockedCycles 159658898 # Number of cycles decode is blocked 451system.cpu.decode.RunCycles 484662986 # Number of cycles decode is running 452system.cpu.decode.UnblockCycles 38629701 # Number of cycles decode is unblocking 453system.cpu.decode.SquashCycles 15518116 # Number of cycles decode is squashing 454system.cpu.decode.BranchResolved 25135087 # Number of times decode resolved a branch 455system.cpu.decode.BranchMispred 13824 # Number of times decode detected a branch misprediction 456system.cpu.decode.DecodedInsts 1248129900 # Number of instructions handled by decode 457system.cpu.decode.SquashedInsts 39966537 # Number of squashed instructions handled by decode 458system.cpu.rename.SquashCycles 15518116 # Number of cycles rename is squashing 459system.cpu.rename.IdleCycles 176998470 # Number of cycles rename is idle 460system.cpu.rename.BlockCycles 78894904 # Number of cycles rename is blocking 461system.cpu.rename.serializeStallCycles 210510 # count of cycles rename stalled for serializing inst 462system.cpu.rename.RunCycles 464956548 # Number of cycles rename is running 463system.cpu.rename.UnblockCycles 81882245 # Number of cycles rename is unblocking 464system.cpu.rename.RenamedInsts 1190637892 # Number of instructions processed by rename 465system.cpu.rename.SquashedInsts 25457774 # Number of squashed instructions processed by rename 466system.cpu.rename.ROBFullEvents 24955109 # Number of times rename has blocked due to ROB full 467system.cpu.rename.IQFullEvents 2267146 # Number of times rename has blocked due to IQ full 468system.cpu.rename.LQFullEvents 41533192 # Number of times rename has blocked due to LQ full 469system.cpu.rename.SQFullEvents 1699566 # Number of times rename has blocked due to SQ full 470system.cpu.rename.RenamedOperands 1225425199 # Number of destination operands rename has renamed 471system.cpu.rename.RenameLookups 5812490436 # Number of register rename lookups that rename has made 472system.cpu.rename.int_rename_lookups 1358169789 # Number of integer rename lookups 473system.cpu.rename.fp_rename_lookups 40876588 # Number of floating rename lookups 474system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed 475system.cpu.rename.UndoneMaps 350646969 # Number of HB maps that are undone due to squashing 476system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed 477system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed 478system.cpu.rename.skidInsts 108140115 # count of insts added to the skid buffer 479system.cpu.memDep0.insertedLoads 366205100 # Number of loads inserted to the mem dependence unit. 480system.cpu.memDep0.insertedStores 236096667 # Number of stores inserted to the mem dependence unit. 481system.cpu.memDep0.conflictingLoads 1646330 # Number of conflicting loads. 482system.cpu.memDep0.conflictingStores 5328678 # Number of conflicting stores. 483system.cpu.iq.iqInstsAdded 1168639452 # Number of instructions added to the IQ (excludes non-spec) 484system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ 485system.cpu.iq.iqInstsIssued 1017122920 # Number of instructions issued 486system.cpu.iq.iqSquashedInstsIssued 18523621 # Number of squashed instructions issued 487system.cpu.iq.iqSquashedInstsExamined 379819992 # Number of squashed instructions iterated over during squash; mainly for profiling 488system.cpu.iq.iqSquashedOperandsExamined 1032577011 # Number of squashed operands that are examined and possibly removed from graph 489system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed 490system.cpu.iq.issued_per_cycle::samples 818460793 # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::mean 1.242727 # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::stdev 1.084979 # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::0 260810349 31.87% 31.87% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::1 227739162 27.83% 59.69% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::2 216495712 26.45% 86.14% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::3 97269955 11.88% 98.03% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::4 16145606 1.97% 100.00% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::total 818460793 # Number of insts issued each cycle 507system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 508system.cpu.iq.fu_full::IntAlu 64512117 19.12% 19.12% # attempts to use FU when none available 509system.cpu.iq.fu_full::IntMult 18144 0.01% 19.12% # attempts to use FU when none available 510system.cpu.iq.fu_full::IntDiv 0 0.00% 19.12% # attempts to use FU when none available 511system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.12% # attempts to use FU when none available 512system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.12% # attempts to use FU when none available 513system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.12% # attempts to use FU when none available 514system.cpu.iq.fu_full::FloatMult 0 0.00% 19.12% # attempts to use FU when none available 515system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.12% # attempts to use FU when none available 516system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.12% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.12% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.12% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.12% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.12% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.12% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.12% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdMult 0 0.00% 19.12% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.12% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdShift 0 0.00% 19.12% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.12% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.12% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.12% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.12% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.12% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.31% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available 537system.cpu.iq.fu_full::MemRead 155573719 46.11% 65.42% # attempts to use FU when none available 538system.cpu.iq.fu_full::MemWrite 116674794 34.58% 100.00% # attempts to use FU when none available 539system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 540system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 541system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 542system.cpu.iq.FU_type_0::IntAlu 456371749 44.87% 44.87% # Type of FU issued 543system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued 544system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued 545system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued 546system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued 547system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued 548system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued 549system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued 550system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued 571system.cpu.iq.FU_type_0::MemRead 322115143 31.67% 78.80% # Type of FU issued 572system.cpu.iq.FU_type_0::MemWrite 215585851 21.20% 100.00% # Type of FU issued 573system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 574system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 575system.cpu.iq.FU_type_0::total 1017122920 # Type of FU issued 576system.cpu.iq.rate 1.242213 # Inst issue rate 577system.cpu.iq.fu_busy_cnt 337415663 # FU busy when requested 578system.cpu.iq.fu_busy_rate 0.331735 # FU busy rate (busy events/executed inst) 579system.cpu.iq.int_inst_queue_reads 3146768879 # Number of integer instruction queue reads 580system.cpu.iq.int_inst_queue_writes 1504924384 # Number of integer instruction queue writes 581system.cpu.iq.int_inst_queue_wakeup_accesses 934270592 # Number of integer instruction queue wakeup accesses 582system.cpu.iq.fp_inst_queue_reads 61877038 # Number of floating instruction queue reads 583system.cpu.iq.fp_inst_queue_writes 43565805 # Number of floating instruction queue writes 584system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses 585system.cpu.iq.int_alu_accesses 1320728240 # Number of integer alu accesses 586system.cpu.iq.fp_alu_accesses 33810343 # Number of floating point alu accesses 587system.cpu.iew.lsq.thread0.forwLoads 9960122 # Number of loads that had data forwarded from stores 588system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 589system.cpu.iew.lsq.thread0.squashedLoads 113964162 # Number of loads squashed 590system.cpu.iew.lsq.thread0.ignoredResponses 1106 # Number of memory responses ignored because the instruction is squashed 591system.cpu.iew.lsq.thread0.memOrderViolation 18388 # Number of memory ordering violations 592system.cpu.iew.lsq.thread0.squashedStores 107116171 # Number of stores squashed 593system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 594system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 595system.cpu.iew.lsq.thread0.rescheduledLoads 2065787 # Number of loads that were rescheduled 596system.cpu.iew.lsq.thread0.cacheBlocked 22375 # Number of times an access to memory failed due to the cache being blocked 597system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 598system.cpu.iew.iewSquashCycles 15518116 # Number of cycles IEW is squashing 599system.cpu.iew.iewBlockCycles 35326355 # Number of cycles IEW is blocking 600system.cpu.iew.iewUnblockCycles 41902 # Number of cycles IEW is unblocking 601system.cpu.iew.iewDispatchedInsts 1168657365 # Number of instructions dispatched to IQ 602system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 603system.cpu.iew.iewDispLoadInsts 366205100 # Number of dispatched load instructions 604system.cpu.iew.iewDispStoreInsts 236096667 # Number of dispatched store instructions 605system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions 606system.cpu.iew.iewIQFullEvents 109 # Number of times the IQ has become full, causing a stall 607system.cpu.iew.iewLSQFullEvents 45517 # Number of times the LSQ has become full, causing a stall 608system.cpu.iew.memOrderViolationEvents 18388 # Number of memory order violations 609system.cpu.iew.predictedTakenIncorrect 15437362 # Number of branches that were predicted taken incorrectly 610system.cpu.iew.predictedNotTakenIncorrect 3784555 # Number of branches that were predicted not taken incorrectly 611system.cpu.iew.branchMispredicts 19221917 # Number of branch mispredicts detected at execute 612system.cpu.iew.iewExecutedInsts 974750423 # Number of executed instructions 613system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed 614system.cpu.iew.iewExecSquashedInsts 42372497 # Number of squashed instructions skipped in execute 615system.cpu.iew.exec_swp 0 # number of swp insts executed 616system.cpu.iew.exec_nop 5553 # number of nop insts executed 617system.cpu.iew.exec_refs 497763737 # number of memory reference insts executed 618system.cpu.iew.exec_branches 150613650 # Number of branches executed 619system.cpu.iew.exec_stores 194466026 # Number of stores executed 620system.cpu.iew.exec_rate 1.190464 # Inst execution rate 621system.cpu.iew.wb_sent 963723367 # cumulative count of insts sent to commit 622system.cpu.iew.wb_count 960423035 # cumulative count of insts written-back 623system.cpu.iew.wb_producers 536681402 # num instructions producing a value 624system.cpu.iew.wb_consumers 893284482 # num instructions consuming a value 625system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 626system.cpu.iew.wb_rate 1.172966 # insts written-back per cycle 627system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back 628system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 629system.cpu.commit.commitSquashedInsts 357409752 # The number of squashed insts skipped by commit 630system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards 631system.cpu.commit.branchMispredicts 15500908 # The number of times a branch was mispredicted 632system.cpu.commit.committed_per_cycle::samples 767640271 # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::mean 1.027474 # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::stdev 1.786859 # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::0 430932808 56.14% 56.14% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::1 172476946 22.47% 78.61% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::2 73566678 9.58% 88.19% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::3 31624021 4.12% 92.31% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::4 8540196 1.11% 93.42% # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::5 14250754 1.86% 95.28% # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::6 7269409 0.95% 96.22% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::7 6618976 0.86% 97.09% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::8 22360483 2.91% 100.00% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::total 767640271 # Number of insts commited each cycle 649system.cpu.commit.committedInsts 640654410 # Number of instructions committed 650system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed 651system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 652system.cpu.commit.refs 381221434 # Number of memory references committed 653system.cpu.commit.loads 252240938 # Number of loads committed 654system.cpu.commit.membars 5740 # Number of memory barriers committed 655system.cpu.commit.branches 137364859 # Number of branches committed 656system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. 657system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. 658system.cpu.commit.function_calls 19275340 # Number of function calls committed. 659system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 660system.cpu.commit.op_class_0::IntAlu 385756793 48.91% 48.91% # Class of committed instruction 661system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 662system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 663system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 664system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 665system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 666system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 667system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 668system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 689system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 690system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 691system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 692system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 693system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction 694system.cpu.commit.bw_lim_events 22360483 # number cycles where commit BW limit reached	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.409399 # Number of seconds simulated 4sim_ticks 409399480000 # Number of ticks simulated 5final_tick 409399480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 93383 # Simulator instruction rate (inst/s) 8host_op_rate 114967 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59675446 # Simulator tick rate (ticks/s) 10host_mem_usage 317532 # Number of bytes of host memory used 11host_seconds 6860.43 # Real time elapsed on the host 12sim_insts 640649298 # Number of instructions simulated 13sim_ops 788724957 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7025088 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 12938560 # Number of bytes read from this memory 19system.physmem.bytes_read::total 20195840 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4244864 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4244864 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 109767 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 202165 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 315560 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 66326 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 66326 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 567153 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 17159494 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 31603753 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 49330400 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 567153 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 567153 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 10368513 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 10368513 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 10368513 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 567153 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 17159494 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 31603753 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 59698913 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 315560 # Number of read requests accepted 44system.physmem.writeReqs 66326 # Number of write requests accepted 45system.physmem.readBursts 315560 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 66326 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 20177344 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue 49system.physmem.bytesWritten 4238912 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 20195840 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 4244864 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 19910 # Per bank write bursts 56system.physmem.perBankRdBursts::1 19474 # Per bank write bursts 57system.physmem.perBankRdBursts::2 19822 # Per bank write bursts 58system.physmem.perBankRdBursts::3 19845 # Per bank write bursts 59system.physmem.perBankRdBursts::4 19720 # Per bank write bursts 60system.physmem.perBankRdBursts::5 20103 # Per bank write bursts 61system.physmem.perBankRdBursts::6 19622 # Per bank write bursts 62system.physmem.perBankRdBursts::7 19424 # Per bank write bursts 63system.physmem.perBankRdBursts::8 19577 # Per bank write bursts 64system.physmem.perBankRdBursts::9 19501 # Per bank write bursts 65system.physmem.perBankRdBursts::10 19475 # Per bank write bursts 66system.physmem.perBankRdBursts::11 19731 # Per bank write bursts 67system.physmem.perBankRdBursts::12 19558 # Per bank write bursts 68system.physmem.perBankRdBursts::13 20043 # Per bank write bursts 69system.physmem.perBankRdBursts::14 19546 # Per bank write bursts 70system.physmem.perBankRdBursts::15 19920 # Per bank write bursts 71system.physmem.perBankWrBursts::0 4269 # Per bank write bursts 72system.physmem.perBankWrBursts::1 4104 # Per bank write bursts 73system.physmem.perBankWrBursts::2 4141 # Per bank write bursts 74system.physmem.perBankWrBursts::3 4150 # Per bank write bursts 75system.physmem.perBankWrBursts::4 4244 # Per bank write bursts 76system.physmem.perBankWrBursts::5 4227 # Per bank write bursts 77system.physmem.perBankWrBursts::6 4174 # Per bank write bursts 78system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 83system.physmem.perBankWrBursts::12 4097 # Per bank write bursts 84system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 85system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 86system.physmem.perBankWrBursts::15 4154 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 409399425500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 315560 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 66326 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 122658 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 117599 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 14107 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 6797 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6389 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 7384 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 8395 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 8262 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 10480 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 4277 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 3294 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2442 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1850 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1337 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 589 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 613 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1000 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 1788 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2652 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 3312 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 3720 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4067 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4646 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 4886 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5091 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5229 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 5064 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 4821 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 4400 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 4184 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 4072 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 90 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 76 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 83 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 66 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 60 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 136638 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 178.677557 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 128.806703 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 198.419690 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 53973 39.50% 39.50% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 57563 42.13% 81.63% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 14775 10.81% 92.44% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1288 0.94% 93.38% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1420 1.04% 94.42% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1465 1.07% 95.50% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1207 0.88% 96.38% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1190 0.87% 97.25% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 3757 2.75% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 136638 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 68.784581 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 34.732770 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 517.054396 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-1023 4014 99.50% 99.50% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::1024-2047 8 0.20% 99.70% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::2048-3071 5 0.12% 99.83% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::7168-8191 3 0.07% 99.93% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.95% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::19456-20479 1 0.02% 100.00% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes 227system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::mean 16.418691 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::gmean 16.384198 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::stdev 1.147646 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::16 3405 84.41% 84.41% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::17 7 0.17% 84.58% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::18 450 11.16% 95.74% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::19 75 1.86% 97.60% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::20 34 0.84% 98.44% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::21 21 0.52% 98.96% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::22 13 0.32% 99.28% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::23 12 0.30% 99.58% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24 6 0.15% 99.73% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::25 6 0.15% 99.88% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::26 3 0.07% 99.95% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::27 2 0.05% 100.00% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads 244system.physmem.totQLat 9487812639 # Total ticks spent queuing 245system.physmem.totMemAccLat 15399143889 # Total ticks spent from burst creation until serviced by the DRAM 246system.physmem.totBusLat 1576355000 # Total ticks spent in databus transfers 247system.physmem.avgQLat 30094.15 # Average queueing delay per DRAM burst 248system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 249system.physmem.avgMemAccLat 48844.15 # Average memory access latency per DRAM burst 250system.physmem.avgRdBW 49.29 # Average DRAM read bandwidth in MiByte/s 251system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s 252system.physmem.avgRdBWSys 49.33 # Average system read bandwidth in MiByte/s 253system.physmem.avgWrBWSys 10.37 # Average system write bandwidth in MiByte/s 254system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 255system.physmem.busUtil 0.47 # Data bus utilization in percentage 256system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads 257system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes 258system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing 259system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing 260system.physmem.readRowHits 218399 # Number of row buffer hits during reads 261system.physmem.writeRowHits 26454 # Number of row buffer hits during writes 262system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads 263system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes 264system.physmem.avgGap 1072046.17 # Average gap between requests 265system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined 266system.physmem_0.actEnergy 517640760 # Energy for activate commands per rank (pJ) 267system.physmem_0.preEnergy 282442875 # Energy for precharge commands per rank (pJ) 268system.physmem_0.readEnergy 1231518600 # Energy for read commands per rank (pJ) 269system.physmem_0.writeEnergy 216464400 # Energy for write commands per rank (pJ) 270system.physmem_0.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) 271system.physmem_0.actBackEnergy 96784987680 # Energy for active background per rank (pJ) 272system.physmem_0.preBackEnergy 160736987250 # Energy for precharge background per rank (pJ) 273system.physmem_0.totalEnergy 286509617805 # Total energy per rank (pJ) 274system.physmem_0.averagePower 699.839198 # Core power per rank (mW) 275system.physmem_0.memoryStateTime::IDLE 266762765318 # Time in different power states 276system.physmem_0.memoryStateTime::REF 13670540000 # Time in different power states 277system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 278system.physmem_0.memoryStateTime::ACT 128960598682 # Time in different power states 279system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 280system.physmem_1.actEnergy 515168640 # Energy for activate commands per rank (pJ) 281system.physmem_1.preEnergy 281094000 # Energy for precharge commands per rank (pJ) 282system.physmem_1.readEnergy 1226955600 # Energy for read commands per rank (pJ) 283system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) 284system.physmem_1.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) 285system.physmem_1.actBackEnergy 96280028955 # Energy for active background per rank (pJ) 286system.physmem_1.preBackEnergy 161179933500 # Energy for precharge background per rank (pJ) 287system.physmem_1.totalEnergy 286435482375 # Total energy per rank (pJ) 288system.physmem_1.averagePower 699.658112 # Core power per rank (mW) 289system.physmem_1.memoryStateTime::IDLE 267502793659 # Time in different power states 290system.physmem_1.memoryStateTime::REF 13670540000 # Time in different power states 291system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 292system.physmem_1.memoryStateTime::ACT 128220707341 # Time in different power states 293system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 294system.cpu.branchPred.lookups 234006176 # Number of BP lookups 295system.cpu.branchPred.condPredicted 161868409 # Number of conditional branches predicted 296system.cpu.branchPred.condIncorrect 15514584 # Number of conditional branches incorrect 297system.cpu.branchPred.BTBLookups 121529948 # Number of BTB lookups 298system.cpu.branchPred.BTBHits 108213709 # Number of BTB hits 299system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 300system.cpu.branchPred.BTBHitPct 89.042833 # BTB Hit Percentage 301system.cpu.branchPred.usedRAS 25036783 # Number of times the RAS was used to get a target. 302system.cpu.branchPred.RASInCorrect 1300149 # Number of incorrect RAS predictions. 303system.cpu_clk_domain.clock 500 # Clock period in ticks 304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 313system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 314system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 315system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 316system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 317system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 322system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 323system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 324system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 333system.cpu.dtb.walker.walks 0 # Table walker walks requested 334system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.inst_hits 0 # ITB inst hits 342system.cpu.dtb.inst_misses 0 # ITB inst misses 343system.cpu.dtb.read_hits 0 # DTB read hits 344system.cpu.dtb.read_misses 0 # DTB read misses 345system.cpu.dtb.write_hits 0 # DTB write hits 346system.cpu.dtb.write_misses 0 # DTB write misses 347system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 348system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 349system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 350system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 351system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 352system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 353system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 354system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 355system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 356system.cpu.dtb.read_accesses 0 # DTB read accesses 357system.cpu.dtb.write_accesses 0 # DTB write accesses 358system.cpu.dtb.inst_accesses 0 # ITB inst accesses 359system.cpu.dtb.hits 0 # DTB hits 360system.cpu.dtb.misses 0 # DTB misses 361system.cpu.dtb.accesses 0 # DTB accesses 362system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 371system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 372system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 373system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 374system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 375system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 376system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 377system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 378system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 379system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 380system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 381system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 382system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 383system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 384system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 386system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 387system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 388system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 389system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 390system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 391system.cpu.itb.walker.walks 0 # Table walker walks requested 392system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.inst_hits 0 # ITB inst hits 400system.cpu.itb.inst_misses 0 # ITB inst misses 401system.cpu.itb.read_hits 0 # DTB read hits 402system.cpu.itb.read_misses 0 # DTB read misses 403system.cpu.itb.write_hits 0 # DTB write hits 404system.cpu.itb.write_misses 0 # DTB write misses 405system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 406system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 408system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 409system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 410system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu.itb.read_accesses 0 # DTB read accesses 415system.cpu.itb.write_accesses 0 # DTB write accesses 416system.cpu.itb.inst_accesses 0 # ITB inst accesses 417system.cpu.itb.hits 0 # DTB hits 418system.cpu.itb.misses 0 # DTB misses 419system.cpu.itb.accesses 0 # DTB accesses 420system.cpu.workload.num_syscalls 673 # Number of system calls 421system.cpu.numCycles 818798961 # number of cpu cycles simulated 422system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 423system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 424system.cpu.fetch.icacheStallCycles 84078294 # Number of cycles fetch is stalled on an Icache miss 425system.cpu.fetch.Insts 1200783068 # Number of instructions fetch has processed 426system.cpu.fetch.Branches 234006176 # Number of branches that fetch encountered 427system.cpu.fetch.predictedBranches 133250492 # Number of branches that fetch has predicted taken 428system.cpu.fetch.Cycles 718844861 # Number of cycles fetch has run and was not squashing or blocked 429system.cpu.fetch.SquashCycles 31063585 # Number of cycles fetch has spent squashing 430system.cpu.fetch.MiscStallCycles 2466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 431system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps 432system.cpu.fetch.IcacheWaitRetryStallCycles 3349 # Number of stall cycles due to full MSHR 433system.cpu.fetch.CacheLines 370656305 # Number of cache lines fetched 434system.cpu.fetch.IcacheSquashes 652882 # Number of outstanding Icache misses that were squashed 435system.cpu.fetch.rateDist::samples 818460793 # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::mean 1.833394 # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::stdev 1.163540 # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::0 136795118 16.71% 16.71% # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::1 223180654 27.27% 43.98% # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::2 98074923 11.98% 55.96% # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::3 360410098 44.04% 100.00% # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::total 818460793 # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.branchRate 0.285792 # Number of branch fetches per cycle 448system.cpu.fetch.rate 1.466518 # Number of inst fetches per cycle 449system.cpu.decode.IdleCycles 119991092 # Number of cycles decode is idle 450system.cpu.decode.BlockedCycles 159658898 # Number of cycles decode is blocked 451system.cpu.decode.RunCycles 484662986 # Number of cycles decode is running 452system.cpu.decode.UnblockCycles 38629701 # Number of cycles decode is unblocking 453system.cpu.decode.SquashCycles 15518116 # Number of cycles decode is squashing 454system.cpu.decode.BranchResolved 25135087 # Number of times decode resolved a branch 455system.cpu.decode.BranchMispred 13824 # Number of times decode detected a branch misprediction 456system.cpu.decode.DecodedInsts 1248129900 # Number of instructions handled by decode 457system.cpu.decode.SquashedInsts 39966537 # Number of squashed instructions handled by decode 458system.cpu.rename.SquashCycles 15518116 # Number of cycles rename is squashing 459system.cpu.rename.IdleCycles 176998470 # Number of cycles rename is idle 460system.cpu.rename.BlockCycles 78894904 # Number of cycles rename is blocking 461system.cpu.rename.serializeStallCycles 210510 # count of cycles rename stalled for serializing inst 462system.cpu.rename.RunCycles 464956548 # Number of cycles rename is running 463system.cpu.rename.UnblockCycles 81882245 # Number of cycles rename is unblocking 464system.cpu.rename.RenamedInsts 1190637892 # Number of instructions processed by rename 465system.cpu.rename.SquashedInsts 25457774 # Number of squashed instructions processed by rename 466system.cpu.rename.ROBFullEvents 24955109 # Number of times rename has blocked due to ROB full 467system.cpu.rename.IQFullEvents 2267146 # Number of times rename has blocked due to IQ full 468system.cpu.rename.LQFullEvents 41533192 # Number of times rename has blocked due to LQ full 469system.cpu.rename.SQFullEvents 1699566 # Number of times rename has blocked due to SQ full 470system.cpu.rename.RenamedOperands 1225425199 # Number of destination operands rename has renamed 471system.cpu.rename.RenameLookups 5812490436 # Number of register rename lookups that rename has made 472system.cpu.rename.int_rename_lookups 1358169789 # Number of integer rename lookups 473system.cpu.rename.fp_rename_lookups 40876588 # Number of floating rename lookups 474system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed 475system.cpu.rename.UndoneMaps 350646969 # Number of HB maps that are undone due to squashing 476system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed 477system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed 478system.cpu.rename.skidInsts 108140115 # count of insts added to the skid buffer 479system.cpu.memDep0.insertedLoads 366205100 # Number of loads inserted to the mem dependence unit. 480system.cpu.memDep0.insertedStores 236096667 # Number of stores inserted to the mem dependence unit. 481system.cpu.memDep0.conflictingLoads 1646330 # Number of conflicting loads. 482system.cpu.memDep0.conflictingStores 5328678 # Number of conflicting stores. 483system.cpu.iq.iqInstsAdded 1168639452 # Number of instructions added to the IQ (excludes non-spec) 484system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ 485system.cpu.iq.iqInstsIssued 1017122920 # Number of instructions issued 486system.cpu.iq.iqSquashedInstsIssued 18523621 # Number of squashed instructions issued 487system.cpu.iq.iqSquashedInstsExamined 379819992 # Number of squashed instructions iterated over during squash; mainly for profiling 488system.cpu.iq.iqSquashedOperandsExamined 1032577011 # Number of squashed operands that are examined and possibly removed from graph 489system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed 490system.cpu.iq.issued_per_cycle::samples 818460793 # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::mean 1.242727 # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::stdev 1.084979 # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::0 260810349 31.87% 31.87% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::1 227739162 27.83% 59.69% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::2 216495712 26.45% 86.14% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::3 97269955 11.88% 98.03% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::4 16145606 1.97% 100.00% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::total 818460793 # Number of insts issued each cycle 507system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 508system.cpu.iq.fu_full::IntAlu 64512117 19.12% 19.12% # attempts to use FU when none available 509system.cpu.iq.fu_full::IntMult 18144 0.01% 19.12% # attempts to use FU when none available 510system.cpu.iq.fu_full::IntDiv 0 0.00% 19.12% # attempts to use FU when none available 511system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.12% # attempts to use FU when none available 512system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.12% # attempts to use FU when none available 513system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.12% # attempts to use FU when none available 514system.cpu.iq.fu_full::FloatMult 0 0.00% 19.12% # attempts to use FU when none available 515system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.12% # attempts to use FU when none available 516system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.12% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.12% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.12% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.12% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.12% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.12% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.12% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdMult 0 0.00% 19.12% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.12% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdShift 0 0.00% 19.12% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.12% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.12% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.12% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.12% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.12% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.31% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available 537system.cpu.iq.fu_full::MemRead 155573719 46.11% 65.42% # attempts to use FU when none available 538system.cpu.iq.fu_full::MemWrite 116674794 34.58% 100.00% # attempts to use FU when none available 539system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 540system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 541system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 542system.cpu.iq.FU_type_0::IntAlu 456371749 44.87% 44.87% # Type of FU issued 543system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued 544system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued 545system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued 546system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued 547system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued 548system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued 549system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued 550system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued 571system.cpu.iq.FU_type_0::MemRead 322115143 31.67% 78.80% # Type of FU issued 572system.cpu.iq.FU_type_0::MemWrite 215585851 21.20% 100.00% # Type of FU issued 573system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 574system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 575system.cpu.iq.FU_type_0::total 1017122920 # Type of FU issued 576system.cpu.iq.rate 1.242213 # Inst issue rate 577system.cpu.iq.fu_busy_cnt 337415663 # FU busy when requested 578system.cpu.iq.fu_busy_rate 0.331735 # FU busy rate (busy events/executed inst) 579system.cpu.iq.int_inst_queue_reads 3146768879 # Number of integer instruction queue reads 580system.cpu.iq.int_inst_queue_writes 1504924384 # Number of integer instruction queue writes 581system.cpu.iq.int_inst_queue_wakeup_accesses 934270592 # Number of integer instruction queue wakeup accesses 582system.cpu.iq.fp_inst_queue_reads 61877038 # Number of floating instruction queue reads 583system.cpu.iq.fp_inst_queue_writes 43565805 # Number of floating instruction queue writes 584system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses 585system.cpu.iq.int_alu_accesses 1320728240 # Number of integer alu accesses 586system.cpu.iq.fp_alu_accesses 33810343 # Number of floating point alu accesses 587system.cpu.iew.lsq.thread0.forwLoads 9960122 # Number of loads that had data forwarded from stores 588system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 589system.cpu.iew.lsq.thread0.squashedLoads 113964162 # Number of loads squashed 590system.cpu.iew.lsq.thread0.ignoredResponses 1106 # Number of memory responses ignored because the instruction is squashed 591system.cpu.iew.lsq.thread0.memOrderViolation 18388 # Number of memory ordering violations 592system.cpu.iew.lsq.thread0.squashedStores 107116171 # Number of stores squashed 593system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 594system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 595system.cpu.iew.lsq.thread0.rescheduledLoads 2065787 # Number of loads that were rescheduled 596system.cpu.iew.lsq.thread0.cacheBlocked 22375 # Number of times an access to memory failed due to the cache being blocked 597system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 598system.cpu.iew.iewSquashCycles 15518116 # Number of cycles IEW is squashing 599system.cpu.iew.iewBlockCycles 35326355 # Number of cycles IEW is blocking 600system.cpu.iew.iewUnblockCycles 41902 # Number of cycles IEW is unblocking 601system.cpu.iew.iewDispatchedInsts 1168657365 # Number of instructions dispatched to IQ 602system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 603system.cpu.iew.iewDispLoadInsts 366205100 # Number of dispatched load instructions 604system.cpu.iew.iewDispStoreInsts 236096667 # Number of dispatched store instructions 605system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions 606system.cpu.iew.iewIQFullEvents 109 # Number of times the IQ has become full, causing a stall 607system.cpu.iew.iewLSQFullEvents 45517 # Number of times the LSQ has become full, causing a stall 608system.cpu.iew.memOrderViolationEvents 18388 # Number of memory order violations 609system.cpu.iew.predictedTakenIncorrect 15437362 # Number of branches that were predicted taken incorrectly 610system.cpu.iew.predictedNotTakenIncorrect 3784555 # Number of branches that were predicted not taken incorrectly 611system.cpu.iew.branchMispredicts 19221917 # Number of branch mispredicts detected at execute 612system.cpu.iew.iewExecutedInsts 974750423 # Number of executed instructions 613system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed 614system.cpu.iew.iewExecSquashedInsts 42372497 # Number of squashed instructions skipped in execute 615system.cpu.iew.exec_swp 0 # number of swp insts executed 616system.cpu.iew.exec_nop 5553 # number of nop insts executed 617system.cpu.iew.exec_refs 497763737 # number of memory reference insts executed 618system.cpu.iew.exec_branches 150613650 # Number of branches executed 619system.cpu.iew.exec_stores 194466026 # Number of stores executed 620system.cpu.iew.exec_rate 1.190464 # Inst execution rate 621system.cpu.iew.wb_sent 963723367 # cumulative count of insts sent to commit 622system.cpu.iew.wb_count 960423035 # cumulative count of insts written-back 623system.cpu.iew.wb_producers 536681402 # num instructions producing a value 624system.cpu.iew.wb_consumers 893284482 # num instructions consuming a value 625system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 626system.cpu.iew.wb_rate 1.172966 # insts written-back per cycle 627system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back 628system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 629system.cpu.commit.commitSquashedInsts 357409752 # The number of squashed insts skipped by commit 630system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards 631system.cpu.commit.branchMispredicts 15500908 # The number of times a branch was mispredicted 632system.cpu.commit.committed_per_cycle::samples 767640271 # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::mean 1.027474 # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::stdev 1.786859 # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::0 430932808 56.14% 56.14% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::1 172476946 22.47% 78.61% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::2 73566678 9.58% 88.19% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::3 31624021 4.12% 92.31% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::4 8540196 1.11% 93.42% # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::5 14250754 1.86% 95.28% # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::6 7269409 0.95% 96.22% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::7 6618976 0.86% 97.09% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::8 22360483 2.91% 100.00% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::total 767640271 # Number of insts commited each cycle 649system.cpu.commit.committedInsts 640654410 # Number of instructions committed 650system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed 651system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 652system.cpu.commit.refs 381221434 # Number of memory references committed 653system.cpu.commit.loads 252240938 # Number of loads committed 654system.cpu.commit.membars 5740 # Number of memory barriers committed 655system.cpu.commit.branches 137364859 # Number of branches committed 656system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. 657system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. 658system.cpu.commit.function_calls 19275340 # Number of function calls committed. 659system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 660system.cpu.commit.op_class_0::IntAlu 385756793 48.91% 48.91% # Class of committed instruction 661system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 662system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 663system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 664system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 665system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 666system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 667system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 668system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 689system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 690system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 691system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 692system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 693system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction 694system.cpu.commit.bw_lim_events 22360483 # number cycles where commit BW limit reached
695system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
696system.cpu.rob.rob_reads 1891410858 # The number of ROB reads 697system.cpu.rob.rob_writes 2343104087 # The number of ROB writes 698system.cpu.timesIdled 647398 # Number of times that the entire CPU went into an idle state and unscheduled itself 699system.cpu.idleCycles 338168 # Total number of cycles that the CPU has spent unscheduled due to idling 700system.cpu.committedInsts 640649298 # Number of Instructions Simulated 701system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated 702system.cpu.cpi 1.278077 # CPI: Cycles Per Instruction 703system.cpu.cpi_total 1.278077 # CPI: Total CPI of All Threads 704system.cpu.ipc 0.782426 # IPC: Instructions Per Cycle 705system.cpu.ipc_total 0.782426 # IPC: Total IPC of All Threads 706system.cpu.int_regfile_reads 995803851 # number of integer regfile reads 707system.cpu.int_regfile_writes 567906934 # number of integer regfile writes 708system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads 709system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes 710system.cpu.cc_regfile_reads 3794434058 # number of cc regfile reads 711system.cpu.cc_regfile_writes 384899317 # number of cc regfile writes 712system.cpu.misc_regfile_reads 715816288 # number of misc regfile reads 713system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes 714system.cpu.dcache.tags.replacements 2756182 # number of replacements 715system.cpu.dcache.tags.tagsinuse 511.932940 # Cycle average of tags in use 716system.cpu.dcache.tags.total_refs 414226912 # Total number of references to valid blocks. 717system.cpu.dcache.tags.sampled_refs 2756694 # Sample count of references to valid blocks. 718system.cpu.dcache.tags.avg_refs 150.262202 # Average number of references to valid blocks. 719system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. 720system.cpu.dcache.tags.occ_blocks::cpu.data 511.932940 # Average occupied blocks per requestor 721system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy 722system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy 723system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 724system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 725system.cpu.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id 726system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id 727system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 728system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 729system.cpu.dcache.tags.tag_accesses 839344268 # Number of tag accesses 730system.cpu.dcache.tags.data_accesses 839344268 # Number of data accesses 731system.cpu.dcache.ReadReq_hits::cpu.data 286295518 # number of ReadReq hits 732system.cpu.dcache.ReadReq_hits::total 286295518 # number of ReadReq hits 733system.cpu.dcache.WriteReq_hits::cpu.data 127916671 # number of WriteReq hits 734system.cpu.dcache.WriteReq_hits::total 127916671 # number of WriteReq hits 735system.cpu.dcache.SoftPFReq_hits::cpu.data 3177 # number of SoftPFReq hits 736system.cpu.dcache.SoftPFReq_hits::total 3177 # number of SoftPFReq hits 737system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits 738system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits 739system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 740system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 741system.cpu.dcache.demand_hits::cpu.data 414212189 # number of demand (read+write) hits 742system.cpu.dcache.demand_hits::total 414212189 # number of demand (read+write) hits 743system.cpu.dcache.overall_hits::cpu.data 414215366 # number of overall hits 744system.cpu.dcache.overall_hits::total 414215366 # number of overall hits 745system.cpu.dcache.ReadReq_misses::cpu.data 3031489 # number of ReadReq misses 746system.cpu.dcache.ReadReq_misses::total 3031489 # number of ReadReq misses 747system.cpu.dcache.WriteReq_misses::cpu.data 1034806 # number of WriteReq misses 748system.cpu.dcache.WriteReq_misses::total 1034806 # number of WriteReq misses 749system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses 750system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses 751system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 752system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 753system.cpu.dcache.demand_misses::cpu.data 4066295 # number of demand (read+write) misses 754system.cpu.dcache.demand_misses::total 4066295 # number of demand (read+write) misses 755system.cpu.dcache.overall_misses::cpu.data 4066942 # number of overall misses 756system.cpu.dcache.overall_misses::total 4066942 # number of overall misses 757system.cpu.dcache.ReadReq_miss_latency::cpu.data 35316006617 # number of ReadReq miss cycles 758system.cpu.dcache.ReadReq_miss_latency::total 35316006617 # number of ReadReq miss cycles 759system.cpu.dcache.WriteReq_miss_latency::cpu.data 10004118304 # number of WriteReq miss cycles 760system.cpu.dcache.WriteReq_miss_latency::total 10004118304 # number of WriteReq miss cycles 761system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 202750 # number of LoadLockedReq miss cycles 762system.cpu.dcache.LoadLockedReq_miss_latency::total 202750 # number of LoadLockedReq miss cycles 763system.cpu.dcache.demand_miss_latency::cpu.data 45320124921 # number of demand (read+write) miss cycles 764system.cpu.dcache.demand_miss_latency::total 45320124921 # number of demand (read+write) miss cycles 765system.cpu.dcache.overall_miss_latency::cpu.data 45320124921 # number of overall miss cycles 766system.cpu.dcache.overall_miss_latency::total 45320124921 # number of overall miss cycles 767system.cpu.dcache.ReadReq_accesses::cpu.data 289327007 # number of ReadReq accesses(hits+misses) 768system.cpu.dcache.ReadReq_accesses::total 289327007 # number of ReadReq accesses(hits+misses) 769system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 770system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 771system.cpu.dcache.SoftPFReq_accesses::cpu.data 3824 # number of SoftPFReq accesses(hits+misses) 772system.cpu.dcache.SoftPFReq_accesses::total 3824 # number of SoftPFReq accesses(hits+misses) 773system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) 774system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) 775system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 776system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 777system.cpu.dcache.demand_accesses::cpu.data 418278484 # number of demand (read+write) accesses 778system.cpu.dcache.demand_accesses::total 418278484 # number of demand (read+write) accesses 779system.cpu.dcache.overall_accesses::cpu.data 418282308 # number of overall (read+write) accesses 780system.cpu.dcache.overall_accesses::total 418282308 # number of overall (read+write) accesses 781system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses 782system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses 783system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses 784system.cpu.dcache.WriteReq_miss_rate::total 0.008025 # miss rate for WriteReq accesses 785system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169195 # miss rate for SoftPFReq accesses 786system.cpu.dcache.SoftPFReq_miss_rate::total 0.169195 # miss rate for SoftPFReq accesses 787system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses 788system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses 789system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 # miss rate for demand accesses 790system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses 791system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses 792system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses 793system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11649.722832 # average ReadReq miss latency 794system.cpu.dcache.ReadReq_avg_miss_latency::total 11649.722832 # average ReadReq miss latency 795system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9667.626883 # average WriteReq miss latency 796system.cpu.dcache.WriteReq_avg_miss_latency::total 9667.626883 # average WriteReq miss latency 797system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67583.333333 # average LoadLockedReq miss latency 798system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67583.333333 # average LoadLockedReq miss latency 799system.cpu.dcache.demand_avg_miss_latency::cpu.data 11145.311622 # average overall miss latency 800system.cpu.dcache.demand_avg_miss_latency::total 11145.311622 # average overall miss latency 801system.cpu.dcache.overall_avg_miss_latency::cpu.data 11143.538541 # average overall miss latency 802system.cpu.dcache.overall_avg_miss_latency::total 11143.538541 # average overall miss latency 803system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 804system.cpu.dcache.blocked_cycles::no_targets 349732 # number of cycles access was blocked 805system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 806system.cpu.dcache.blocked::no_targets 5194 # number of cycles access was blocked 807system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 808system.cpu.dcache.avg_blocked_cycles::no_targets 67.333847 # average number of cycles each access was blocked 809system.cpu.dcache.fast_writes 0 # number of fast writes performed 810system.cpu.dcache.cache_copies 0 # number of cache copies performed 811system.cpu.dcache.writebacks::writebacks 735277 # number of writebacks 812system.cpu.dcache.writebacks::total 735277 # number of writebacks 813system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996280 # number of ReadReq MSHR hits 814system.cpu.dcache.ReadReq_mshr_hits::total 996280 # number of ReadReq MSHR hits 815system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313945 # number of WriteReq MSHR hits 816system.cpu.dcache.WriteReq_mshr_hits::total 313945 # number of WriteReq MSHR hits 817system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 818system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 819system.cpu.dcache.demand_mshr_hits::cpu.data 1310225 # number of demand (read+write) MSHR hits 820system.cpu.dcache.demand_mshr_hits::total 1310225 # number of demand (read+write) MSHR hits 821system.cpu.dcache.overall_mshr_hits::cpu.data 1310225 # number of overall MSHR hits 822system.cpu.dcache.overall_mshr_hits::total 1310225 # number of overall MSHR hits 823system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses 824system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses 825system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720861 # number of WriteReq MSHR misses 826system.cpu.dcache.WriteReq_mshr_misses::total 720861 # number of WriteReq MSHR misses 827system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses 828system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses 829system.cpu.dcache.demand_mshr_misses::cpu.data 2756070 # number of demand (read+write) MSHR misses 830system.cpu.dcache.demand_mshr_misses::total 2756070 # number of demand (read+write) MSHR misses 831system.cpu.dcache.overall_mshr_misses::cpu.data 2756711 # number of overall MSHR misses 832system.cpu.dcache.overall_mshr_misses::total 2756711 # number of overall MSHR misses 833system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23121613833 # number of ReadReq MSHR miss cycles 834system.cpu.dcache.ReadReq_mshr_miss_latency::total 23121613833 # number of ReadReq MSHR miss cycles 835system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5599042571 # number of WriteReq MSHR miss cycles 836system.cpu.dcache.WriteReq_mshr_miss_latency::total 5599042571 # number of WriteReq MSHR miss cycles 837system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5366500 # number of SoftPFReq MSHR miss cycles 838system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5366500 # number of SoftPFReq MSHR miss cycles 839system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28720656404 # number of demand (read+write) MSHR miss cycles 840system.cpu.dcache.demand_mshr_miss_latency::total 28720656404 # number of demand (read+write) MSHR miss cycles 841system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28726022904 # number of overall MSHR miss cycles 842system.cpu.dcache.overall_mshr_miss_latency::total 28726022904 # number of overall MSHR miss cycles 843system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses 844system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses 845system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses 846system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses 847system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167626 # mshr miss rate for SoftPFReq accesses 848system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167626 # mshr miss rate for SoftPFReq accesses 849system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses 850system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses 851system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses 852system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses 853system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11360.805614 # average ReadReq mshr miss latency 854system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11360.805614 # average ReadReq mshr miss latency 855system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7767.159787 # average WriteReq mshr miss latency 856system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7767.159787 # average WriteReq mshr miss latency 857system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8372.074883 # average SoftPFReq mshr miss latency 858system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8372.074883 # average SoftPFReq mshr miss latency 859system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10420.873346 # average overall mshr miss latency 860system.cpu.dcache.demand_avg_mshr_miss_latency::total 10420.873346 # average overall mshr miss latency 861system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10420.396953 # average overall mshr miss latency 862system.cpu.dcache.overall_avg_mshr_miss_latency::total 10420.396953 # average overall mshr miss latency 863system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 864system.cpu.icache.tags.replacements 5169874 # number of replacements 865system.cpu.icache.tags.tagsinuse 510.641329 # Cycle average of tags in use 866system.cpu.icache.tags.total_refs 365482216 # Total number of references to valid blocks. 867system.cpu.icache.tags.sampled_refs 5170384 # Sample count of references to valid blocks. 868system.cpu.icache.tags.avg_refs 70.687635 # Average number of references to valid blocks. 869system.cpu.icache.tags.warmup_cycle 247770250 # Cycle when the warmup percentage was hit. 870system.cpu.icache.tags.occ_blocks::cpu.inst 510.641329 # Average occupied blocks per requestor 871system.cpu.icache.tags.occ_percent::cpu.inst 0.997346 # Average percentage of cache occupancy 872system.cpu.icache.tags.occ_percent::total 0.997346 # Average percentage of cache occupancy 873system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 874system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 875system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 876system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 877system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id 878system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 879system.cpu.icache.tags.tag_accesses 746482947 # Number of tag accesses 880system.cpu.icache.tags.data_accesses 746482947 # Number of data accesses 881system.cpu.icache.ReadReq_hits::cpu.inst 365482251 # number of ReadReq hits 882system.cpu.icache.ReadReq_hits::total 365482251 # number of ReadReq hits 883system.cpu.icache.demand_hits::cpu.inst 365482251 # number of demand (read+write) hits 884system.cpu.icache.demand_hits::total 365482251 # number of demand (read+write) hits 885system.cpu.icache.overall_hits::cpu.inst 365482251 # number of overall hits 886system.cpu.icache.overall_hits::total 365482251 # number of overall hits 887system.cpu.icache.ReadReq_misses::cpu.inst 5174022 # number of ReadReq misses 888system.cpu.icache.ReadReq_misses::total 5174022 # number of ReadReq misses 889system.cpu.icache.demand_misses::cpu.inst 5174022 # number of demand (read+write) misses 890system.cpu.icache.demand_misses::total 5174022 # number of demand (read+write) misses 891system.cpu.icache.overall_misses::cpu.inst 5174022 # number of overall misses 892system.cpu.icache.overall_misses::total 5174022 # number of overall misses 893system.cpu.icache.ReadReq_miss_latency::cpu.inst 41654200685 # number of ReadReq miss cycles 894system.cpu.icache.ReadReq_miss_latency::total 41654200685 # number of ReadReq miss cycles 895system.cpu.icache.demand_miss_latency::cpu.inst 41654200685 # number of demand (read+write) miss cycles 896system.cpu.icache.demand_miss_latency::total 41654200685 # number of demand (read+write) miss cycles 897system.cpu.icache.overall_miss_latency::cpu.inst 41654200685 # number of overall miss cycles 898system.cpu.icache.overall_miss_latency::total 41654200685 # number of overall miss cycles 899system.cpu.icache.ReadReq_accesses::cpu.inst 370656273 # number of ReadReq accesses(hits+misses) 900system.cpu.icache.ReadReq_accesses::total 370656273 # number of ReadReq accesses(hits+misses) 901system.cpu.icache.demand_accesses::cpu.inst 370656273 # number of demand (read+write) accesses 902system.cpu.icache.demand_accesses::total 370656273 # number of demand (read+write) accesses 903system.cpu.icache.overall_accesses::cpu.inst 370656273 # number of overall (read+write) accesses 904system.cpu.icache.overall_accesses::total 370656273 # number of overall (read+write) accesses 905system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013959 # miss rate for ReadReq accesses 906system.cpu.icache.ReadReq_miss_rate::total 0.013959 # miss rate for ReadReq accesses 907system.cpu.icache.demand_miss_rate::cpu.inst 0.013959 # miss rate for demand accesses 908system.cpu.icache.demand_miss_rate::total 0.013959 # miss rate for demand accesses 909system.cpu.icache.overall_miss_rate::cpu.inst 0.013959 # miss rate for overall accesses 910system.cpu.icache.overall_miss_rate::total 0.013959 # miss rate for overall accesses 911system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8050.642360 # average ReadReq miss latency 912system.cpu.icache.ReadReq_avg_miss_latency::total 8050.642360 # average ReadReq miss latency 913system.cpu.icache.demand_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency 914system.cpu.icache.demand_avg_miss_latency::total 8050.642360 # average overall miss latency 915system.cpu.icache.overall_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency 916system.cpu.icache.overall_avg_miss_latency::total 8050.642360 # average overall miss latency 917system.cpu.icache.blocked_cycles::no_mshrs 76485 # number of cycles access was blocked 918system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked 919system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked 920system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 921system.cpu.icache.avg_blocked_cycles::no_mshrs 24.358280 # average number of cycles each access was blocked 922system.cpu.icache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked 923system.cpu.icache.fast_writes 0 # number of fast writes performed 924system.cpu.icache.cache_copies 0 # number of cache copies performed 925system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3620 # number of ReadReq MSHR hits 926system.cpu.icache.ReadReq_mshr_hits::total 3620 # number of ReadReq MSHR hits 927system.cpu.icache.demand_mshr_hits::cpu.inst 3620 # number of demand (read+write) MSHR hits 928system.cpu.icache.demand_mshr_hits::total 3620 # number of demand (read+write) MSHR hits 929system.cpu.icache.overall_mshr_hits::cpu.inst 3620 # number of overall MSHR hits 930system.cpu.icache.overall_mshr_hits::total 3620 # number of overall MSHR hits 931system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170402 # number of ReadReq MSHR misses 932system.cpu.icache.ReadReq_mshr_misses::total 5170402 # number of ReadReq MSHR misses 933system.cpu.icache.demand_mshr_misses::cpu.inst 5170402 # number of demand (read+write) MSHR misses 934system.cpu.icache.demand_mshr_misses::total 5170402 # number of demand (read+write) MSHR misses 935system.cpu.icache.overall_mshr_misses::cpu.inst 5170402 # number of overall MSHR misses 936system.cpu.icache.overall_mshr_misses::total 5170402 # number of overall MSHR misses 937system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36439121179 # number of ReadReq MSHR miss cycles 938system.cpu.icache.ReadReq_mshr_miss_latency::total 36439121179 # number of ReadReq MSHR miss cycles 939system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36439121179 # number of demand (read+write) MSHR miss cycles 940system.cpu.icache.demand_mshr_miss_latency::total 36439121179 # number of demand (read+write) MSHR miss cycles 941system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36439121179 # number of overall MSHR miss cycles 942system.cpu.icache.overall_mshr_miss_latency::total 36439121179 # number of overall MSHR miss cycles 943system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for ReadReq accesses 944system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013949 # mshr miss rate for ReadReq accesses 945system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for demand accesses 946system.cpu.icache.demand_mshr_miss_rate::total 0.013949 # mshr miss rate for demand accesses 947system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for overall accesses 948system.cpu.icache.overall_mshr_miss_rate::total 0.013949 # mshr miss rate for overall accesses 949system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7047.637917 # average ReadReq mshr miss latency 950system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7047.637917 # average ReadReq mshr miss latency 951system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7047.637917 # average overall mshr miss latency 952system.cpu.icache.demand_avg_mshr_miss_latency::total 7047.637917 # average overall mshr miss latency 953system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7047.637917 # average overall mshr miss latency 954system.cpu.icache.overall_avg_mshr_miss_latency::total 7047.637917 # average overall mshr miss latency 955system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 956system.cpu.l2cache.prefetcher.num_hwpf_issued 1347058 # number of hwpf issued 957system.cpu.l2cache.prefetcher.pfIdentified 1355234 # number of prefetch candidates identified 958system.cpu.l2cache.prefetcher.pfBufferHit 7153 # number of redundant prefetches already in prefetch queue 959system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 960system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 961system.cpu.l2cache.prefetcher.pfSpanPage 4790478 # number of prefetches not generated due to page crossing 962system.cpu.l2cache.tags.replacements 299258 # number of replacements 963system.cpu.l2cache.tags.tagsinuse 16361.552831 # Cycle average of tags in use 964system.cpu.l2cache.tags.total_refs 7824313 # Total number of references to valid blocks. 965system.cpu.l2cache.tags.sampled_refs 315622 # Sample count of references to valid blocks. 966system.cpu.l2cache.tags.avg_refs 24.790138 # Average number of references to valid blocks. 967system.cpu.l2cache.tags.warmup_cycle 13409363000 # Cycle when the warmup percentage was hit. 968system.cpu.l2cache.tags.occ_blocks::writebacks 738.976811 # Average occupied blocks per requestor 969system.cpu.l2cache.tags.occ_blocks::cpu.inst 129.067019 # Average occupied blocks per requestor 970system.cpu.l2cache.tags.occ_blocks::cpu.data 8785.583028 # Average occupied blocks per requestor 971system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6707.925973 # Average occupied blocks per requestor 972system.cpu.l2cache.tags.occ_percent::writebacks 0.045104 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007878 # Average percentage of cache occupancy 974system.cpu.l2cache.tags.occ_percent::cpu.data 0.536229 # Average percentage of cache occupancy 975system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.409419 # Average percentage of cache occupancy 976system.cpu.l2cache.tags.occ_percent::total 0.998630 # Average percentage of cache occupancy 977system.cpu.l2cache.tags.occ_task_id_blocks::1022 6482 # Occupied blocks per task id 978system.cpu.l2cache.tags.occ_task_id_blocks::1024 9882 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1022::2 155 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1470 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4840 # Occupied blocks per task id 983system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 984system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id 986system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2079 # Occupied blocks per task id 987system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7315 # Occupied blocks per task id 988system.cpu.l2cache.tags.occ_task_id_percent::1022 0.395630 # Percentage of cache occupancy per task id 989system.cpu.l2cache.tags.occ_task_id_percent::1024 0.603149 # Percentage of cache occupancy per task id 990system.cpu.l2cache.tags.tag_accesses 139634451 # Number of tag accesses 991system.cpu.l2cache.tags.data_accesses 139634451 # Number of data accesses 992system.cpu.l2cache.ReadReq_hits::cpu.inst 5166743 # number of ReadReq hits 993system.cpu.l2cache.ReadReq_hits::cpu.data 1926167 # number of ReadReq hits 994system.cpu.l2cache.ReadReq_hits::total 7092910 # number of ReadReq hits 995system.cpu.l2cache.Writeback_hits::writebacks 735277 # number of Writeback hits 996system.cpu.l2cache.Writeback_hits::total 735277 # number of Writeback hits 997system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 998system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 999system.cpu.l2cache.ReadExReq_hits::cpu.data 718012 # number of ReadExReq hits 1000system.cpu.l2cache.ReadExReq_hits::total 718012 # number of ReadExReq hits 1001system.cpu.l2cache.demand_hits::cpu.inst 5166743 # number of demand (read+write) hits 1002system.cpu.l2cache.demand_hits::cpu.data 2644179 # number of demand (read+write) hits 1003system.cpu.l2cache.demand_hits::total 7810922 # number of demand (read+write) hits 1004system.cpu.l2cache.overall_hits::cpu.inst 5166743 # number of overall hits 1005system.cpu.l2cache.overall_hits::cpu.data 2644179 # number of overall hits 1006system.cpu.l2cache.overall_hits::total 7810922 # number of overall hits 1007system.cpu.l2cache.ReadReq_misses::cpu.inst 3643 # number of ReadReq misses 1008system.cpu.l2cache.ReadReq_misses::cpu.data 109683 # number of ReadReq misses 1009system.cpu.l2cache.ReadReq_misses::total 113326 # number of ReadReq misses 1010system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses 1011system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses 1012system.cpu.l2cache.ReadExReq_misses::cpu.data 2832 # number of ReadExReq misses 1013system.cpu.l2cache.ReadExReq_misses::total 2832 # number of ReadExReq misses 1014system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses 1015system.cpu.l2cache.demand_misses::cpu.data 112515 # number of demand (read+write) misses 1016system.cpu.l2cache.demand_misses::total 116158 # number of demand (read+write) misses 1017system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses 1018system.cpu.l2cache.overall_misses::cpu.data 112515 # number of overall misses 1019system.cpu.l2cache.overall_misses::total 116158 # number of overall misses 1020system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 270029959 # number of ReadReq miss cycles 1021system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8565404562 # number of ReadReq miss cycles 1022system.cpu.l2cache.ReadReq_miss_latency::total 8835434521 # number of ReadReq miss cycles 1023system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 207607487 # number of ReadExReq miss cycles 1024system.cpu.l2cache.ReadExReq_miss_latency::total 207607487 # number of ReadExReq miss cycles 1025system.cpu.l2cache.demand_miss_latency::cpu.inst 270029959 # number of demand (read+write) miss cycles 1026system.cpu.l2cache.demand_miss_latency::cpu.data 8773012049 # number of demand (read+write) miss cycles 1027system.cpu.l2cache.demand_miss_latency::total 9043042008 # number of demand (read+write) miss cycles 1028system.cpu.l2cache.overall_miss_latency::cpu.inst 270029959 # number of overall miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.data 8773012049 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::total 9043042008 # number of overall miss cycles 1031system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170386 # number of ReadReq accesses(hits+misses) 1032system.cpu.l2cache.ReadReq_accesses::cpu.data 2035850 # number of ReadReq accesses(hits+misses) 1033system.cpu.l2cache.ReadReq_accesses::total 7206236 # number of ReadReq accesses(hits+misses) 1034system.cpu.l2cache.Writeback_accesses::writebacks 735277 # number of Writeback accesses(hits+misses) 1035system.cpu.l2cache.Writeback_accesses::total 735277 # number of Writeback accesses(hits+misses) 1036system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 1037system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 1038system.cpu.l2cache.ReadExReq_accesses::cpu.data 720844 # number of ReadExReq accesses(hits+misses) 1039system.cpu.l2cache.ReadExReq_accesses::total 720844 # number of ReadExReq accesses(hits+misses) 1040system.cpu.l2cache.demand_accesses::cpu.inst 5170386 # number of demand (read+write) accesses 1041system.cpu.l2cache.demand_accesses::cpu.data 2756694 # number of demand (read+write) accesses 1042system.cpu.l2cache.demand_accesses::total 7927080 # number of demand (read+write) accesses 1043system.cpu.l2cache.overall_accesses::cpu.inst 5170386 # number of overall (read+write) accesses 1044system.cpu.l2cache.overall_accesses::cpu.data 2756694 # number of overall (read+write) accesses 1045system.cpu.l2cache.overall_accesses::total 7927080 # number of overall (read+write) accesses 1046system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000705 # miss rate for ReadReq accesses 1047system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053876 # miss rate for ReadReq accesses 1048system.cpu.l2cache.ReadReq_miss_rate::total 0.015726 # miss rate for ReadReq accesses 1049system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.941176 # miss rate for UpgradeReq accesses 1050system.cpu.l2cache.UpgradeReq_miss_rate::total 0.941176 # miss rate for UpgradeReq accesses 1051system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003929 # miss rate for ReadExReq accesses 1052system.cpu.l2cache.ReadExReq_miss_rate::total 0.003929 # miss rate for ReadExReq accesses 1053system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000705 # miss rate for demand accesses 1054system.cpu.l2cache.demand_miss_rate::cpu.data 0.040815 # miss rate for demand accesses 1055system.cpu.l2cache.demand_miss_rate::total 0.014653 # miss rate for demand accesses 1056system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000705 # miss rate for overall accesses 1057system.cpu.l2cache.overall_miss_rate::cpu.data 0.040815 # miss rate for overall accesses 1058system.cpu.l2cache.overall_miss_rate::total 0.014653 # miss rate for overall accesses 1059system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74122.964315 # average ReadReq miss latency 1060system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.362189 # average ReadReq miss latency 1061system.cpu.l2cache.ReadReq_avg_miss_latency::total 77964.761140 # average ReadReq miss latency 1062system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73307.728460 # average ReadExReq miss latency 1063system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73307.728460 # average ReadExReq miss latency 1064system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency 1065system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency 1066system.cpu.l2cache.demand_avg_miss_latency::total 77851.219959 # average overall miss latency 1067system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency 1068system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency 1069system.cpu.l2cache.overall_avg_miss_latency::total 77851.219959 # average overall miss latency 1070system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1077system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1078system.cpu.l2cache.writebacks::writebacks 66326 # number of writebacks 1079system.cpu.l2cache.writebacks::total 66326 # number of writebacks 1080system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits 1081system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1303 # number of ReadReq MSHR hits 1082system.cpu.l2cache.ReadReq_mshr_hits::total 1318 # number of ReadReq MSHR hits 1083system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1445 # number of ReadExReq MSHR hits 1084system.cpu.l2cache.ReadExReq_mshr_hits::total 1445 # number of ReadExReq MSHR hits 1085system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits 1086system.cpu.l2cache.demand_mshr_hits::cpu.data 2748 # number of demand (read+write) MSHR hits 1087system.cpu.l2cache.demand_mshr_hits::total 2763 # number of demand (read+write) MSHR hits 1088system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits 1089system.cpu.l2cache.overall_mshr_hits::cpu.data 2748 # number of overall MSHR hits 1090system.cpu.l2cache.overall_mshr_hits::total 2763 # number of overall MSHR hits 1091system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3628 # number of ReadReq MSHR misses 1092system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108380 # number of ReadReq MSHR misses 1093system.cpu.l2cache.ReadReq_mshr_misses::total 112008 # number of ReadReq MSHR misses 1094system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202241 # number of HardPFReq MSHR misses 1095system.cpu.l2cache.HardPFReq_mshr_misses::total 202241 # number of HardPFReq MSHR misses 1096system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses 1097system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses 1098system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses 1099system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses 1100system.cpu.l2cache.demand_mshr_misses::cpu.inst 3628 # number of demand (read+write) MSHR misses 1101system.cpu.l2cache.demand_mshr_misses::cpu.data 109767 # number of demand (read+write) MSHR misses 1102system.cpu.l2cache.demand_mshr_misses::total 113395 # number of demand (read+write) MSHR misses 1103system.cpu.l2cache.overall_mshr_misses::cpu.inst 3628 # number of overall MSHR misses 1104system.cpu.l2cache.overall_mshr_misses::cpu.data 109767 # number of overall MSHR misses 1105system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202241 # number of overall MSHR misses 1106system.cpu.l2cache.overall_mshr_misses::total 315636 # number of overall MSHR misses 1107system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 238098541 # number of ReadReq MSHR miss cycles 1108system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7611970750 # number of ReadReq MSHR miss cycles 1109system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7850069291 # number of ReadReq MSHR miss cycles 1110system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of HardPFReq MSHR miss cycles 1111system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17087057356 # number of HardPFReq MSHR miss cycles 1112system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 219516 # number of UpgradeReq MSHR miss cycles 1113system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 219516 # number of UpgradeReq MSHR miss cycles 1114system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114561754 # number of ReadExReq MSHR miss cycles 1115system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114561754 # number of ReadExReq MSHR miss cycles 1116system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238098541 # number of demand (read+write) MSHR miss cycles 1117system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7726532504 # number of demand (read+write) MSHR miss cycles 1118system.cpu.l2cache.demand_mshr_miss_latency::total 7964631045 # number of demand (read+write) MSHR miss cycles 1119system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238098541 # number of overall MSHR miss cycles 1120system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7726532504 # number of overall MSHR miss cycles 1121system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of overall MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::total 25051688401 # number of overall MSHR miss cycles 1123system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for ReadReq accesses 1124system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053236 # mshr miss rate for ReadReq accesses 1125system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses 1126system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1127system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1128system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses 1129system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses 1130system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses 1131system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses 1132system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for demand accesses 1133system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for demand accesses 1134system.cpu.l2cache.demand_mshr_miss_rate::total 0.014305 # mshr miss rate for demand accesses 1135system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for overall accesses 1136system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for overall accesses 1137system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1138system.cpu.l2cache.overall_mshr_miss_rate::total 0.039817 # mshr miss rate for overall accesses 1139system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65628.043275 # average ReadReq mshr miss latency 1140system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70234.090699 # average ReadReq mshr miss latency 1141system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70084.898320 # average ReadReq mshr miss latency 1142system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average HardPFReq mshr miss latency 1143system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84488.592105 # average HardPFReq mshr miss latency 1144system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13719.750000 # average UpgradeReq mshr miss latency 1145system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13719.750000 # average UpgradeReq mshr miss latency 1146system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82596.794521 # average ReadExReq mshr miss latency 1147system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82596.794521 # average ReadExReq mshr miss latency 1148system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency 1149system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency 1150system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.938578 # average overall mshr miss latency 1151system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency 1152system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency 1153system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average overall mshr miss latency 1154system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79368.919898 # average overall mshr miss latency 1155system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1156system.cpu.toL2Bus.trans_dist::ReadReq 7206252 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::ReadResp 7206251 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::Writeback 735277 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::HardPFReq 248818 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::ReadExReq 720844 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::ReadExResp 720844 # Transaction distribution 1164system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340787 # Packet count per connected master and slave (bytes) 1165system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248699 # Packet count per connected master and slave (bytes) 1166system.cpu.toL2Bus.pkt_count::total 16589486 # Packet count per connected master and slave (bytes) 1167system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330904640 # Cumulative packet size per connected master and slave (bytes) 1168system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223486144 # Cumulative packet size per connected master and slave (bytes) 1169system.cpu.toL2Bus.pkt_size::total 554390784 # Cumulative packet size per connected master and slave (bytes) 1170system.cpu.toL2Bus.snoops 248834 # Total snoops (count) 1171system.cpu.toL2Bus.snoop_fanout::samples 8911208 # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::mean 3.027922 # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::stdev 0.164749 # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::3 8662390 97.21% 97.21% # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::4 248818 2.79% 100.00% # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::total 8911208 # Request fanout histogram 1184system.cpu.toL2Bus.reqLayer0.occupancy 5066472000 # Layer occupancy (ticks) 1185system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1186system.cpu.toL2Bus.respLayer0.occupancy 7756152507 # Layer occupancy (ticks) 1187system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 1188system.cpu.toL2Bus.respLayer1.occupancy 4138701196 # Layer occupancy (ticks) 1189system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 1190system.membus.trans_dist::ReadReq 314173 # Transaction distribution 1191system.membus.trans_dist::ReadResp 314173 # Transaction distribution 1192system.membus.trans_dist::Writeback 66326 # Transaction distribution 1193system.membus.trans_dist::UpgradeReq 16 # Transaction distribution 1194system.membus.trans_dist::UpgradeResp 16 # Transaction distribution 1195system.membus.trans_dist::ReadExReq 1387 # Transaction distribution 1196system.membus.trans_dist::ReadExResp 1387 # Transaction distribution 1197system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697478 # Packet count per connected master and slave (bytes) 1198system.membus.pkt_count::total 697478 # Packet count per connected master and slave (bytes) 1199system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24440704 # Cumulative packet size per connected master and slave (bytes) 1200system.membus.pkt_size::total 24440704 # Cumulative packet size per connected master and slave (bytes) 1201system.membus.snoops 0 # Total snoops (count) 1202system.membus.snoop_fanout::samples 381902 # Request fanout histogram 1203system.membus.snoop_fanout::mean 0 # Request fanout histogram 1204system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1205system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1206system.membus.snoop_fanout::0 381902 100.00% 100.00% # Request fanout histogram 1207system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1208system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1209system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1210system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1211system.membus.snoop_fanout::total 381902 # Request fanout histogram 1212system.membus.reqLayer0.occupancy 746879857 # Layer occupancy (ticks) 1213system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 1214system.membus.respLayer1.occupancy 1648874306 # Layer occupancy (ticks) 1215system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 1216 1217---------- End Simulation Statistics ----------	695system.cpu.rob.rob_reads 1891410858 # The number of ROB reads 696system.cpu.rob.rob_writes 2343104087 # The number of ROB writes 697system.cpu.timesIdled 647398 # Number of times that the entire CPU went into an idle state and unscheduled itself 698system.cpu.idleCycles 338168 # Total number of cycles that the CPU has spent unscheduled due to idling 699system.cpu.committedInsts 640649298 # Number of Instructions Simulated 700system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated 701system.cpu.cpi 1.278077 # CPI: Cycles Per Instruction 702system.cpu.cpi_total 1.278077 # CPI: Total CPI of All Threads 703system.cpu.ipc 0.782426 # IPC: Instructions Per Cycle 704system.cpu.ipc_total 0.782426 # IPC: Total IPC of All Threads 705system.cpu.int_regfile_reads 995803851 # number of integer regfile reads 706system.cpu.int_regfile_writes 567906934 # number of integer regfile writes 707system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads 708system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes 709system.cpu.cc_regfile_reads 3794434058 # number of cc regfile reads 710system.cpu.cc_regfile_writes 384899317 # number of cc regfile writes 711system.cpu.misc_regfile_reads 715816288 # number of misc regfile reads 712system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes 713system.cpu.dcache.tags.replacements 2756182 # number of replacements 714system.cpu.dcache.tags.tagsinuse 511.932940 # Cycle average of tags in use 715system.cpu.dcache.tags.total_refs 414226912 # Total number of references to valid blocks. 716system.cpu.dcache.tags.sampled_refs 2756694 # Sample count of references to valid blocks. 717system.cpu.dcache.tags.avg_refs 150.262202 # Average number of references to valid blocks. 718system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. 719system.cpu.dcache.tags.occ_blocks::cpu.data 511.932940 # Average occupied blocks per requestor 720system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy 721system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy 722system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 723system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 724system.cpu.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id 725system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id 726system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 727system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 728system.cpu.dcache.tags.tag_accesses 839344268 # Number of tag accesses 729system.cpu.dcache.tags.data_accesses 839344268 # Number of data accesses 730system.cpu.dcache.ReadReq_hits::cpu.data 286295518 # number of ReadReq hits 731system.cpu.dcache.ReadReq_hits::total 286295518 # number of ReadReq hits 732system.cpu.dcache.WriteReq_hits::cpu.data 127916671 # number of WriteReq hits 733system.cpu.dcache.WriteReq_hits::total 127916671 # number of WriteReq hits 734system.cpu.dcache.SoftPFReq_hits::cpu.data 3177 # number of SoftPFReq hits 735system.cpu.dcache.SoftPFReq_hits::total 3177 # number of SoftPFReq hits 736system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits 737system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits 738system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 739system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 740system.cpu.dcache.demand_hits::cpu.data 414212189 # number of demand (read+write) hits 741system.cpu.dcache.demand_hits::total 414212189 # number of demand (read+write) hits 742system.cpu.dcache.overall_hits::cpu.data 414215366 # number of overall hits 743system.cpu.dcache.overall_hits::total 414215366 # number of overall hits 744system.cpu.dcache.ReadReq_misses::cpu.data 3031489 # number of ReadReq misses 745system.cpu.dcache.ReadReq_misses::total 3031489 # number of ReadReq misses 746system.cpu.dcache.WriteReq_misses::cpu.data 1034806 # number of WriteReq misses 747system.cpu.dcache.WriteReq_misses::total 1034806 # number of WriteReq misses 748system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses 749system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses 750system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 751system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 752system.cpu.dcache.demand_misses::cpu.data 4066295 # number of demand (read+write) misses 753system.cpu.dcache.demand_misses::total 4066295 # number of demand (read+write) misses 754system.cpu.dcache.overall_misses::cpu.data 4066942 # number of overall misses 755system.cpu.dcache.overall_misses::total 4066942 # number of overall misses 756system.cpu.dcache.ReadReq_miss_latency::cpu.data 35316006617 # number of ReadReq miss cycles 757system.cpu.dcache.ReadReq_miss_latency::total 35316006617 # number of ReadReq miss cycles 758system.cpu.dcache.WriteReq_miss_latency::cpu.data 10004118304 # number of WriteReq miss cycles 759system.cpu.dcache.WriteReq_miss_latency::total 10004118304 # number of WriteReq miss cycles 760system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 202750 # number of LoadLockedReq miss cycles 761system.cpu.dcache.LoadLockedReq_miss_latency::total 202750 # number of LoadLockedReq miss cycles 762system.cpu.dcache.demand_miss_latency::cpu.data 45320124921 # number of demand (read+write) miss cycles 763system.cpu.dcache.demand_miss_latency::total 45320124921 # number of demand (read+write) miss cycles 764system.cpu.dcache.overall_miss_latency::cpu.data 45320124921 # number of overall miss cycles 765system.cpu.dcache.overall_miss_latency::total 45320124921 # number of overall miss cycles 766system.cpu.dcache.ReadReq_accesses::cpu.data 289327007 # number of ReadReq accesses(hits+misses) 767system.cpu.dcache.ReadReq_accesses::total 289327007 # number of ReadReq accesses(hits+misses) 768system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 769system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 770system.cpu.dcache.SoftPFReq_accesses::cpu.data 3824 # number of SoftPFReq accesses(hits+misses) 771system.cpu.dcache.SoftPFReq_accesses::total 3824 # number of SoftPFReq accesses(hits+misses) 772system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) 773system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) 774system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 775system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 776system.cpu.dcache.demand_accesses::cpu.data 418278484 # number of demand (read+write) accesses 777system.cpu.dcache.demand_accesses::total 418278484 # number of demand (read+write) accesses 778system.cpu.dcache.overall_accesses::cpu.data 418282308 # number of overall (read+write) accesses 779system.cpu.dcache.overall_accesses::total 418282308 # number of overall (read+write) accesses 780system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses 781system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses 782system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses 783system.cpu.dcache.WriteReq_miss_rate::total 0.008025 # miss rate for WriteReq accesses 784system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169195 # miss rate for SoftPFReq accesses 785system.cpu.dcache.SoftPFReq_miss_rate::total 0.169195 # miss rate for SoftPFReq accesses 786system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses 787system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses 788system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 # miss rate for demand accesses 789system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses 790system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses 791system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses 792system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11649.722832 # average ReadReq miss latency 793system.cpu.dcache.ReadReq_avg_miss_latency::total 11649.722832 # average ReadReq miss latency 794system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9667.626883 # average WriteReq miss latency 795system.cpu.dcache.WriteReq_avg_miss_latency::total 9667.626883 # average WriteReq miss latency 796system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67583.333333 # average LoadLockedReq miss latency 797system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67583.333333 # average LoadLockedReq miss latency 798system.cpu.dcache.demand_avg_miss_latency::cpu.data 11145.311622 # average overall miss latency 799system.cpu.dcache.demand_avg_miss_latency::total 11145.311622 # average overall miss latency 800system.cpu.dcache.overall_avg_miss_latency::cpu.data 11143.538541 # average overall miss latency 801system.cpu.dcache.overall_avg_miss_latency::total 11143.538541 # average overall miss latency 802system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 803system.cpu.dcache.blocked_cycles::no_targets 349732 # number of cycles access was blocked 804system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 805system.cpu.dcache.blocked::no_targets 5194 # number of cycles access was blocked 806system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 807system.cpu.dcache.avg_blocked_cycles::no_targets 67.333847 # average number of cycles each access was blocked 808system.cpu.dcache.fast_writes 0 # number of fast writes performed 809system.cpu.dcache.cache_copies 0 # number of cache copies performed 810system.cpu.dcache.writebacks::writebacks 735277 # number of writebacks 811system.cpu.dcache.writebacks::total 735277 # number of writebacks 812system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996280 # number of ReadReq MSHR hits 813system.cpu.dcache.ReadReq_mshr_hits::total 996280 # number of ReadReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313945 # number of WriteReq MSHR hits 815system.cpu.dcache.WriteReq_mshr_hits::total 313945 # number of WriteReq MSHR hits 816system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 817system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 818system.cpu.dcache.demand_mshr_hits::cpu.data 1310225 # number of demand (read+write) MSHR hits 819system.cpu.dcache.demand_mshr_hits::total 1310225 # number of demand (read+write) MSHR hits 820system.cpu.dcache.overall_mshr_hits::cpu.data 1310225 # number of overall MSHR hits 821system.cpu.dcache.overall_mshr_hits::total 1310225 # number of overall MSHR hits 822system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses 823system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses 824system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720861 # number of WriteReq MSHR misses 825system.cpu.dcache.WriteReq_mshr_misses::total 720861 # number of WriteReq MSHR misses 826system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses 827system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses 828system.cpu.dcache.demand_mshr_misses::cpu.data 2756070 # number of demand (read+write) MSHR misses 829system.cpu.dcache.demand_mshr_misses::total 2756070 # number of demand (read+write) MSHR misses 830system.cpu.dcache.overall_mshr_misses::cpu.data 2756711 # number of overall MSHR misses 831system.cpu.dcache.overall_mshr_misses::total 2756711 # number of overall MSHR misses 832system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23121613833 # number of ReadReq MSHR miss cycles 833system.cpu.dcache.ReadReq_mshr_miss_latency::total 23121613833 # number of ReadReq MSHR miss cycles 834system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5599042571 # number of WriteReq MSHR miss cycles 835system.cpu.dcache.WriteReq_mshr_miss_latency::total 5599042571 # number of WriteReq MSHR miss cycles 836system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5366500 # number of SoftPFReq MSHR miss cycles 837system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5366500 # number of SoftPFReq MSHR miss cycles 838system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28720656404 # number of demand (read+write) MSHR miss cycles 839system.cpu.dcache.demand_mshr_miss_latency::total 28720656404 # number of demand (read+write) MSHR miss cycles 840system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28726022904 # number of overall MSHR miss cycles 841system.cpu.dcache.overall_mshr_miss_latency::total 28726022904 # number of overall MSHR miss cycles 842system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses 843system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses 844system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses 845system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses 846system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167626 # mshr miss rate for SoftPFReq accesses 847system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167626 # mshr miss rate for SoftPFReq accesses 848system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses 849system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses 850system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses 851system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses 852system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11360.805614 # average ReadReq mshr miss latency 853system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11360.805614 # average ReadReq mshr miss latency 854system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7767.159787 # average WriteReq mshr miss latency 855system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7767.159787 # average WriteReq mshr miss latency 856system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8372.074883 # average SoftPFReq mshr miss latency 857system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8372.074883 # average SoftPFReq mshr miss latency 858system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10420.873346 # average overall mshr miss latency 859system.cpu.dcache.demand_avg_mshr_miss_latency::total 10420.873346 # average overall mshr miss latency 860system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10420.396953 # average overall mshr miss latency 861system.cpu.dcache.overall_avg_mshr_miss_latency::total 10420.396953 # average overall mshr miss latency 862system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 863system.cpu.icache.tags.replacements 5169874 # number of replacements 864system.cpu.icache.tags.tagsinuse 510.641329 # Cycle average of tags in use 865system.cpu.icache.tags.total_refs 365482216 # Total number of references to valid blocks. 866system.cpu.icache.tags.sampled_refs 5170384 # Sample count of references to valid blocks. 867system.cpu.icache.tags.avg_refs 70.687635 # Average number of references to valid blocks. 868system.cpu.icache.tags.warmup_cycle 247770250 # Cycle when the warmup percentage was hit. 869system.cpu.icache.tags.occ_blocks::cpu.inst 510.641329 # Average occupied blocks per requestor 870system.cpu.icache.tags.occ_percent::cpu.inst 0.997346 # Average percentage of cache occupancy 871system.cpu.icache.tags.occ_percent::total 0.997346 # Average percentage of cache occupancy 872system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 873system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 874system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 875system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 876system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id 877system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 878system.cpu.icache.tags.tag_accesses 746482947 # Number of tag accesses 879system.cpu.icache.tags.data_accesses 746482947 # Number of data accesses 880system.cpu.icache.ReadReq_hits::cpu.inst 365482251 # number of ReadReq hits 881system.cpu.icache.ReadReq_hits::total 365482251 # number of ReadReq hits 882system.cpu.icache.demand_hits::cpu.inst 365482251 # number of demand (read+write) hits 883system.cpu.icache.demand_hits::total 365482251 # number of demand (read+write) hits 884system.cpu.icache.overall_hits::cpu.inst 365482251 # number of overall hits 885system.cpu.icache.overall_hits::total 365482251 # number of overall hits 886system.cpu.icache.ReadReq_misses::cpu.inst 5174022 # number of ReadReq misses 887system.cpu.icache.ReadReq_misses::total 5174022 # number of ReadReq misses 888system.cpu.icache.demand_misses::cpu.inst 5174022 # number of demand (read+write) misses 889system.cpu.icache.demand_misses::total 5174022 # number of demand (read+write) misses 890system.cpu.icache.overall_misses::cpu.inst 5174022 # number of overall misses 891system.cpu.icache.overall_misses::total 5174022 # number of overall misses 892system.cpu.icache.ReadReq_miss_latency::cpu.inst 41654200685 # number of ReadReq miss cycles 893system.cpu.icache.ReadReq_miss_latency::total 41654200685 # number of ReadReq miss cycles 894system.cpu.icache.demand_miss_latency::cpu.inst 41654200685 # number of demand (read+write) miss cycles 895system.cpu.icache.demand_miss_latency::total 41654200685 # number of demand (read+write) miss cycles 896system.cpu.icache.overall_miss_latency::cpu.inst 41654200685 # number of overall miss cycles 897system.cpu.icache.overall_miss_latency::total 41654200685 # number of overall miss cycles 898system.cpu.icache.ReadReq_accesses::cpu.inst 370656273 # number of ReadReq accesses(hits+misses) 899system.cpu.icache.ReadReq_accesses::total 370656273 # number of ReadReq accesses(hits+misses) 900system.cpu.icache.demand_accesses::cpu.inst 370656273 # number of demand (read+write) accesses 901system.cpu.icache.demand_accesses::total 370656273 # number of demand (read+write) accesses 902system.cpu.icache.overall_accesses::cpu.inst 370656273 # number of overall (read+write) accesses 903system.cpu.icache.overall_accesses::total 370656273 # number of overall (read+write) accesses 904system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013959 # miss rate for ReadReq accesses 905system.cpu.icache.ReadReq_miss_rate::total 0.013959 # miss rate for ReadReq accesses 906system.cpu.icache.demand_miss_rate::cpu.inst 0.013959 # miss rate for demand accesses 907system.cpu.icache.demand_miss_rate::total 0.013959 # miss rate for demand accesses 908system.cpu.icache.overall_miss_rate::cpu.inst 0.013959 # miss rate for overall accesses 909system.cpu.icache.overall_miss_rate::total 0.013959 # miss rate for overall accesses 910system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8050.642360 # average ReadReq miss latency 911system.cpu.icache.ReadReq_avg_miss_latency::total 8050.642360 # average ReadReq miss latency 912system.cpu.icache.demand_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency 913system.cpu.icache.demand_avg_miss_latency::total 8050.642360 # average overall miss latency 914system.cpu.icache.overall_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency 915system.cpu.icache.overall_avg_miss_latency::total 8050.642360 # average overall miss latency 916system.cpu.icache.blocked_cycles::no_mshrs 76485 # number of cycles access was blocked 917system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked 918system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked 919system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 920system.cpu.icache.avg_blocked_cycles::no_mshrs 24.358280 # average number of cycles each access was blocked 921system.cpu.icache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked 922system.cpu.icache.fast_writes 0 # number of fast writes performed 923system.cpu.icache.cache_copies 0 # number of cache copies performed 924system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3620 # number of ReadReq MSHR hits 925system.cpu.icache.ReadReq_mshr_hits::total 3620 # number of ReadReq MSHR hits 926system.cpu.icache.demand_mshr_hits::cpu.inst 3620 # number of demand (read+write) MSHR hits 927system.cpu.icache.demand_mshr_hits::total 3620 # number of demand (read+write) MSHR hits 928system.cpu.icache.overall_mshr_hits::cpu.inst 3620 # number of overall MSHR hits 929system.cpu.icache.overall_mshr_hits::total 3620 # number of overall MSHR hits 930system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170402 # number of ReadReq MSHR misses 931system.cpu.icache.ReadReq_mshr_misses::total 5170402 # number of ReadReq MSHR misses 932system.cpu.icache.demand_mshr_misses::cpu.inst 5170402 # number of demand (read+write) MSHR misses 933system.cpu.icache.demand_mshr_misses::total 5170402 # number of demand (read+write) MSHR misses 934system.cpu.icache.overall_mshr_misses::cpu.inst 5170402 # number of overall MSHR misses 935system.cpu.icache.overall_mshr_misses::total 5170402 # number of overall MSHR misses 936system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36439121179 # number of ReadReq MSHR miss cycles 937system.cpu.icache.ReadReq_mshr_miss_latency::total 36439121179 # number of ReadReq MSHR miss cycles 938system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36439121179 # number of demand (read+write) MSHR miss cycles 939system.cpu.icache.demand_mshr_miss_latency::total 36439121179 # number of demand (read+write) MSHR miss cycles 940system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36439121179 # number of overall MSHR miss cycles 941system.cpu.icache.overall_mshr_miss_latency::total 36439121179 # number of overall MSHR miss cycles 942system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for ReadReq accesses 943system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013949 # mshr miss rate for ReadReq accesses 944system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for demand accesses 945system.cpu.icache.demand_mshr_miss_rate::total 0.013949 # mshr miss rate for demand accesses 946system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for overall accesses 947system.cpu.icache.overall_mshr_miss_rate::total 0.013949 # mshr miss rate for overall accesses 948system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7047.637917 # average ReadReq mshr miss latency 949system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7047.637917 # average ReadReq mshr miss latency 950system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7047.637917 # average overall mshr miss latency 951system.cpu.icache.demand_avg_mshr_miss_latency::total 7047.637917 # average overall mshr miss latency 952system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7047.637917 # average overall mshr miss latency 953system.cpu.icache.overall_avg_mshr_miss_latency::total 7047.637917 # average overall mshr miss latency 954system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 955system.cpu.l2cache.prefetcher.num_hwpf_issued 1347058 # number of hwpf issued 956system.cpu.l2cache.prefetcher.pfIdentified 1355234 # number of prefetch candidates identified 957system.cpu.l2cache.prefetcher.pfBufferHit 7153 # number of redundant prefetches already in prefetch queue 958system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 959system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 960system.cpu.l2cache.prefetcher.pfSpanPage 4790478 # number of prefetches not generated due to page crossing 961system.cpu.l2cache.tags.replacements 299258 # number of replacements 962system.cpu.l2cache.tags.tagsinuse 16361.552831 # Cycle average of tags in use 963system.cpu.l2cache.tags.total_refs 7824313 # Total number of references to valid blocks. 964system.cpu.l2cache.tags.sampled_refs 315622 # Sample count of references to valid blocks. 965system.cpu.l2cache.tags.avg_refs 24.790138 # Average number of references to valid blocks. 966system.cpu.l2cache.tags.warmup_cycle 13409363000 # Cycle when the warmup percentage was hit. 967system.cpu.l2cache.tags.occ_blocks::writebacks 738.976811 # Average occupied blocks per requestor 968system.cpu.l2cache.tags.occ_blocks::cpu.inst 129.067019 # Average occupied blocks per requestor 969system.cpu.l2cache.tags.occ_blocks::cpu.data 8785.583028 # Average occupied blocks per requestor 970system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6707.925973 # Average occupied blocks per requestor 971system.cpu.l2cache.tags.occ_percent::writebacks 0.045104 # Average percentage of cache occupancy 972system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007878 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_percent::cpu.data 0.536229 # Average percentage of cache occupancy 974system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.409419 # Average percentage of cache occupancy 975system.cpu.l2cache.tags.occ_percent::total 0.998630 # Average percentage of cache occupancy 976system.cpu.l2cache.tags.occ_task_id_blocks::1022 6482 # Occupied blocks per task id 977system.cpu.l2cache.tags.occ_task_id_blocks::1024 9882 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1022::2 155 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1470 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4840 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 983system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 984system.cpu.l2cache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2079 # Occupied blocks per task id 986system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7315 # Occupied blocks per task id 987system.cpu.l2cache.tags.occ_task_id_percent::1022 0.395630 # Percentage of cache occupancy per task id 988system.cpu.l2cache.tags.occ_task_id_percent::1024 0.603149 # Percentage of cache occupancy per task id 989system.cpu.l2cache.tags.tag_accesses 139634451 # Number of tag accesses 990system.cpu.l2cache.tags.data_accesses 139634451 # Number of data accesses 991system.cpu.l2cache.ReadReq_hits::cpu.inst 5166743 # number of ReadReq hits 992system.cpu.l2cache.ReadReq_hits::cpu.data 1926167 # number of ReadReq hits 993system.cpu.l2cache.ReadReq_hits::total 7092910 # number of ReadReq hits 994system.cpu.l2cache.Writeback_hits::writebacks 735277 # number of Writeback hits 995system.cpu.l2cache.Writeback_hits::total 735277 # number of Writeback hits 996system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 997system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 998system.cpu.l2cache.ReadExReq_hits::cpu.data 718012 # number of ReadExReq hits 999system.cpu.l2cache.ReadExReq_hits::total 718012 # number of ReadExReq hits 1000system.cpu.l2cache.demand_hits::cpu.inst 5166743 # number of demand (read+write) hits 1001system.cpu.l2cache.demand_hits::cpu.data 2644179 # number of demand (read+write) hits 1002system.cpu.l2cache.demand_hits::total 7810922 # number of demand (read+write) hits 1003system.cpu.l2cache.overall_hits::cpu.inst 5166743 # number of overall hits 1004system.cpu.l2cache.overall_hits::cpu.data 2644179 # number of overall hits 1005system.cpu.l2cache.overall_hits::total 7810922 # number of overall hits 1006system.cpu.l2cache.ReadReq_misses::cpu.inst 3643 # number of ReadReq misses 1007system.cpu.l2cache.ReadReq_misses::cpu.data 109683 # number of ReadReq misses 1008system.cpu.l2cache.ReadReq_misses::total 113326 # number of ReadReq misses 1009system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses 1010system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses 1011system.cpu.l2cache.ReadExReq_misses::cpu.data 2832 # number of ReadExReq misses 1012system.cpu.l2cache.ReadExReq_misses::total 2832 # number of ReadExReq misses 1013system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses 1014system.cpu.l2cache.demand_misses::cpu.data 112515 # number of demand (read+write) misses 1015system.cpu.l2cache.demand_misses::total 116158 # number of demand (read+write) misses 1016system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses 1017system.cpu.l2cache.overall_misses::cpu.data 112515 # number of overall misses 1018system.cpu.l2cache.overall_misses::total 116158 # number of overall misses 1019system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 270029959 # number of ReadReq miss cycles 1020system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8565404562 # number of ReadReq miss cycles 1021system.cpu.l2cache.ReadReq_miss_latency::total 8835434521 # number of ReadReq miss cycles 1022system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 207607487 # number of ReadExReq miss cycles 1023system.cpu.l2cache.ReadExReq_miss_latency::total 207607487 # number of ReadExReq miss cycles 1024system.cpu.l2cache.demand_miss_latency::cpu.inst 270029959 # number of demand (read+write) miss cycles 1025system.cpu.l2cache.demand_miss_latency::cpu.data 8773012049 # number of demand (read+write) miss cycles 1026system.cpu.l2cache.demand_miss_latency::total 9043042008 # number of demand (read+write) miss cycles 1027system.cpu.l2cache.overall_miss_latency::cpu.inst 270029959 # number of overall miss cycles 1028system.cpu.l2cache.overall_miss_latency::cpu.data 8773012049 # number of overall miss cycles 1029system.cpu.l2cache.overall_miss_latency::total 9043042008 # number of overall miss cycles 1030system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170386 # number of ReadReq accesses(hits+misses) 1031system.cpu.l2cache.ReadReq_accesses::cpu.data 2035850 # number of ReadReq accesses(hits+misses) 1032system.cpu.l2cache.ReadReq_accesses::total 7206236 # number of ReadReq accesses(hits+misses) 1033system.cpu.l2cache.Writeback_accesses::writebacks 735277 # number of Writeback accesses(hits+misses) 1034system.cpu.l2cache.Writeback_accesses::total 735277 # number of Writeback accesses(hits+misses) 1035system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 1036system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 1037system.cpu.l2cache.ReadExReq_accesses::cpu.data 720844 # number of ReadExReq accesses(hits+misses) 1038system.cpu.l2cache.ReadExReq_accesses::total 720844 # number of ReadExReq accesses(hits+misses) 1039system.cpu.l2cache.demand_accesses::cpu.inst 5170386 # number of demand (read+write) accesses 1040system.cpu.l2cache.demand_accesses::cpu.data 2756694 # number of demand (read+write) accesses 1041system.cpu.l2cache.demand_accesses::total 7927080 # number of demand (read+write) accesses 1042system.cpu.l2cache.overall_accesses::cpu.inst 5170386 # number of overall (read+write) accesses 1043system.cpu.l2cache.overall_accesses::cpu.data 2756694 # number of overall (read+write) accesses 1044system.cpu.l2cache.overall_accesses::total 7927080 # number of overall (read+write) accesses 1045system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000705 # miss rate for ReadReq accesses 1046system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053876 # miss rate for ReadReq accesses 1047system.cpu.l2cache.ReadReq_miss_rate::total 0.015726 # miss rate for ReadReq accesses 1048system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.941176 # miss rate for UpgradeReq accesses 1049system.cpu.l2cache.UpgradeReq_miss_rate::total 0.941176 # miss rate for UpgradeReq accesses 1050system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003929 # miss rate for ReadExReq accesses 1051system.cpu.l2cache.ReadExReq_miss_rate::total 0.003929 # miss rate for ReadExReq accesses 1052system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000705 # miss rate for demand accesses 1053system.cpu.l2cache.demand_miss_rate::cpu.data 0.040815 # miss rate for demand accesses 1054system.cpu.l2cache.demand_miss_rate::total 0.014653 # miss rate for demand accesses 1055system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000705 # miss rate for overall accesses 1056system.cpu.l2cache.overall_miss_rate::cpu.data 0.040815 # miss rate for overall accesses 1057system.cpu.l2cache.overall_miss_rate::total 0.014653 # miss rate for overall accesses 1058system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74122.964315 # average ReadReq miss latency 1059system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.362189 # average ReadReq miss latency 1060system.cpu.l2cache.ReadReq_avg_miss_latency::total 77964.761140 # average ReadReq miss latency 1061system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73307.728460 # average ReadExReq miss latency 1062system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73307.728460 # average ReadExReq miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency 1064system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency 1065system.cpu.l2cache.demand_avg_miss_latency::total 77851.219959 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency 1067system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency 1068system.cpu.l2cache.overall_avg_miss_latency::total 77851.219959 # average overall miss latency 1069system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1070system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1071system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1072system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1073system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1074system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1075system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1076system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1077system.cpu.l2cache.writebacks::writebacks 66326 # number of writebacks 1078system.cpu.l2cache.writebacks::total 66326 # number of writebacks 1079system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits 1080system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1303 # number of ReadReq MSHR hits 1081system.cpu.l2cache.ReadReq_mshr_hits::total 1318 # number of ReadReq MSHR hits 1082system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1445 # number of ReadExReq MSHR hits 1083system.cpu.l2cache.ReadExReq_mshr_hits::total 1445 # number of ReadExReq MSHR hits 1084system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits 1085system.cpu.l2cache.demand_mshr_hits::cpu.data 2748 # number of demand (read+write) MSHR hits 1086system.cpu.l2cache.demand_mshr_hits::total 2763 # number of demand (read+write) MSHR hits 1087system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits 1088system.cpu.l2cache.overall_mshr_hits::cpu.data 2748 # number of overall MSHR hits 1089system.cpu.l2cache.overall_mshr_hits::total 2763 # number of overall MSHR hits 1090system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3628 # number of ReadReq MSHR misses 1091system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108380 # number of ReadReq MSHR misses 1092system.cpu.l2cache.ReadReq_mshr_misses::total 112008 # number of ReadReq MSHR misses 1093system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202241 # number of HardPFReq MSHR misses 1094system.cpu.l2cache.HardPFReq_mshr_misses::total 202241 # number of HardPFReq MSHR misses 1095system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses 1096system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses 1097system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses 1098system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses 1099system.cpu.l2cache.demand_mshr_misses::cpu.inst 3628 # number of demand (read+write) MSHR misses 1100system.cpu.l2cache.demand_mshr_misses::cpu.data 109767 # number of demand (read+write) MSHR misses 1101system.cpu.l2cache.demand_mshr_misses::total 113395 # number of demand (read+write) MSHR misses 1102system.cpu.l2cache.overall_mshr_misses::cpu.inst 3628 # number of overall MSHR misses 1103system.cpu.l2cache.overall_mshr_misses::cpu.data 109767 # number of overall MSHR misses 1104system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202241 # number of overall MSHR misses 1105system.cpu.l2cache.overall_mshr_misses::total 315636 # number of overall MSHR misses 1106system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 238098541 # number of ReadReq MSHR miss cycles 1107system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7611970750 # number of ReadReq MSHR miss cycles 1108system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7850069291 # number of ReadReq MSHR miss cycles 1109system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of HardPFReq MSHR miss cycles 1110system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17087057356 # number of HardPFReq MSHR miss cycles 1111system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 219516 # number of UpgradeReq MSHR miss cycles 1112system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 219516 # number of UpgradeReq MSHR miss cycles 1113system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114561754 # number of ReadExReq MSHR miss cycles 1114system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114561754 # number of ReadExReq MSHR miss cycles 1115system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238098541 # number of demand (read+write) MSHR miss cycles 1116system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7726532504 # number of demand (read+write) MSHR miss cycles 1117system.cpu.l2cache.demand_mshr_miss_latency::total 7964631045 # number of demand (read+write) MSHR miss cycles 1118system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238098541 # number of overall MSHR miss cycles 1119system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7726532504 # number of overall MSHR miss cycles 1120system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of overall MSHR miss cycles 1121system.cpu.l2cache.overall_mshr_miss_latency::total 25051688401 # number of overall MSHR miss cycles 1122system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for ReadReq accesses 1123system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053236 # mshr miss rate for ReadReq accesses 1124system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses 1125system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1126system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1127system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses 1128system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses 1129system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses 1130system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses 1131system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for demand accesses 1132system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for demand accesses 1133system.cpu.l2cache.demand_mshr_miss_rate::total 0.014305 # mshr miss rate for demand accesses 1134system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for overall accesses 1135system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for overall accesses 1136system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1137system.cpu.l2cache.overall_mshr_miss_rate::total 0.039817 # mshr miss rate for overall accesses 1138system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65628.043275 # average ReadReq mshr miss latency 1139system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70234.090699 # average ReadReq mshr miss latency 1140system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70084.898320 # average ReadReq mshr miss latency 1141system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average HardPFReq mshr miss latency 1142system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84488.592105 # average HardPFReq mshr miss latency 1143system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13719.750000 # average UpgradeReq mshr miss latency 1144system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13719.750000 # average UpgradeReq mshr miss latency 1145system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82596.794521 # average ReadExReq mshr miss latency 1146system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82596.794521 # average ReadExReq mshr miss latency 1147system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency 1148system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency 1149system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.938578 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency 1151system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency 1152system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average overall mshr miss latency 1153system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79368.919898 # average overall mshr miss latency 1154system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1155system.cpu.toL2Bus.trans_dist::ReadReq 7206252 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::ReadResp 7206251 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::Writeback 735277 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::HardPFReq 248818 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::ReadExReq 720844 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::ReadExResp 720844 # Transaction distribution 1163system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340787 # Packet count per connected master and slave (bytes) 1164system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248699 # Packet count per connected master and slave (bytes) 1165system.cpu.toL2Bus.pkt_count::total 16589486 # Packet count per connected master and slave (bytes) 1166system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330904640 # Cumulative packet size per connected master and slave (bytes) 1167system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223486144 # Cumulative packet size per connected master and slave (bytes) 1168system.cpu.toL2Bus.pkt_size::total 554390784 # Cumulative packet size per connected master and slave (bytes) 1169system.cpu.toL2Bus.snoops 248834 # Total snoops (count) 1170system.cpu.toL2Bus.snoop_fanout::samples 8911208 # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::mean 3.027922 # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::stdev 0.164749 # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::3 8662390 97.21% 97.21% # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::4 248818 2.79% 100.00% # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::total 8911208 # Request fanout histogram 1183system.cpu.toL2Bus.reqLayer0.occupancy 5066472000 # Layer occupancy (ticks) 1184system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1185system.cpu.toL2Bus.respLayer0.occupancy 7756152507 # Layer occupancy (ticks) 1186system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 1187system.cpu.toL2Bus.respLayer1.occupancy 4138701196 # Layer occupancy (ticks) 1188system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 1189system.membus.trans_dist::ReadReq 314173 # Transaction distribution 1190system.membus.trans_dist::ReadResp 314173 # Transaction distribution 1191system.membus.trans_dist::Writeback 66326 # Transaction distribution 1192system.membus.trans_dist::UpgradeReq 16 # Transaction distribution 1193system.membus.trans_dist::UpgradeResp 16 # Transaction distribution 1194system.membus.trans_dist::ReadExReq 1387 # Transaction distribution 1195system.membus.trans_dist::ReadExResp 1387 # Transaction distribution 1196system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697478 # Packet count per connected master and slave (bytes) 1197system.membus.pkt_count::total 697478 # Packet count per connected master and slave (bytes) 1198system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24440704 # Cumulative packet size per connected master and slave (bytes) 1199system.membus.pkt_size::total 24440704 # Cumulative packet size per connected master and slave (bytes) 1200system.membus.snoops 0 # Total snoops (count) 1201system.membus.snoop_fanout::samples 381902 # Request fanout histogram 1202system.membus.snoop_fanout::mean 0 # Request fanout histogram 1203system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1204system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1205system.membus.snoop_fanout::0 381902 100.00% 100.00% # Request fanout histogram 1206system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1207system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1208system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1209system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1210system.membus.snoop_fanout::total 381902 # Request fanout histogram 1211system.membus.reqLayer0.occupancy 746879857 # Layer occupancy (ticks) 1212system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 1213system.membus.respLayer1.occupancy 1648874306 # Layer occupancy (ticks) 1214system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 1215 1216---------- End Simulation Statistics ----------