Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.629535 # Number of seconds simulated
4sim_ticks 629535413500 # Number of ticks simulated
5final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 111054 # Simulator instruction rate (inst/s)
8host_op_rate 151240 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 50501117 # Simulator tick rate (ticks/s)
10host_mem_usage 257896 # Number of bytes of host memory used
11host_seconds 12465.77 # Real time elapsed on the host

7host_inst_rate 106173 # Simulator instruction rate (inst/s)
8host_op_rate 144593 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 48281629 # Simulator tick rate (ticks/s)
10host_mem_usage 278772 # Number of bytes of host memory used
11host_seconds 13038.82 # Real time elapsed on the host

12sim_insts 1384370590 # Number of instructions simulated
13sim_ops 1885325342 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 30242496 # Number of bytes read from this memory
18system.physmem.bytes_read::total 30397632 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 472539 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 474963 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 246429 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 48039388 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 48285817 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 246429 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 246429 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 6719673 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 6719673 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 6719673 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 246429 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 48039388 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 55005490 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 474963 # Number of read requests accepted
40system.physmem.writeReqs 66098 # Number of write requests accepted
41system.physmem.readBursts 474963 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 30390400 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue
45system.physmem.bytesWritten 4229888 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 30397632 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 4262 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 29871 # Per bank write bursts
52system.physmem.perBankRdBursts::1 29675 # Per bank write bursts
53system.physmem.perBankRdBursts::2 29749 # Per bank write bursts
54system.physmem.perBankRdBursts::3 29712 # Per bank write bursts
55system.physmem.perBankRdBursts::4 29816 # Per bank write bursts
56system.physmem.perBankRdBursts::5 29834 # Per bank write bursts
57system.physmem.perBankRdBursts::6 29642 # Per bank write bursts
58system.physmem.perBankRdBursts::7 29444 # Per bank write bursts
59system.physmem.perBankRdBursts::8 29480 # Per bank write bursts
60system.physmem.perBankRdBursts::9 29489 # Per bank write bursts
61system.physmem.perBankRdBursts::10 29547 # Per bank write bursts
62system.physmem.perBankRdBursts::11 29649 # Per bank write bursts
63system.physmem.perBankRdBursts::12 29701 # Per bank write bursts
64system.physmem.perBankRdBursts::13 29813 # Per bank write bursts
65system.physmem.perBankRdBursts::14 29629 # Per bank write bursts
66system.physmem.perBankRdBursts::15 29799 # Per bank write bursts
67system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
68system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
69system.physmem.perBankWrBursts::2 4138 # Per bank write bursts
70system.physmem.perBankWrBursts::3 4148 # Per bank write bursts
71system.physmem.perBankWrBursts::4 4226 # Per bank write bursts
72system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
73system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
74system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
75system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
76system.physmem.perBankWrBursts::9 4093 # Per bank write bursts
77system.physmem.perBankWrBursts::10 4095 # Per bank write bursts
78system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
79system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
80system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
81system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
82system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 629535350500 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 474963 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 66098 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 407876 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 66617 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 275 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132system.physmem.wrQLenPdf::0 3005 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::1 3005 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::2 3005 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::3 3005 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::4 3005 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::5 3005 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::6 3004 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 3004 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 3004 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 3004 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 3004 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 3004 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 3004 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 3004 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 3004 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 3004 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 3004 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 3005 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 3005 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 3006 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
164system.physmem.bytesPerActivate::samples 190822 # Bytes accessed per row activation
165system.physmem.bytesPerActivate::mean 181.419082 # Bytes accessed per row activation
166system.physmem.bytesPerActivate::gmean 122.160667 # Bytes accessed per row activation
167system.physmem.bytesPerActivate::stdev 377.205430 # Bytes accessed per row activation
168system.physmem.bytesPerActivate::64 76972 40.34% 40.34% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::128 49989 26.20% 66.53% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::192 37639 19.72% 86.26% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::256 19482 10.21% 96.47% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::320 187 0.10% 96.57% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::384 252 0.13% 96.70% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::448 85 0.04% 96.74% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::512 218 0.11% 96.86% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::576 85 0.04% 96.90% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::640 231 0.12% 97.02% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::704 52 0.03% 97.05% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::768 225 0.12% 97.17% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::832 65 0.03% 97.20% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::896 188 0.10% 97.30% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::960 60 0.03% 97.33% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1024 181 0.09% 97.43% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1088 44 0.02% 97.45% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1152 201 0.11% 97.55% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1216 67 0.04% 97.59% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1280 181 0.09% 97.68% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1344 66 0.03% 97.72% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::1408 3167 1.66% 99.38% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::1472 20 0.01% 99.39% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::1536 13 0.01% 99.40% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::1600 12 0.01% 99.40% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::1664 12 0.01% 99.41% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1728 13 0.01% 99.42% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1792 17 0.01% 99.42% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1856 15 0.01% 99.43% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1920 15 0.01% 99.44% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1984 19 0.01% 99.45% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::2048 10 0.01% 99.46% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::2112 18 0.01% 99.46% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::2176 13 0.01% 99.47% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::2240 11 0.01% 99.48% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::2304 14 0.01% 99.48% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::2368 14 0.01% 99.49% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::2432 15 0.01% 99.50% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::2496 21 0.01% 99.51% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::2560 12 0.01% 99.52% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::2624 17 0.01% 99.53% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::2688 16 0.01% 99.53% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::2752 16 0.01% 99.54% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::2816 13 0.01% 99.55% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::2880 12 0.01% 99.56% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::2944 12 0.01% 99.56% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::3008 14 0.01% 99.57% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::3072 9 0.00% 99.57% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::3136 19 0.01% 99.58% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::3200 10 0.01% 99.59% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::3264 20 0.01% 99.60% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::3328 10 0.01% 99.61% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::3392 16 0.01% 99.61% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::3456 12 0.01% 99.62% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::3520 21 0.01% 99.63% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::3584 13 0.01% 99.64% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::3648 16 0.01% 99.65% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3712 15 0.01% 99.65% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3776 18 0.01% 99.66% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3840 7 0.00% 99.67% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::3904 15 0.01% 99.68% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::3968 17 0.01% 99.68% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::4032 14 0.01% 99.69% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::4096 12 0.01% 99.70% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::4160 28 0.01% 99.71% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::4224 16 0.01% 99.72% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::4288 14 0.01% 99.73% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::4352 7 0.00% 99.73% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::4416 17 0.01% 99.74% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::4480 11 0.01% 99.75% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::4544 14 0.01% 99.75% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::4608 12 0.01% 99.76% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::4672 19 0.01% 99.77% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4736 10 0.01% 99.78% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4800 13 0.01% 99.78% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4864 9 0.00% 99.79% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::4928 17 0.01% 99.80% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::4992 8 0.00% 99.80% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::5056 17 0.01% 99.81% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::5120 7 0.00% 99.81% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::5184 9 0.00% 99.82% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::5248 9 0.00% 99.82% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::5312 13 0.01% 99.83% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::5376 11 0.01% 99.83% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::5440 14 0.01% 99.84% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::5504 12 0.01% 99.85% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::5568 15 0.01% 99.86% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::5632 15 0.01% 99.86% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::5696 31 0.02% 99.88% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::5760 73 0.04% 99.92% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::5824 59 0.03% 99.95% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::5888 4 0.00% 99.95% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::5952 3 0.00% 99.95% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::6016 6 0.00% 99.96% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::6080 8 0.00% 99.96% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation

267system.physmem.totQLat 3804882250 # Total ticks spent queuing
268system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM

267system.physmem.totQLat 3804806750 # Total ticks spent queuing
268system.physmem.totMemAccLat 15248020500 # Total ticks spent from burst creation until serviced by the DRAM

269system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers
270system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks

271system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst

271system.physmem.avgQLat 8012.65 # Average queueing delay per DRAM burst

272system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst
273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

274system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst

274system.physmem.avgMemAccLat 32111.24 # Average memory access latency per DRAM burst

275system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s
276system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s
277system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s
278system.physmem.avgWrBWSys 6.72 # Average system write bandwidth in MiByte/s
279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
280system.physmem.busUtil 0.43 # Data bus utilization in percentage
281system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads
282system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
283system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing
284system.physmem.avgWrQLen 6.84 # Average write queue length when enqueuing
285system.physmem.readRowHits 300749 # Number of row buffer hits during reads
286system.physmem.writeRowHits 49371 # Number of row buffer hits during writes
287system.physmem.readRowHitRate 63.34 # Row buffer hit rate for reads
288system.physmem.writeRowHitRate 74.69 # Row buffer hit rate for writes
289system.physmem.avgGap 1163520.10 # Average gap between requests
290system.physmem.pageHitRate 64.72 # Row buffer hit rate, read and write combined
291system.physmem.prechargeAllPercent 24.30 # Percentage of time for which DRAM has all the banks in precharge state
292system.membus.throughput 55005389 # Throughput (bytes/s)
293system.membus.trans_dist::ReadReq 408886 # Transaction distribution
294system.membus.trans_dist::ReadResp 408885 # Transaction distribution
295system.membus.trans_dist::Writeback 66098 # Transaction distribution
296system.membus.trans_dist::UpgradeReq 4262 # Transaction distribution
297system.membus.trans_dist::UpgradeResp 4262 # Transaction distribution
298system.membus.trans_dist::ReadExReq 66077 # Transaction distribution
299system.membus.trans_dist::ReadExResp 66077 # Transaction distribution
300system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024547 # Packet count per connected master and slave (bytes)
301system.membus.pkt_count::total 1024547 # Packet count per connected master and slave (bytes)
302system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627840 # Cumulative packet size per connected master and slave (bytes)
303system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes)
304system.membus.data_through_bus 34627840 # Total data (bytes)
305system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)

306system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks)

306system.membus.reqLayer0.occupancy 1215457500 # Layer occupancy (ticks)

307system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)

308system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks)

308system.membus.respLayer1.occupancy 4442862738 # Layer occupancy (ticks)

309system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
310system.cpu_clk_domain.clock 500 # Clock period in ticks

311system.cpu.branchPred.lookups 438247561 # Number of BP lookups
312system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted

311system.cpu.branchPred.lookups 438247722 # Number of BP lookups
312system.cpu.branchPred.condPredicted 350864471 # Number of conditional branches predicted

313system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect

314system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups
315system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits

314system.cpu.branchPred.BTBLookups 248480162 # Number of BTB lookups
315system.cpu.branchPred.BTBHits 229339460 # Number of BTB hits

316system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

317system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage

317system.cpu.branchPred.BTBHitPct 92.296889 # BTB Hit Percentage

318system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target.
319system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions.

320system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
321system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
322system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
323system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
324system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
325system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
326system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
327system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
328system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
329system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
330system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
331system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
332system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
333system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
334system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
335system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
336system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
337system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
338system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
339system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
340system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

320system.cpu.dtb.inst_hits 0 # ITB inst hits
321system.cpu.dtb.inst_misses 0 # ITB inst misses
322system.cpu.dtb.read_hits 0 # DTB read hits
323system.cpu.dtb.read_misses 0 # DTB read misses
324system.cpu.dtb.write_hits 0 # DTB write hits
325system.cpu.dtb.write_misses 0 # DTB write misses
326system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
327system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
328system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
329system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
330system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
331system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
332system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
333system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
334system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
335system.cpu.dtb.read_accesses 0 # DTB read accesses
336system.cpu.dtb.write_accesses 0 # DTB write accesses
337system.cpu.dtb.inst_accesses 0 # ITB inst accesses
338system.cpu.dtb.hits 0 # DTB hits
339system.cpu.dtb.misses 0 # DTB misses
340system.cpu.dtb.accesses 0 # DTB accesses

341system.cpu.dtb.inst_hits 0 # ITB inst hits
342system.cpu.dtb.inst_misses 0 # ITB inst misses
343system.cpu.dtb.read_hits 0 # DTB read hits
344system.cpu.dtb.read_misses 0 # DTB read misses
345system.cpu.dtb.write_hits 0 # DTB write hits
346system.cpu.dtb.write_misses 0 # DTB write misses
347system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
348system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
349system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
350system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
351system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
352system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
353system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
354system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
355system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
356system.cpu.dtb.read_accesses 0 # DTB read accesses
357system.cpu.dtb.write_accesses 0 # DTB write accesses
358system.cpu.dtb.inst_accesses 0 # ITB inst accesses
359system.cpu.dtb.hits 0 # DTB hits
360system.cpu.dtb.misses 0 # DTB misses
361system.cpu.dtb.accesses 0 # DTB accesses

362system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
363system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
364system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
365system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
366system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
367system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
368system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
369system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
372system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
373system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
374system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
375system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
376system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
377system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
378system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
379system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
380system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
381system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
382system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

341system.cpu.itb.inst_hits 0 # ITB inst hits
342system.cpu.itb.inst_misses 0 # ITB inst misses
343system.cpu.itb.read_hits 0 # DTB read hits
344system.cpu.itb.read_misses 0 # DTB read misses
345system.cpu.itb.write_hits 0 # DTB write hits
346system.cpu.itb.write_misses 0 # DTB write misses
347system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
348system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
349system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
350system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
351system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
352system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
353system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
354system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
355system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
356system.cpu.itb.read_accesses 0 # DTB read accesses
357system.cpu.itb.write_accesses 0 # DTB write accesses
358system.cpu.itb.inst_accesses 0 # ITB inst accesses
359system.cpu.itb.hits 0 # DTB hits
360system.cpu.itb.misses 0 # DTB misses
361system.cpu.itb.accesses 0 # DTB accesses
362system.cpu.workload.num_syscalls 1411 # Number of system calls
363system.cpu.numCycles 1259070828 # number of cpu cycles simulated
364system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
365system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

383system.cpu.itb.inst_hits 0 # ITB inst hits
384system.cpu.itb.inst_misses 0 # ITB inst misses
385system.cpu.itb.read_hits 0 # DTB read hits
386system.cpu.itb.read_misses 0 # DTB read misses
387system.cpu.itb.write_hits 0 # DTB write hits
388system.cpu.itb.write_misses 0 # DTB write misses
389system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
390system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
391system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
392system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
393system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
394system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
395system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
396system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
397system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
398system.cpu.itb.read_accesses 0 # DTB read accesses
399system.cpu.itb.write_accesses 0 # DTB write accesses
400system.cpu.itb.inst_accesses 0 # ITB inst accesses
401system.cpu.itb.hits 0 # DTB hits
402system.cpu.itb.misses 0 # DTB misses
403system.cpu.itb.accesses 0 # DTB accesses
404system.cpu.workload.num_syscalls 1411 # Number of system calls
405system.cpu.numCycles 1259070828 # number of cpu cycles simulated
406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

366system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss
367system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed
368system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered
369system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken
370system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked
371system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing
372system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked

408system.cpu.fetch.icacheStallCycles 354141020 # Number of cycles fetch is stalled on an Icache miss
409system.cpu.fetch.Insts 2279761292 # Number of instructions fetch has processed
410system.cpu.fetch.Branches 438247722 # Number of branches that fetch encountered
411system.cpu.fetch.predictedBranches 282255131 # Number of branches that fetch has predicted taken
412system.cpu.fetch.Cycles 601258233 # Number of cycles fetch has run and was not squashing or blocked
413system.cpu.fetch.SquashCycles 157188182 # Number of cycles fetch has spent squashing
414system.cpu.fetch.BlockedCycles 134732573 # Number of cycles fetch has spent blocked

373system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
374system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps
375system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR
376system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched

415system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
416system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps
417system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR
418system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched

377system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed
378system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total)
379system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total)

419system.cpu.fetch.IcacheSquashes 11658358 # Number of outstanding Icache misses that were squashed
420system.cpu.fetch.rateDist::samples 1216659303 # Number of instructions fetched each cycle (Total)
421system.cpu.fetch.rateDist::mean 2.575913 # Number of instructions fetched each cycle (Total)

380system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total)
381system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

422system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total)
423system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

382system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total)

424system.cpu.fetch.rateDist::0 615445842 50.58% 50.58% # Number of instructions fetched each cycle (Total)

383system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total)
384system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total)
385system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total)
386system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total)

425system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total)
426system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total)
427system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total)
428system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total)

387system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total)

429system.cpu.fetch.rateDist::5 44699403 3.67% 76.27% # Number of instructions fetched each cycle (Total)

388system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total)
389system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total)
390system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total)
391system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
392system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
393system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

430system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total)
431system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total)
432system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total)
433system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
434system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
435system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

394system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total)

436system.cpu.fetch.rateDist::total 1216659303 # Number of instructions fetched each cycle (Total)

395system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle

437system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle

396system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle
397system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle
398system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked
399system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running
400system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking
401system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing
402system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch

438system.cpu.fetch.rate 1.810670 # Number of inst fetches per cycle
439system.cpu.decode.IdleCycles 405371770 # Number of cycles decode is idle
440system.cpu.decode.BlockedCycles 106745247 # Number of cycles decode is blocked
441system.cpu.decode.RunCycles 560687148 # Number of cycles decode is running
442system.cpu.decode.UnblockCycles 17351012 # Number of cycles decode is unblocking
443system.cpu.decode.SquashCycles 126504126 # Number of cycles decode is squashing
444system.cpu.decode.BranchResolved 44828011 # Number of times decode resolved a branch

403system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction

445system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction

404system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode

446system.cpu.decode.DecodedInsts 3022924000 # Number of instructions handled by decode

405system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode

447system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode

406system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing
407system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle
408system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking
409system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst
410system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running
411system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking
412system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename

448system.cpu.rename.SquashCycles 126504126 # Number of cycles rename is squashing
449system.cpu.rename.IdleCycles 441422956 # Number of cycles rename is idle
450system.cpu.rename.BlockCycles 38086039 # Number of cycles rename is blocking
451system.cpu.rename.serializeStallCycles 457739 # count of cycles rename stalled for serializing inst
452system.cpu.rename.RunCycles 539750713 # Number of cycles rename is running
453system.cpu.rename.UnblockCycles 70437730 # Number of cycles rename is unblocking
454system.cpu.rename.RenamedInsts 2941757147 # Number of instructions processed by rename

413system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full
414system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full

455system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full
456system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full

415system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full
416system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
417system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed
418system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made
419system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups

457system.cpu.rename.LSQFullEvents 54385461 # Number of times rename has blocked due to LSQ full
458system.cpu.rename.FullRegisterEvents 740 # Number of times there has been no free registers
459system.cpu.rename.RenamedOperands 2930215043 # Number of destination operands rename has renamed
460system.cpu.rename.RenameLookups 14237570542 # Number of register rename lookups that rename has made
461system.cpu.rename.int_rename_lookups 12151139431 # Number of integer rename lookups

420system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups
421system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed

462system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups
463system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed

422system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing

464system.cpu.rename.UndoneMaps 937074953 # Number of HB maps that are undone due to squashing

423system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed
424system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed

465system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed
466system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed

425system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer

467system.cpu.rename.skidInsts 179296103 # count of insts added to the skid buffer

426system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit.
427system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit.
428system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads.
429system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores.

468system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit.
469system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit.
470system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads.
471system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores.

430system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec)

472system.cpu.iq.iqInstsAdded 2792666387 # Number of instructions added to the IQ (excludes non-spec)

431system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ

473system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ

432system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued

474system.cpu.iq.iqInstsIssued 2435151733 # Number of instructions issued

433system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued

475system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued

434system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling
435system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph

476system.cpu.iq.iqSquashedInstsExamined 894813074 # Number of squashed instructions iterated over during squash; mainly for profiling
477system.cpu.iq.iqSquashedOperandsExamined 2341267254 # Number of squashed operands that are examined and possibly removed from graph

436system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed

478system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed

437system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle

479system.cpu.iq.issued_per_cycle::samples 1216659303 # Number of insts issued each cycle

438system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle

480system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle

439system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle

481system.cpu.iq.issued_per_cycle::stdev 1.873340 # Number of insts issued each cycle

440system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

482system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

441system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle
442system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle
443system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle
444system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle
445system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle
446system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle

483system.cpu.iq.issued_per_cycle::0 380682463 31.29% 31.29% # Number of insts issued each cycle
484system.cpu.iq.issued_per_cycle::1 183043299 15.04% 46.33% # Number of insts issued each cycle
485system.cpu.iq.issued_per_cycle::2 204121257 16.78% 63.11% # Number of insts issued each cycle
486system.cpu.iq.issued_per_cycle::3 169552429 13.94% 77.05% # Number of insts issued each cycle
487system.cpu.iq.issued_per_cycle::4 132904836 10.92% 87.97% # Number of insts issued each cycle
488system.cpu.iq.issued_per_cycle::5 92976040 7.64% 95.61% # Number of insts issued each cycle

447system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle

489system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle

448system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle

490system.cpu.iq.issued_per_cycle::7 12393775 1.02% 99.75% # Number of insts issued each cycle

449system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle
450system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
451system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
452system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

491system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle
492system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
493system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
494system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

453system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle

495system.cpu.iq.issued_per_cycle::total 1216659303 # Number of insts issued each cycle

454system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
455system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available
456system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available
457system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
458system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
459system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
460system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available
461system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available
462system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available
463system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
464system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available
465system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available
466system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available
467system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available
468system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available
469system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available
470system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available
471system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available
472system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available
473system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available
474system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available
475system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available
476system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available
477system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available
478system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available
479system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available
480system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available
481system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
482system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
483system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
484system.cpu.iq.fu_full::MemRead 55158409 62.92% 63.76% # attempts to use FU when none available
485system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # attempts to use FU when none available
486system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
487system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
488system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

496system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
497system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available
498system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available
499system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
500system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
501system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
502system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available
503system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available
504system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available
505system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
506system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available
507system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available
508system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available
509system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available
510system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available
511system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available
512system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available
513system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available
514system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available
515system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available
516system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available
517system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available
518system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available
519system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available
520system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available
521system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available
522system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available
523system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
524system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
525system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
526system.cpu.iq.fu_full::MemRead 55158409 62.92% 63.76% # attempts to use FU when none available
527system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # attempts to use FU when none available
528system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
529system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
530system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

489system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued

531system.cpu.iq.FU_type_0::IntAlu 1104245990 45.35% 45.35% # Type of FU issued

490system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued
491system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued
492system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued
493system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.81% # Type of FU issued
494system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.81% # Type of FU issued
495system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.81% # Type of FU issued
496system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.81% # Type of FU issued
497system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.81% # Type of FU issued
498system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.81% # Type of FU issued
499system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.81% # Type of FU issued
500system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.81% # Type of FU issued
501system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.81% # Type of FU issued
502system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.81% # Type of FU issued
503system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.81% # Type of FU issued
504system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.81% # Type of FU issued
505system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.81% # Type of FU issued
506system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.81% # Type of FU issued
507system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.81% # Type of FU issued
508system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.81% # Type of FU issued
509system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.86% # Type of FU issued
510system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.86% # Type of FU issued
511system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.15% # Type of FU issued
512system.cpu.iq.FU_type_0::SimdFloatCvt 5502438 0.23% 46.37% # Type of FU issued
513system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.37% # Type of FU issued
514system.cpu.iq.FU_type_0::SimdFloatMisc 23399832 0.96% 47.33% # Type of FU issued
515system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
516system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued
517system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
518system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Type of FU issued
519system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued
520system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
521system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

532system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued
533system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued
534system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued
535system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.81% # Type of FU issued
536system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.81% # Type of FU issued
537system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.81% # Type of FU issued
538system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.81% # Type of FU issued
539system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.81% # Type of FU issued
540system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.81% # Type of FU issued
541system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.81% # Type of FU issued
542system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.81% # Type of FU issued
543system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.81% # Type of FU issued
544system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.81% # Type of FU issued
545system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.81% # Type of FU issued
546system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.81% # Type of FU issued
547system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.81% # Type of FU issued
548system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.81% # Type of FU issued
549system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.81% # Type of FU issued
550system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.81% # Type of FU issued
551system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.86% # Type of FU issued
552system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.86% # Type of FU issued
553system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.15% # Type of FU issued
554system.cpu.iq.FU_type_0::SimdFloatCvt 5502438 0.23% 46.37% # Type of FU issued
555system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.37% # Type of FU issued
556system.cpu.iq.FU_type_0::SimdFloatMisc 23399832 0.96% 47.33% # Type of FU issued
557system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
558system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued
559system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
560system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Type of FU issued
561system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued
562system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
563system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

522system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued
523system.cpu.iq.rate 1.934087 # Inst issue rate

564system.cpu.iq.FU_type_0::total 2435151733 # Type of FU issued
565system.cpu.iq.rate 1.934086 # Inst issue rate

524system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested
525system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst)

566system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested
567system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst)

526system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads
527system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes
528system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses

568system.cpu.iq.int_inst_queue_reads 6065394864 # Number of integer instruction queue reads
569system.cpu.iq.int_inst_queue_writes 3604907210 # Number of integer instruction queue writes
570system.cpu.iq.int_inst_queue_wakeup_accesses 2250139818 # Number of integer instruction queue wakeup accesses

529system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads
530system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes
531system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses

571system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads
572system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes
573system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses

532system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses

574system.cpu.iq.int_alu_accesses 2459502901 # Number of integer alu accesses

533system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses
534system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores
535system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
536system.cpu.iew.lsq.thread0.squashedLoads 340360670 # Number of loads squashed
537system.cpu.iew.lsq.thread0.ignoredResponses 9529 # Number of memory responses ignored because the instruction is squashed
538system.cpu.iew.lsq.thread0.memOrderViolation 1430281 # Number of memory ordering violations
539system.cpu.iew.lsq.thread0.squashedStores 208692629 # Number of stores squashed
540system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
541system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
542system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled

575system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses
576system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores
577system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
578system.cpu.iew.lsq.thread0.squashedLoads 340360670 # Number of loads squashed
579system.cpu.iew.lsq.thread0.ignoredResponses 9529 # Number of memory responses ignored because the instruction is squashed
580system.cpu.iew.lsq.thread0.memOrderViolation 1430281 # Number of memory ordering violations
581system.cpu.iew.lsq.thread0.squashedStores 208692629 # Number of stores squashed
582system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
583system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
584system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled

543system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked

585system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked

544system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

586system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

545system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing

587system.cpu.iew.iewSquashCycles 126504126 # Number of cycles IEW is squashing

546system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking
547system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking

588system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking
589system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking

548system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ
549system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch

590system.cpu.iew.iewDispatchedInsts 2792706809 # Number of instructions dispatched to IQ
591system.cpu.iew.iewDispSquashedInsts 1386483 # Number of squashed instructions skipped by dispatch

550system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions
551system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions
552system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions
553system.cpu.iew.iewIQFullEvents 1559989 # Number of times the IQ has become full, causing a stall
554system.cpu.iew.iewLSQFullEvents 2525 # Number of times the LSQ has become full, causing a stall
555system.cpu.iew.memOrderViolationEvents 1430281 # Number of memory order violations
556system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly
557system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly
558system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute

592system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions
593system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions
594system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions
595system.cpu.iew.iewIQFullEvents 1559989 # Number of times the IQ has become full, causing a stall
596system.cpu.iew.iewLSQFullEvents 2525 # Number of times the LSQ has become full, causing a stall
597system.cpu.iew.memOrderViolationEvents 1430281 # Number of memory order violations
598system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly
599system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly
600system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute

559system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions
560system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed
561system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute

601system.cpu.iew.iewExecutedInsts 2359934527 # Number of executed instructions
602system.cpu.iew.iewExecLoadInsts 794158761 # Number of load instructions executed
603system.cpu.iew.iewExecSquashedInsts 75217206 # Number of squashed instructions skipped in execute

562system.cpu.iew.exec_swp 0 # number of swp insts executed
563system.cpu.iew.exec_nop 12446 # number of nop insts executed

604system.cpu.iew.exec_swp 0 # number of swp insts executed
605system.cpu.iew.exec_nop 12446 # number of nop insts executed

564system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed

606system.cpu.iew.exec_refs 1217435347 # number of memory reference insts executed

565system.cpu.iew.exec_branches 319532182 # Number of branches executed
566system.cpu.iew.exec_stores 423276586 # Number of stores executed
567system.cpu.iew.exec_rate 1.874346 # Inst execution rate

607system.cpu.iew.exec_branches 319532182 # Number of branches executed
608system.cpu.iew.exec_stores 423276586 # Number of stores executed
609system.cpu.iew.exec_rate 1.874346 # Inst execution rate

568system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit
569system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back
570system.cpu.iew.wb_producers 1349155886 # num instructions producing a value
571system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value

610system.cpu.iew.wb_sent 2332318600 # cumulative count of insts sent to commit
611system.cpu.iew.wb_count 2306572921 # cumulative count of insts written-back
612system.cpu.iew.wb_producers 1349155649 # num instructions producing a value
613system.cpu.iew.wb_consumers 2527421878 # num instructions consuming a value

572system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

614system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

573system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle

615system.cpu.iew.wb_rate 1.831964 # insts written-back per cycle

574system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back
575system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

616system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back
617system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

576system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit

618system.cpu.commit.commitSquashedInsts 907370579 # The number of squashed insts skipped by commit

577system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
578system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted

619system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
620system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted

579system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle

621system.cpu.commit.committed_per_cycle::samples 1090155177 # Number of insts commited each cycle

580system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle
581system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle
582system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

622system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle
623system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle
624system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

583system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle
584system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle
585system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle
586system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle
587system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle

625system.cpu.commit.committed_per_cycle::0 449868742 41.27% 41.27% # Number of insts commited each cycle
626system.cpu.commit.committed_per_cycle::1 288583282 26.47% 67.74% # Number of insts commited each cycle
627system.cpu.commit.committed_per_cycle::2 95106533 8.72% 76.46% # Number of insts commited each cycle
628system.cpu.commit.committed_per_cycle::3 70222065 6.44% 82.90% # Number of insts commited each cycle
629system.cpu.commit.committed_per_cycle::4 46473839 4.26% 87.17% # Number of insts commited each cycle

588system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle

630system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle

589system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle
590system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle

631system.cpu.commit.committed_per_cycle::6 15848509 1.45% 90.66% # Number of insts commited each cycle
632system.cpu.commit.committed_per_cycle::7 10986576 1.01% 91.66% # Number of insts commited each cycle

591system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle
592system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
593system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
594system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

633system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle
634system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
635system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
636system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

595system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle

637system.cpu.commit.committed_per_cycle::total 1090155177 # Number of insts commited each cycle

596system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
597system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
598system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
599system.cpu.commit.refs 908382478 # Number of memory references committed
600system.cpu.commit.loads 631387181 # Number of loads committed
601system.cpu.commit.membars 9986 # Number of memory barriers committed
602system.cpu.commit.branches 298259106 # Number of branches committed
603system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
604system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
605system.cpu.commit.function_calls 41577833 # Number of function calls committed.
606system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached
607system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

638system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
639system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
640system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
641system.cpu.commit.refs 908382478 # Number of memory references committed
642system.cpu.commit.loads 631387181 # Number of loads committed
643system.cpu.commit.membars 9986 # Number of memory barriers committed
644system.cpu.commit.branches 298259106 # Number of branches committed
645system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
646system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
647system.cpu.commit.function_calls 41577833 # Number of function calls committed.
648system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached
649system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

608system.cpu.rob.rob_reads 3791959297 # The number of ROB reads
609system.cpu.rob.rob_writes 5711929091 # The number of ROB writes

650system.cpu.rob.rob_reads 3791959363 # The number of ROB reads
651system.cpu.rob.rob_writes 5711929117 # The number of ROB writes

610system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself

652system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself

611system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling

653system.cpu.idleCycles 42411525 # Total number of cycles that the CPU has spent unscheduled due to idling

612system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
613system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
614system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
615system.cpu.cpi 0.909490 # CPI: Cycles Per Instruction
616system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads
617system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle
618system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads

654system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
655system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
656system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
657system.cpu.cpi 0.909490 # CPI: Cycles Per Instruction
658system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads
659system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle
660system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads

619system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads
620system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes

661system.cpu.int_regfile_reads 11767673388 # number of integer regfile reads
662system.cpu.int_regfile_writes 2220511965 # number of integer regfile writes

621system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads
622system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes

663system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads
664system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes

623system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads

665system.cpu.misc_regfile_reads 1678583418 # number of misc regfile reads

624system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
625system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s)
626system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution
627system.cpu.toL2Bus.trans_dist::ReadResp 1493830 # Transaction distribution
628system.cpu.toL2Bus.trans_dist::Writeback 96313 # Transaction distribution
629system.cpu.toL2Bus.trans_dist::UpgradeReq 4265 # Transaction distribution
630system.cpu.toL2Bus.trans_dist::UpgradeResp 4265 # Transaction distribution
631system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution
632system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution
633system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54300 # Packet count per connected master and slave (bytes)
634system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178976 # Packet count per connected master and slave (bytes)
635system.cpu.toL2Bus.pkt_count::total 3233276 # Packet count per connected master and slave (bytes)
636system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1601152 # Cumulative packet size per connected master and slave (bytes)
637system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536256 # Cumulative packet size per connected master and slave (bytes)
638system.cpu.toL2Bus.tot_pkt_size::total 106137408 # Cumulative packet size per connected master and slave (bytes)
639system.cpu.toL2Bus.data_through_bus 106137408 # Total data (bytes)
640system.cpu.toL2Bus.snoop_data_through_bus 272896 # Total snoop data (bytes)
641system.cpu.toL2Bus.reqLayer0.occupancy 929776999 # Layer occupancy (ticks)
642system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
643system.cpu.toL2Bus.respLayer0.occupancy 44342246 # Layer occupancy (ticks)
644system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
645system.cpu.toL2Bus.respLayer1.occupancy 2368551488 # Layer occupancy (ticks)
646system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
647system.cpu.icache.tags.replacements 23332 # number of replacements
648system.cpu.icache.tags.tagsinuse 1641.273486 # Cycle average of tags in use
649system.cpu.icache.tags.total_refs 334698554 # Total number of references to valid blocks.
650system.cpu.icache.tags.sampled_refs 25017 # Sample count of references to valid blocks.
651system.cpu.icache.tags.avg_refs 13378.844546 # Average number of references to valid blocks.
652system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
653system.cpu.icache.tags.occ_blocks::cpu.inst 1641.273486 # Average occupied blocks per requestor
654system.cpu.icache.tags.occ_percent::cpu.inst 0.801403 # Average percentage of cache occupancy
655system.cpu.icache.tags.occ_percent::total 0.801403 # Average percentage of cache occupancy
656system.cpu.icache.tags.occ_task_id_blocks::1024 1685 # Occupied blocks per task id
657system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
658system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
659system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
660system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
661system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id
662system.cpu.icache.tags.occ_task_id_percent::1024 0.822754 # Percentage of cache occupancy per task id
663system.cpu.icache.tags.tag_accesses 669498564 # Number of tag accesses
664system.cpu.icache.tags.data_accesses 669498564 # Number of data accesses
665system.cpu.icache.ReadReq_hits::cpu.inst 334702534 # number of ReadReq hits
666system.cpu.icache.ReadReq_hits::total 334702534 # number of ReadReq hits
667system.cpu.icache.demand_hits::cpu.inst 334702534 # number of demand (read+write) hits
668system.cpu.icache.demand_hits::total 334702534 # number of demand (read+write) hits
669system.cpu.icache.overall_hits::cpu.inst 334702534 # number of overall hits
670system.cpu.icache.overall_hits::total 334702534 # number of overall hits
671system.cpu.icache.ReadReq_misses::cpu.inst 32107 # number of ReadReq misses
672system.cpu.icache.ReadReq_misses::total 32107 # number of ReadReq misses
673system.cpu.icache.demand_misses::cpu.inst 32107 # number of demand (read+write) misses
674system.cpu.icache.demand_misses::total 32107 # number of demand (read+write) misses
675system.cpu.icache.overall_misses::cpu.inst 32107 # number of overall misses
676system.cpu.icache.overall_misses::total 32107 # number of overall misses
677system.cpu.icache.ReadReq_miss_latency::cpu.inst 545585992 # number of ReadReq miss cycles
678system.cpu.icache.ReadReq_miss_latency::total 545585992 # number of ReadReq miss cycles
679system.cpu.icache.demand_miss_latency::cpu.inst 545585992 # number of demand (read+write) miss cycles
680system.cpu.icache.demand_miss_latency::total 545585992 # number of demand (read+write) miss cycles
681system.cpu.icache.overall_miss_latency::cpu.inst 545585992 # number of overall miss cycles
682system.cpu.icache.overall_miss_latency::total 545585992 # number of overall miss cycles
683system.cpu.icache.ReadReq_accesses::cpu.inst 334734641 # number of ReadReq accesses(hits+misses)
684system.cpu.icache.ReadReq_accesses::total 334734641 # number of ReadReq accesses(hits+misses)
685system.cpu.icache.demand_accesses::cpu.inst 334734641 # number of demand (read+write) accesses
686system.cpu.icache.demand_accesses::total 334734641 # number of demand (read+write) accesses
687system.cpu.icache.overall_accesses::cpu.inst 334734641 # number of overall (read+write) accesses
688system.cpu.icache.overall_accesses::total 334734641 # number of overall (read+write) accesses
689system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses
690system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses
691system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses
692system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses
693system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses
694system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses
695system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16992.742766 # average ReadReq miss latency
696system.cpu.icache.ReadReq_avg_miss_latency::total 16992.742766 # average ReadReq miss latency
697system.cpu.icache.demand_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency
698system.cpu.icache.demand_avg_miss_latency::total 16992.742766 # average overall miss latency
699system.cpu.icache.overall_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency
700system.cpu.icache.overall_avg_miss_latency::total 16992.742766 # average overall miss latency
701system.cpu.icache.blocked_cycles::no_mshrs 2092 # number of cycles access was blocked
702system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
703system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked
704system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
705system.cpu.icache.avg_blocked_cycles::no_mshrs 55.052632 # average number of cycles each access was blocked
706system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
707system.cpu.icache.fast_writes 0 # number of fast writes performed
708system.cpu.icache.cache_copies 0 # number of cache copies performed
709system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2825 # number of ReadReq MSHR hits
710system.cpu.icache.ReadReq_mshr_hits::total 2825 # number of ReadReq MSHR hits
711system.cpu.icache.demand_mshr_hits::cpu.inst 2825 # number of demand (read+write) MSHR hits
712system.cpu.icache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits
713system.cpu.icache.overall_mshr_hits::cpu.inst 2825 # number of overall MSHR hits
714system.cpu.icache.overall_mshr_hits::total 2825 # number of overall MSHR hits
715system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29282 # number of ReadReq MSHR misses
716system.cpu.icache.ReadReq_mshr_misses::total 29282 # number of ReadReq MSHR misses
717system.cpu.icache.demand_mshr_misses::cpu.inst 29282 # number of demand (read+write) MSHR misses
718system.cpu.icache.demand_mshr_misses::total 29282 # number of demand (read+write) MSHR misses
719system.cpu.icache.overall_mshr_misses::cpu.inst 29282 # number of overall MSHR misses
720system.cpu.icache.overall_mshr_misses::total 29282 # number of overall MSHR misses
721system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435718750 # number of ReadReq MSHR miss cycles
722system.cpu.icache.ReadReq_mshr_miss_latency::total 435718750 # number of ReadReq MSHR miss cycles
723system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435718750 # number of demand (read+write) MSHR miss cycles
724system.cpu.icache.demand_mshr_miss_latency::total 435718750 # number of demand (read+write) MSHR miss cycles
725system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435718750 # number of overall MSHR miss cycles
726system.cpu.icache.overall_mshr_miss_latency::total 435718750 # number of overall MSHR miss cycles
727system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
728system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
729system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
730system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
731system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
732system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
733system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14880.088450 # average ReadReq mshr miss latency
734system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14880.088450 # average ReadReq mshr miss latency
735system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency
736system.cpu.icache.demand_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency
737system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency
738system.cpu.icache.overall_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency
739system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
740system.cpu.l2cache.tags.replacements 442179 # number of replacements
741system.cpu.l2cache.tags.tagsinuse 32678.084712 # Cycle average of tags in use
742system.cpu.l2cache.tags.total_refs 1110777 # Total number of references to valid blocks.
743system.cpu.l2cache.tags.sampled_refs 474927 # Sample count of references to valid blocks.
744system.cpu.l2cache.tags.avg_refs 2.338837 # Average number of references to valid blocks.
745system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

666system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
667system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s)
668system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution
669system.cpu.toL2Bus.trans_dist::ReadResp 1493830 # Transaction distribution
670system.cpu.toL2Bus.trans_dist::Writeback 96313 # Transaction distribution
671system.cpu.toL2Bus.trans_dist::UpgradeReq 4265 # Transaction distribution
672system.cpu.toL2Bus.trans_dist::UpgradeResp 4265 # Transaction distribution
673system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution
674system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution
675system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54300 # Packet count per connected master and slave (bytes)
676system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178976 # Packet count per connected master and slave (bytes)
677system.cpu.toL2Bus.pkt_count::total 3233276 # Packet count per connected master and slave (bytes)
678system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1601152 # Cumulative packet size per connected master and slave (bytes)
679system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536256 # Cumulative packet size per connected master and slave (bytes)
680system.cpu.toL2Bus.tot_pkt_size::total 106137408 # Cumulative packet size per connected master and slave (bytes)
681system.cpu.toL2Bus.data_through_bus 106137408 # Total data (bytes)
682system.cpu.toL2Bus.snoop_data_through_bus 272896 # Total snoop data (bytes)
683system.cpu.toL2Bus.reqLayer0.occupancy 929776999 # Layer occupancy (ticks)
684system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
685system.cpu.toL2Bus.respLayer0.occupancy 44342246 # Layer occupancy (ticks)
686system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
687system.cpu.toL2Bus.respLayer1.occupancy 2368551488 # Layer occupancy (ticks)
688system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
689system.cpu.icache.tags.replacements 23332 # number of replacements
690system.cpu.icache.tags.tagsinuse 1641.273486 # Cycle average of tags in use
691system.cpu.icache.tags.total_refs 334698554 # Total number of references to valid blocks.
692system.cpu.icache.tags.sampled_refs 25017 # Sample count of references to valid blocks.
693system.cpu.icache.tags.avg_refs 13378.844546 # Average number of references to valid blocks.
694system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
695system.cpu.icache.tags.occ_blocks::cpu.inst 1641.273486 # Average occupied blocks per requestor
696system.cpu.icache.tags.occ_percent::cpu.inst 0.801403 # Average percentage of cache occupancy
697system.cpu.icache.tags.occ_percent::total 0.801403 # Average percentage of cache occupancy
698system.cpu.icache.tags.occ_task_id_blocks::1024 1685 # Occupied blocks per task id
699system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
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701system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
702system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
703system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id
704system.cpu.icache.tags.occ_task_id_percent::1024 0.822754 # Percentage of cache occupancy per task id
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706system.cpu.icache.tags.data_accesses 669498564 # Number of data accesses
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708system.cpu.icache.ReadReq_hits::total 334702534 # number of ReadReq hits
709system.cpu.icache.demand_hits::cpu.inst 334702534 # number of demand (read+write) hits
710system.cpu.icache.demand_hits::total 334702534 # number of demand (read+write) hits
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712system.cpu.icache.overall_hits::total 334702534 # number of overall hits
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714system.cpu.icache.ReadReq_misses::total 32107 # number of ReadReq misses
715system.cpu.icache.demand_misses::cpu.inst 32107 # number of demand (read+write) misses
716system.cpu.icache.demand_misses::total 32107 # number of demand (read+write) misses
717system.cpu.icache.overall_misses::cpu.inst 32107 # number of overall misses
718system.cpu.icache.overall_misses::total 32107 # number of overall misses
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720system.cpu.icache.ReadReq_miss_latency::total 545585992 # number of ReadReq miss cycles
721system.cpu.icache.demand_miss_latency::cpu.inst 545585992 # number of demand (read+write) miss cycles
722system.cpu.icache.demand_miss_latency::total 545585992 # number of demand (read+write) miss cycles
723system.cpu.icache.overall_miss_latency::cpu.inst 545585992 # number of overall miss cycles
724system.cpu.icache.overall_miss_latency::total 545585992 # number of overall miss cycles
725system.cpu.icache.ReadReq_accesses::cpu.inst 334734641 # number of ReadReq accesses(hits+misses)
726system.cpu.icache.ReadReq_accesses::total 334734641 # number of ReadReq accesses(hits+misses)
727system.cpu.icache.demand_accesses::cpu.inst 334734641 # number of demand (read+write) accesses
728system.cpu.icache.demand_accesses::total 334734641 # number of demand (read+write) accesses
729system.cpu.icache.overall_accesses::cpu.inst 334734641 # number of overall (read+write) accesses
730system.cpu.icache.overall_accesses::total 334734641 # number of overall (read+write) accesses
731system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses
732system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses
733system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses
734system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses
735system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses
736system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses
737system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16992.742766 # average ReadReq miss latency
738system.cpu.icache.ReadReq_avg_miss_latency::total 16992.742766 # average ReadReq miss latency
739system.cpu.icache.demand_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency
740system.cpu.icache.demand_avg_miss_latency::total 16992.742766 # average overall miss latency
741system.cpu.icache.overall_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency
742system.cpu.icache.overall_avg_miss_latency::total 16992.742766 # average overall miss latency
743system.cpu.icache.blocked_cycles::no_mshrs 2092 # number of cycles access was blocked
744system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
745system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked
746system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
747system.cpu.icache.avg_blocked_cycles::no_mshrs 55.052632 # average number of cycles each access was blocked
748system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
749system.cpu.icache.fast_writes 0 # number of fast writes performed
750system.cpu.icache.cache_copies 0 # number of cache copies performed
751system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2825 # number of ReadReq MSHR hits
752system.cpu.icache.ReadReq_mshr_hits::total 2825 # number of ReadReq MSHR hits
753system.cpu.icache.demand_mshr_hits::cpu.inst 2825 # number of demand (read+write) MSHR hits
754system.cpu.icache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits
755system.cpu.icache.overall_mshr_hits::cpu.inst 2825 # number of overall MSHR hits
756system.cpu.icache.overall_mshr_hits::total 2825 # number of overall MSHR hits
757system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29282 # number of ReadReq MSHR misses
758system.cpu.icache.ReadReq_mshr_misses::total 29282 # number of ReadReq MSHR misses
759system.cpu.icache.demand_mshr_misses::cpu.inst 29282 # number of demand (read+write) MSHR misses
760system.cpu.icache.demand_mshr_misses::total 29282 # number of demand (read+write) MSHR misses
761system.cpu.icache.overall_mshr_misses::cpu.inst 29282 # number of overall MSHR misses
762system.cpu.icache.overall_mshr_misses::total 29282 # number of overall MSHR misses
763system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435718750 # number of ReadReq MSHR miss cycles
764system.cpu.icache.ReadReq_mshr_miss_latency::total 435718750 # number of ReadReq MSHR miss cycles
765system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435718750 # number of demand (read+write) MSHR miss cycles
766system.cpu.icache.demand_mshr_miss_latency::total 435718750 # number of demand (read+write) MSHR miss cycles
767system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435718750 # number of overall MSHR miss cycles
768system.cpu.icache.overall_mshr_miss_latency::total 435718750 # number of overall MSHR miss cycles
769system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
770system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
771system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
772system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
773system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
774system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
775system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14880.088450 # average ReadReq mshr miss latency
776system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14880.088450 # average ReadReq mshr miss latency
777system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency
778system.cpu.icache.demand_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency
779system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency
780system.cpu.icache.overall_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency
781system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
782system.cpu.l2cache.tags.replacements 442179 # number of replacements
783system.cpu.l2cache.tags.tagsinuse 32678.084712 # Cycle average of tags in use
784system.cpu.l2cache.tags.total_refs 1110777 # Total number of references to valid blocks.
785system.cpu.l2cache.tags.sampled_refs 474927 # Sample count of references to valid blocks.
786system.cpu.l2cache.tags.avg_refs 2.338837 # Average number of references to valid blocks.
787system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

746system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536897 # Average occupied blocks per requestor

788system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536898 # Average occupied blocks per requestor

747system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.699719 # Average occupied blocks per requestor
748system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096 # Average occupied blocks per requestor
749system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 # Average percentage of cache occupancy
750system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001578 # Average percentage of cache occupancy
751system.cpu.l2cache.tags.occ_percent::cpu.data 0.955470 # Average percentage of cache occupancy
752system.cpu.l2cache.tags.occ_percent::total 0.997256 # Average percentage of cache occupancy
753system.cpu.l2cache.tags.occ_task_id_blocks::1024 32748 # Occupied blocks per task id
754system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
755system.cpu.l2cache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id
756system.cpu.l2cache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id
757system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5020 # Occupied blocks per task id
758system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26968 # Occupied blocks per task id
759system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999390 # Percentage of cache occupancy per task id
760system.cpu.l2cache.tags.tag_accesses 13848752 # Number of tag accesses
761system.cpu.l2cache.tags.data_accesses 13848752 # Number of data accesses
762system.cpu.l2cache.ReadReq_hits::cpu.inst 22592 # number of ReadReq hits
763system.cpu.l2cache.ReadReq_hits::cpu.data 1058063 # number of ReadReq hits
764system.cpu.l2cache.ReadReq_hits::total 1080655 # number of ReadReq hits
765system.cpu.l2cache.Writeback_hits::writebacks 96313 # number of Writeback hits
766system.cpu.l2cache.Writeback_hits::total 96313 # number of Writeback hits
767system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
768system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
769system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits
770system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits
771system.cpu.l2cache.demand_hits::cpu.inst 22592 # number of demand (read+write) hits
772system.cpu.l2cache.demand_hits::cpu.data 1064504 # number of demand (read+write) hits
773system.cpu.l2cache.demand_hits::total 1087096 # number of demand (read+write) hits
774system.cpu.l2cache.overall_hits::cpu.inst 22592 # number of overall hits
775system.cpu.l2cache.overall_hits::cpu.data 1064504 # number of overall hits
776system.cpu.l2cache.overall_hits::total 1087096 # number of overall hits
777system.cpu.l2cache.ReadReq_misses::cpu.inst 2426 # number of ReadReq misses
778system.cpu.l2cache.ReadReq_misses::cpu.data 406486 # number of ReadReq misses
779system.cpu.l2cache.ReadReq_misses::total 408912 # number of ReadReq misses
780system.cpu.l2cache.UpgradeReq_misses::cpu.data 4262 # number of UpgradeReq misses
781system.cpu.l2cache.UpgradeReq_misses::total 4262 # number of UpgradeReq misses
782system.cpu.l2cache.ReadExReq_misses::cpu.data 66077 # number of ReadExReq misses
783system.cpu.l2cache.ReadExReq_misses::total 66077 # number of ReadExReq misses
784system.cpu.l2cache.demand_misses::cpu.inst 2426 # number of demand (read+write) misses
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789system.cpu.l2cache.overall_misses::total 474989 # number of overall misses
790system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176218750 # number of ReadReq miss cycles

789system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.699719 # Average occupied blocks per requestor
790system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096 # Average occupied blocks per requestor
791system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 # Average percentage of cache occupancy
792system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001578 # Average percentage of cache occupancy
793system.cpu.l2cache.tags.occ_percent::cpu.data 0.955470 # Average percentage of cache occupancy
794system.cpu.l2cache.tags.occ_percent::total 0.997256 # Average percentage of cache occupancy
795system.cpu.l2cache.tags.occ_task_id_blocks::1024 32748 # Occupied blocks per task id
796system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
797system.cpu.l2cache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id
798system.cpu.l2cache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id
799system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5020 # Occupied blocks per task id
800system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26968 # Occupied blocks per task id
801system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999390 # Percentage of cache occupancy per task id
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803system.cpu.l2cache.tags.data_accesses 13848752 # Number of data accesses
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805system.cpu.l2cache.ReadReq_hits::cpu.data 1058063 # number of ReadReq hits
806system.cpu.l2cache.ReadReq_hits::total 1080655 # number of ReadReq hits
807system.cpu.l2cache.Writeback_hits::writebacks 96313 # number of Writeback hits
808system.cpu.l2cache.Writeback_hits::total 96313 # number of Writeback hits
809system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
810system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
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812system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits
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817system.cpu.l2cache.overall_hits::cpu.data 1064504 # number of overall hits
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823system.cpu.l2cache.UpgradeReq_misses::total 4262 # number of UpgradeReq misses
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793system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4757394750 # number of ReadExReq miss cycles
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837system.cpu.l2cache.demand_miss_latency::cpu.inst 176218750 # number of demand (read+write) miss cycles

796system.cpu.l2cache.demand_miss_latency::cpu.data 35503981750 # number of demand (read+write) miss cycles
797system.cpu.l2cache.demand_miss_latency::total 35680200500 # number of demand (read+write) miss cycles

838system.cpu.l2cache.demand_miss_latency::cpu.data 35503901250 # number of demand (read+write) miss cycles
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798system.cpu.l2cache.overall_miss_latency::cpu.inst 176218750 # number of overall miss cycles

840system.cpu.l2cache.overall_miss_latency::cpu.inst 176218750 # number of overall miss cycles

799system.cpu.l2cache.overall_miss_latency::cpu.data 35503981750 # number of overall miss cycles
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803system.cpu.l2cache.ReadReq_accesses::total 1489567 # number of ReadReq accesses(hits+misses)
804system.cpu.l2cache.Writeback_accesses::writebacks 96313 # number of Writeback accesses(hits+misses)
805system.cpu.l2cache.Writeback_accesses::total 96313 # number of Writeback accesses(hits+misses)
806system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4265 # number of UpgradeReq accesses(hits+misses)
807system.cpu.l2cache.UpgradeReq_accesses::total 4265 # number of UpgradeReq accesses(hits+misses)
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809system.cpu.l2cache.ReadExReq_accesses::total 72518 # number of ReadExReq accesses(hits+misses)
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817system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277550 # miss rate for ReadReq accesses
818system.cpu.l2cache.ReadReq_miss_rate::total 0.274517 # miss rate for ReadReq accesses
819system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999297 # miss rate for UpgradeReq accesses
820system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999297 # miss rate for UpgradeReq accesses
821system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911181 # miss rate for ReadExReq accesses
822system.cpu.l2cache.ReadExReq_miss_rate::total 0.911181 # miss rate for ReadExReq accesses
823system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096970 # miss rate for demand accesses
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826system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096970 # miss rate for overall accesses
827system.cpu.l2cache.overall_miss_rate::cpu.data 0.307445 # miss rate for overall accesses
828system.cpu.l2cache.overall_miss_rate::total 0.304074 # miss rate for overall accesses
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843system.cpu.l2cache.ReadReq_accesses::cpu.inst 25018 # number of ReadReq accesses(hits+misses)
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846system.cpu.l2cache.Writeback_accesses::writebacks 96313 # number of Writeback accesses(hits+misses)
847system.cpu.l2cache.Writeback_accesses::total 96313 # number of Writeback accesses(hits+misses)
848system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4265 # number of UpgradeReq accesses(hits+misses)
849system.cpu.l2cache.UpgradeReq_accesses::total 4265 # number of UpgradeReq accesses(hits+misses)
850system.cpu.l2cache.ReadExReq_accesses::cpu.data 72518 # number of ReadExReq accesses(hits+misses)
851system.cpu.l2cache.ReadExReq_accesses::total 72518 # number of ReadExReq accesses(hits+misses)
852system.cpu.l2cache.demand_accesses::cpu.inst 25018 # number of demand (read+write) accesses
853system.cpu.l2cache.demand_accesses::cpu.data 1537067 # number of demand (read+write) accesses
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855system.cpu.l2cache.overall_accesses::cpu.inst 25018 # number of overall (read+write) accesses
856system.cpu.l2cache.overall_accesses::cpu.data 1537067 # number of overall (read+write) accesses
857system.cpu.l2cache.overall_accesses::total 1562085 # number of overall (read+write) accesses
858system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.096970 # miss rate for ReadReq accesses
859system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277550 # miss rate for ReadReq accesses
860system.cpu.l2cache.ReadReq_miss_rate::total 0.274517 # miss rate for ReadReq accesses
861system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999297 # miss rate for UpgradeReq accesses
862system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999297 # miss rate for UpgradeReq accesses
863system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911181 # miss rate for ReadExReq accesses
864system.cpu.l2cache.ReadExReq_miss_rate::total 0.911181 # miss rate for ReadExReq accesses
865system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096970 # miss rate for demand accesses
866system.cpu.l2cache.demand_miss_rate::cpu.data 0.307445 # miss rate for demand accesses
867system.cpu.l2cache.demand_miss_rate::total 0.304074 # miss rate for demand accesses
868system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096970 # miss rate for overall accesses
869system.cpu.l2cache.overall_miss_rate::cpu.data 0.307445 # miss rate for overall accesses
870system.cpu.l2cache.overall_miss_rate::total 0.304074 # miss rate for overall accesses
871system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72637.572135 # average ReadReq miss latency

830system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.965460 # average ReadReq miss latency
831system.cpu.l2cache.ReadReq_avg_miss_latency::total 75622.152810 # average ReadReq miss latency

872system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.767421 # average ReadReq miss latency
873system.cpu.l2cache.ReadReq_avg_miss_latency::total 75621.955947 # average ReadReq miss latency

832system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272 # average ReadExReq miss latency
833system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272 # average ReadExReq miss latency
834system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency

874system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272 # average ReadExReq miss latency
875system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272 # average ReadExReq miss latency
876system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency

835system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency
836system.cpu.l2cache.demand_avg_miss_latency::total 75117.951153 # average overall miss latency

877system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency
878system.cpu.l2cache.demand_avg_miss_latency::total 75117.781675 # average overall miss latency

837system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency

879system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency

838system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency
839system.cpu.l2cache.overall_avg_miss_latency::total 75117.951153 # average overall miss latency

880system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency
881system.cpu.l2cache.overall_avg_miss_latency::total 75117.781675 # average overall miss latency

840system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
841system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
842system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
843system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
844system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
845system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
846system.cpu.l2cache.fast_writes 0 # number of fast writes performed
847system.cpu.l2cache.cache_copies 0 # number of cache copies performed
848system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
849system.cpu.l2cache.writebacks::total 66098 # number of writebacks
850system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
851system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
852system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits
853system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
854system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
855system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits
856system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
857system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
858system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits
859system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2424 # number of ReadReq MSHR misses
860system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406462 # number of ReadReq MSHR misses
861system.cpu.l2cache.ReadReq_mshr_misses::total 408886 # number of ReadReq MSHR misses
862system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4262 # number of UpgradeReq MSHR misses
863system.cpu.l2cache.UpgradeReq_mshr_misses::total 4262 # number of UpgradeReq MSHR misses
864system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66077 # number of ReadExReq MSHR misses
865system.cpu.l2cache.ReadExReq_mshr_misses::total 66077 # number of ReadExReq MSHR misses
866system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses
867system.cpu.l2cache.demand_mshr_misses::cpu.data 472539 # number of demand (read+write) MSHR misses
868system.cpu.l2cache.demand_mshr_misses::total 474963 # number of demand (read+write) MSHR misses
869system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses
870system.cpu.l2cache.overall_mshr_misses::cpu.data 472539 # number of overall MSHR misses
871system.cpu.l2cache.overall_mshr_misses::total 474963 # number of overall MSHR misses
872system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145637750 # number of ReadReq MSHR miss cycles

882system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
883system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
884system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
885system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
886system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
887system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
888system.cpu.l2cache.fast_writes 0 # number of fast writes performed
889system.cpu.l2cache.cache_copies 0 # number of cache copies performed
890system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
891system.cpu.l2cache.writebacks::total 66098 # number of writebacks
892system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
893system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
894system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits
895system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
896system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
897system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits
898system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
899system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
900system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits
901system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2424 # number of ReadReq MSHR misses
902system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406462 # number of ReadReq MSHR misses
903system.cpu.l2cache.ReadReq_mshr_misses::total 408886 # number of ReadReq MSHR misses
904system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4262 # number of UpgradeReq MSHR misses
905system.cpu.l2cache.UpgradeReq_mshr_misses::total 4262 # number of UpgradeReq MSHR misses
906system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66077 # number of ReadExReq MSHR misses
907system.cpu.l2cache.ReadExReq_mshr_misses::total 66077 # number of ReadExReq MSHR misses
908system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses
909system.cpu.l2cache.demand_mshr_misses::cpu.data 472539 # number of demand (read+write) MSHR misses
910system.cpu.l2cache.demand_mshr_misses::total 474963 # number of demand (read+write) MSHR misses
911system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses
912system.cpu.l2cache.overall_mshr_misses::cpu.data 472539 # number of overall MSHR misses
913system.cpu.l2cache.overall_mshr_misses::total 474963 # number of overall MSHR misses
914system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145637750 # number of ReadReq MSHR miss cycles

873system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686513500 # number of ReadReq MSHR miss cycles
874system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832151250 # number of ReadReq MSHR miss cycles

915system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686438000 # number of ReadReq MSHR miss cycles
916system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832075750 # number of ReadReq MSHR miss cycles

875system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42624262 # number of UpgradeReq MSHR miss cycles
876system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42624262 # number of UpgradeReq MSHR miss cycles
877system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924978750 # number of ReadExReq MSHR miss cycles
878system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924978750 # number of ReadExReq MSHR miss cycles
879system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145637750 # number of demand (read+write) MSHR miss cycles

917system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42624262 # number of UpgradeReq MSHR miss cycles
918system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42624262 # number of UpgradeReq MSHR miss cycles
919system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924978750 # number of ReadExReq MSHR miss cycles
920system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924978750 # number of ReadExReq MSHR miss cycles
921system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145637750 # number of demand (read+write) MSHR miss cycles

880system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611492250 # number of demand (read+write) MSHR miss cycles
881system.cpu.l2cache.demand_mshr_miss_latency::total 29757130000 # number of demand (read+write) MSHR miss cycles

922system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611416750 # number of demand (read+write) MSHR miss cycles
923system.cpu.l2cache.demand_mshr_miss_latency::total 29757054500 # number of demand (read+write) MSHR miss cycles

882system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145637750 # number of overall MSHR miss cycles

924system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145637750 # number of overall MSHR miss cycles

883system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611492250 # number of overall MSHR miss cycles
884system.cpu.l2cache.overall_mshr_miss_latency::total 29757130000 # number of overall MSHR miss cycles

925system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611416750 # number of overall MSHR miss cycles
926system.cpu.l2cache.overall_mshr_miss_latency::total 29757054500 # number of overall MSHR miss cycles

885system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for ReadReq accesses
886system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277534 # mshr miss rate for ReadReq accesses
887system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274500 # mshr miss rate for ReadReq accesses
888system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999297 # mshr miss rate for UpgradeReq accesses
889system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999297 # mshr miss rate for UpgradeReq accesses
890system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911181 # mshr miss rate for ReadExReq accesses
891system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911181 # mshr miss rate for ReadExReq accesses
892system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for demand accesses
893system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for demand accesses
894system.cpu.l2cache.demand_mshr_miss_rate::total 0.304057 # mshr miss rate for demand accesses
895system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for overall accesses
896system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for overall accesses
897system.cpu.l2cache.overall_mshr_miss_rate::total 0.304057 # mshr miss rate for overall accesses
898system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033 # average ReadReq mshr miss latency

927system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for ReadReq accesses
928system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277534 # mshr miss rate for ReadReq accesses
929system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274500 # mshr miss rate for ReadReq accesses
930system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999297 # mshr miss rate for UpgradeReq accesses
931system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999297 # mshr miss rate for UpgradeReq accesses
932system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911181 # mshr miss rate for ReadExReq accesses
933system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911181 # mshr miss rate for ReadExReq accesses
934system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for demand accesses
935system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for demand accesses
936system.cpu.l2cache.demand_mshr_miss_rate::total 0.304057 # mshr miss rate for demand accesses
937system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for overall accesses
938system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for overall accesses
939system.cpu.l2cache.overall_mshr_miss_rate::total 0.304057 # mshr miss rate for overall accesses
940system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033 # average ReadReq mshr miss latency

899system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.362666 # average ReadReq mshr miss latency
900system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.903220 # average ReadReq mshr miss latency

941system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.176917 # average ReadReq mshr miss latency
942system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.718572 # average ReadReq mshr miss latency

901system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
902system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
903system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency
904system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency
905system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency

943system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
944system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
945system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency
946system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency
947system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency

906system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency
907system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency

948system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency
949system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency

908system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency

950system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency

909system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency
910system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency

951system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency
952system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency

911system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
912system.cpu.dcache.tags.replacements 1532970 # number of replacements
913system.cpu.dcache.tags.tagsinuse 4094.376677 # Cycle average of tags in use

953system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
954system.cpu.dcache.tags.replacements 1532970 # number of replacements
955system.cpu.dcache.tags.tagsinuse 4094.376677 # Cycle average of tags in use

914system.cpu.dcache.tags.total_refs 971409274 # Total number of references to valid blocks.

956system.cpu.dcache.tags.total_refs 971409331 # Total number of references to valid blocks.

915system.cpu.dcache.tags.sampled_refs 1537066 # Sample count of references to valid blocks.

957system.cpu.dcache.tags.sampled_refs 1537066 # Sample count of references to valid blocks.

916system.cpu.dcache.tags.avg_refs 631.989306 # Average number of references to valid blocks.

958system.cpu.dcache.tags.avg_refs 631.989343 # Average number of references to valid blocks.

917system.cpu.dcache.tags.warmup_cycle 400505250 # Cycle when the warmup percentage was hit.
918system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor
919system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy
920system.cpu.dcache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy
921system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
922system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
923system.cpu.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
924system.cpu.dcache.tags.age_task_id_blocks_1024::2 977 # Occupied blocks per task id
925system.cpu.dcache.tags.age_task_id_blocks_1024::3 2409 # Occupied blocks per task id
926system.cpu.dcache.tags.age_task_id_blocks_1024::4 402 # Occupied blocks per task id
927system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

959system.cpu.dcache.tags.warmup_cycle 400505250 # Cycle when the warmup percentage was hit.
960system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor
961system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy
962system.cpu.dcache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy
963system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
964system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
965system.cpu.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
966system.cpu.dcache.tags.age_task_id_blocks_1024::2 977 # Occupied blocks per task id
967system.cpu.dcache.tags.age_task_id_blocks_1024::3 2409 # Occupied blocks per task id
968system.cpu.dcache.tags.age_task_id_blocks_1024::4 402 # Occupied blocks per task id
969system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

928system.cpu.dcache.tags.tag_accesses 1949922006 # Number of tag accesses
929system.cpu.dcache.tags.data_accesses 1949922006 # Number of data accesses
930system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits
931system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits

970system.cpu.dcache.tags.tag_accesses 1949922120 # Number of tag accesses
971system.cpu.dcache.tags.data_accesses 1949922120 # Number of data accesses
972system.cpu.dcache.ReadReq_hits::cpu.data 695282746 # number of ReadReq hits
973system.cpu.dcache.ReadReq_hits::total 695282746 # number of ReadReq hits

932system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits
933system.cpu.dcache.WriteReq_hits::total 276093049 # number of WriteReq hits
934system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits
935system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits
936system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
937system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits

974system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits
975system.cpu.dcache.WriteReq_hits::total 276093049 # number of WriteReq hits
976system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits
977system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits
978system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
979system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits

938system.cpu.dcache.demand_hits::cpu.data 971375738 # number of demand (read+write) hits
939system.cpu.dcache.demand_hits::total 971375738 # number of demand (read+write) hits
940system.cpu.dcache.overall_hits::cpu.data 971375738 # number of overall hits
941system.cpu.dcache.overall_hits::total 971375738 # number of overall hits

980system.cpu.dcache.demand_hits::cpu.data 971375795 # number of demand (read+write) hits
981system.cpu.dcache.demand_hits::total 971375795 # number of demand (read+write) hits
982system.cpu.dcache.overall_hits::cpu.data 971375795 # number of overall hits
983system.cpu.dcache.overall_hits::total 971375795 # number of overall hits

942system.cpu.dcache.ReadReq_misses::cpu.data 1954115 # number of ReadReq misses
943system.cpu.dcache.ReadReq_misses::total 1954115 # number of ReadReq misses
944system.cpu.dcache.WriteReq_misses::cpu.data 842629 # number of WriteReq misses
945system.cpu.dcache.WriteReq_misses::total 842629 # number of WriteReq misses
946system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
947system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
948system.cpu.dcache.demand_misses::cpu.data 2796744 # number of demand (read+write) misses
949system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses
950system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses
951system.cpu.dcache.overall_misses::total 2796744 # number of overall misses

984system.cpu.dcache.ReadReq_misses::cpu.data 1954115 # number of ReadReq misses
985system.cpu.dcache.ReadReq_misses::total 1954115 # number of ReadReq misses
986system.cpu.dcache.WriteReq_misses::cpu.data 842629 # number of WriteReq misses
987system.cpu.dcache.WriteReq_misses::total 842629 # number of WriteReq misses
988system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
989system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
990system.cpu.dcache.demand_misses::cpu.data 2796744 # number of demand (read+write) misses
991system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses
992system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses
993system.cpu.dcache.overall_misses::total 2796744 # number of overall misses

952system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415300557 # number of ReadReq miss cycles
953system.cpu.dcache.ReadReq_miss_latency::total 80415300557 # number of ReadReq miss cycles
954system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619884416 # number of WriteReq miss cycles
955system.cpu.dcache.WriteReq_miss_latency::total 58619884416 # number of WriteReq miss cycles

994system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415220057 # number of ReadReq miss cycles
995system.cpu.dcache.ReadReq_miss_latency::total 80415220057 # number of ReadReq miss cycles
996system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619966916 # number of WriteReq miss cycles
997system.cpu.dcache.WriteReq_miss_latency::total 58619966916 # number of WriteReq miss cycles

956system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles
957system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles

998system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles
999system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles

958system.cpu.dcache.demand_miss_latency::cpu.data 139035184973 # number of demand (read+write) miss cycles
959system.cpu.dcache.demand_miss_latency::total 139035184973 # number of demand (read+write) miss cycles
960system.cpu.dcache.overall_miss_latency::cpu.data 139035184973 # number of overall miss cycles
961system.cpu.dcache.overall_miss_latency::total 139035184973 # number of overall miss cycles
962system.cpu.dcache.ReadReq_accesses::cpu.data 697236804 # number of ReadReq accesses(hits+misses)
963system.cpu.dcache.ReadReq_accesses::total 697236804 # number of ReadReq accesses(hits+misses)

1000system.cpu.dcache.demand_miss_latency::cpu.data 139035186973 # number of demand (read+write) miss cycles
1001system.cpu.dcache.demand_miss_latency::total 139035186973 # number of demand (read+write) miss cycles
1002system.cpu.dcache.overall_miss_latency::cpu.data 139035186973 # number of overall miss cycles
1003system.cpu.dcache.overall_miss_latency::total 139035186973 # number of overall miss cycles
1004system.cpu.dcache.ReadReq_accesses::cpu.data 697236861 # number of ReadReq accesses(hits+misses)
1005system.cpu.dcache.ReadReq_accesses::total 697236861 # number of ReadReq accesses(hits+misses)

964system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
965system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
966system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses)
967system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses)
968system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
969system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)

1006system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
1007system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
1008system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses)
1009system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses)
1010system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
1011system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)

970system.cpu.dcache.demand_accesses::cpu.data 974172482 # number of demand (read+write) accesses
971system.cpu.dcache.demand_accesses::total 974172482 # number of demand (read+write) accesses
972system.cpu.dcache.overall_accesses::cpu.data 974172482 # number of overall (read+write) accesses
973system.cpu.dcache.overall_accesses::total 974172482 # number of overall (read+write) accesses

1012system.cpu.dcache.demand_accesses::cpu.data 974172539 # number of demand (read+write) accesses
1013system.cpu.dcache.demand_accesses::total 974172539 # number of demand (read+write) accesses
1014system.cpu.dcache.overall_accesses::cpu.data 974172539 # number of overall (read+write) accesses
1015system.cpu.dcache.overall_accesses::total 974172539 # number of overall (read+write) accesses

974system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses
975system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses
976system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses
977system.cpu.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses
978system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
979system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
980system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 # miss rate for demand accesses
981system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses
982system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses
983system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses

1016system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses
1017system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses
1018system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses
1019system.cpu.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses
1020system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
1021system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
1022system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 # miss rate for demand accesses
1023system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses
1024system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses
1025system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses

984system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.774874 # average ReadReq miss latency
985system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.774874 # average ReadReq miss latency
986system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.845892 # average WriteReq miss latency
987system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.845892 # average WriteReq miss latency

1026system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678 # average ReadReq miss latency
1027system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678 # average ReadReq miss latency
1028system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800 # average WriteReq miss latency
1029system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800 # average WriteReq miss latency

988system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency
989system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency

1030system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency
1031system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency

990system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency
991system.cpu.dcache.demand_avg_miss_latency::total 49713.232592 # average overall miss latency
992system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency
993system.cpu.dcache.overall_avg_miss_latency::total 49713.232592 # average overall miss latency

1032system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency
1033system.cpu.dcache.demand_avg_miss_latency::total 49713.233307 # average overall miss latency
1034system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency
1035system.cpu.dcache.overall_avg_miss_latency::total 49713.233307 # average overall miss latency

994system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked
995system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked
996system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked
997system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
998system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.557692 # average number of cycles each access was blocked
999system.cpu.dcache.avg_blocked_cycles::no_targets 10.550562 # average number of cycles each access was blocked
1000system.cpu.dcache.fast_writes 0 # number of fast writes performed
1001system.cpu.dcache.cache_copies 0 # number of cache copies performed
1002system.cpu.dcache.writebacks::writebacks 96313 # number of writebacks
1003system.cpu.dcache.writebacks::total 96313 # number of writebacks
1004system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489564 # number of ReadReq MSHR hits
1005system.cpu.dcache.ReadReq_mshr_hits::total 489564 # number of ReadReq MSHR hits
1006system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765848 # number of WriteReq MSHR hits
1007system.cpu.dcache.WriteReq_mshr_hits::total 765848 # number of WriteReq MSHR hits
1008system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
1009system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
1010system.cpu.dcache.demand_mshr_hits::cpu.data 1255412 # number of demand (read+write) MSHR hits
1011system.cpu.dcache.demand_mshr_hits::total 1255412 # number of demand (read+write) MSHR hits
1012system.cpu.dcache.overall_mshr_hits::cpu.data 1255412 # number of overall MSHR hits
1013system.cpu.dcache.overall_mshr_hits::total 1255412 # number of overall MSHR hits
1014system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464551 # number of ReadReq MSHR misses
1015system.cpu.dcache.ReadReq_mshr_misses::total 1464551 # number of ReadReq MSHR misses
1016system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76781 # number of WriteReq MSHR misses
1017system.cpu.dcache.WriteReq_mshr_misses::total 76781 # number of WriteReq MSHR misses
1018system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 # number of demand (read+write) MSHR misses
1019system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses
1020system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses
1021system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses

1036system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked
1037system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked
1038system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked
1039system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
1040system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.557692 # average number of cycles each access was blocked
1041system.cpu.dcache.avg_blocked_cycles::no_targets 10.550562 # average number of cycles each access was blocked
1042system.cpu.dcache.fast_writes 0 # number of fast writes performed
1043system.cpu.dcache.cache_copies 0 # number of cache copies performed
1044system.cpu.dcache.writebacks::writebacks 96313 # number of writebacks
1045system.cpu.dcache.writebacks::total 96313 # number of writebacks
1046system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489564 # number of ReadReq MSHR hits
1047system.cpu.dcache.ReadReq_mshr_hits::total 489564 # number of ReadReq MSHR hits
1048system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765848 # number of WriteReq MSHR hits
1049system.cpu.dcache.WriteReq_mshr_hits::total 765848 # number of WriteReq MSHR hits
1050system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
1051system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
1052system.cpu.dcache.demand_mshr_hits::cpu.data 1255412 # number of demand (read+write) MSHR hits
1053system.cpu.dcache.demand_mshr_hits::total 1255412 # number of demand (read+write) MSHR hits
1054system.cpu.dcache.overall_mshr_hits::cpu.data 1255412 # number of overall MSHR hits
1055system.cpu.dcache.overall_mshr_hits::total 1255412 # number of overall MSHR hits
1056system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464551 # number of ReadReq MSHR misses
1057system.cpu.dcache.ReadReq_mshr_misses::total 1464551 # number of ReadReq MSHR misses
1058system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76781 # number of WriteReq MSHR misses
1059system.cpu.dcache.WriteReq_mshr_misses::total 76781 # number of WriteReq MSHR misses
1060system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 # number of demand (read+write) MSHR misses
1061system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses
1062system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses
1063system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses

1022system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles
1023system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles

1064system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792151524 # number of ReadReq MSHR miss cycles
1065system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792151524 # number of ReadReq MSHR miss cycles

1024system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles
1025system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles

1066system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles
1067system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles

1026system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles
1027system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles
1028system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles
1029system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles

1068system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785646012 # number of demand (read+write) MSHR miss cycles
1069system.cpu.dcache.demand_mshr_miss_latency::total 47785646012 # number of demand (read+write) MSHR miss cycles
1070system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785646012 # number of overall MSHR miss cycles
1071system.cpu.dcache.overall_mshr_miss_latency::total 47785646012 # number of overall MSHR miss cycles

1030system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses
1031system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses
1032system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
1033system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
1034system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for demand accesses
1035system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses
1036system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses
1037system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses

1072system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses
1073system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses
1074system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
1075system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
1076system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for demand accesses
1077system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses
1078system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses
1079system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses

1038system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency
1039system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency

1080system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800 # average ReadReq mshr miss latency
1081system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800 # average ReadReq mshr miss latency

1040system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency
1041system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency

1082system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency
1083system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency

1042system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
1043system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency
1044system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
1045system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency

1084system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency
1085system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency
1086system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency
1087system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency