1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.339069 # Number of seconds simulated
4sim_ticks 339069355000 # Number of ticks simulated
5final_tick 339069355000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 212003 # Simulator instruction rate (inst/s)
8host_op_rate 261004 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 112204360 # Simulator tick rate (ticks/s)
10host_mem_usage 277184 # Number of bytes of host memory used
11host_seconds 3021.89 # Real time elapsed on the host
12sim_insts 640649299 # Number of instructions simulated
13sim_ops 788724958 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 272000 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 48065856 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.l2cache.prefetcher 12979392 # Number of bytes read from this memory
20system.physmem.bytes_read::total 61317248 # Number of bytes read from this memory
21system.physmem.bytes_inst_read::cpu.inst 272000 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 272000 # Number of instructions bytes read from this memory
23system.physmem.bytes_written::writebacks 4246400 # Number of bytes written to this memory
24system.physmem.bytes_written::total 4246400 # Number of bytes written to this memory
25system.physmem.num_reads::cpu.inst 4250 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 751029 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.l2cache.prefetcher 202803 # Number of read requests responded to by this memory
28system.physmem.num_reads::total 958082 # Number of read requests responded to by this memory
29system.physmem.num_writes::writebacks 66350 # Number of write requests responded to by this memory
30system.physmem.num_writes::total 66350 # Number of write requests responded to by this memory
31system.physmem.bw_read::cpu.inst 802196 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.data 141758184 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.l2cache.prefetcher 38279461 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::total 180839840 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::cpu.inst 802196 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::total 802196 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_write::writebacks 12523692 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_write::total 12523692 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_total::writebacks 12523692 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.inst 802196 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.data 141758184 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::cpu.l2cache.prefetcher 38279461 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::total 193363532 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.readReqs 958083 # Number of read requests accepted
45system.physmem.writeReqs 66350 # Number of write requests accepted
46system.physmem.readBursts 958083 # Number of DRAM read bursts, including those serviced by the write queue
47system.physmem.writeBursts 66350 # Number of DRAM write bursts, including those merged in the write queue
48system.physmem.bytesReadDRAM 61296960 # Total number of bytes read from DRAM
49system.physmem.bytesReadWrQ 20352 # Total number of bytes read from write queue
50system.physmem.bytesWritten 4240000 # Total number of bytes written to DRAM
51system.physmem.bytesReadSys 61317312 # Total read bytes from the system interface side
52system.physmem.bytesWrittenSys 4246400 # Total written bytes from the system interface side
53system.physmem.servicedByWrQ 318 # Number of DRAM read bursts serviced by the write queue
54system.physmem.mergedWrBursts 71 # Number of DRAM write bursts merged with an existing one
55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
56system.physmem.perBankRdBursts::0 19910 # Per bank write bursts
57system.physmem.perBankRdBursts::1 19573 # Per bank write bursts
58system.physmem.perBankRdBursts::2 657828 # Per bank write bursts
59system.physmem.perBankRdBursts::3 21032 # Per bank write bursts
60system.physmem.perBankRdBursts::4 19718 # Per bank write bursts
61system.physmem.perBankRdBursts::5 21045 # Per bank write bursts
62system.physmem.perBankRdBursts::6 19700 # Per bank write bursts
63system.physmem.perBankRdBursts::7 20038 # Per bank write bursts
64system.physmem.perBankRdBursts::8 19491 # Per bank write bursts
65system.physmem.perBankRdBursts::9 20101 # Per bank write bursts
66system.physmem.perBankRdBursts::10 19540 # Per bank write bursts
67system.physmem.perBankRdBursts::11 19692 # Per bank write bursts
68system.physmem.perBankRdBursts::12 19618 # Per bank write bursts
69system.physmem.perBankRdBursts::13 21105 # Per bank write bursts
70system.physmem.perBankRdBursts::14 19493 # Per bank write bursts
71system.physmem.perBankRdBursts::15 19881 # Per bank write bursts
72system.physmem.perBankWrBursts::0 4272 # Per bank write bursts
73system.physmem.perBankWrBursts::1 4107 # Per bank write bursts
74system.physmem.perBankWrBursts::2 4147 # Per bank write bursts
75system.physmem.perBankWrBursts::3 4153 # Per bank write bursts
76system.physmem.perBankWrBursts::4 4251 # Per bank write bursts
77system.physmem.perBankWrBursts::5 4229 # Per bank write bursts
78system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
79system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
80system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
81system.physmem.perBankWrBursts::9 4095 # Per bank write bursts
82system.physmem.perBankWrBursts::10 4095 # Per bank write bursts
83system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
84system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
85system.physmem.perBankWrBursts::13 4094 # Per bank write bursts
86system.physmem.perBankWrBursts::14 4095 # Per bank write bursts
87system.physmem.perBankWrBursts::15 4151 # Per bank write bursts
88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
90system.physmem.totGap 339069344500 # Total gap between requests
91system.physmem.readPktSize::0 0 # Read request sizes (log2)
92system.physmem.readPktSize::1 0 # Read request sizes (log2)
93system.physmem.readPktSize::2 0 # Read request sizes (log2)
94system.physmem.readPktSize::3 0 # Read request sizes (log2)
95system.physmem.readPktSize::4 0 # Read request sizes (log2)
96system.physmem.readPktSize::5 0 # Read request sizes (log2)
97system.physmem.readPktSize::6 958083 # Read request sizes (log2)
98system.physmem.writePktSize::0 0 # Write request sizes (log2)
99system.physmem.writePktSize::1 0 # Write request sizes (log2)
100system.physmem.writePktSize::2 0 # Write request sizes (log2)
101system.physmem.writePktSize::3 0 # Write request sizes (log2)
102system.physmem.writePktSize::4 0 # Write request sizes (log2)
103system.physmem.writePktSize::5 0 # Write request sizes (log2)
104system.physmem.writePktSize::6 66350 # Write request sizes (log2)
105system.physmem.rdQLenPdf::0 765133 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::1 120601 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::2 15570 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::3 6690 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::4 6457 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::5 7738 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::6 9158 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::7 10207 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::8 6741 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::9 3672 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::10 2435 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::11 1581 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::12 1116 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::13 666 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
137system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::15 511 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::16 556 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::17 857 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::18 1405 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::19 2061 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::20 2611 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::21 3025 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::22 3538 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::23 4041 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::24 4482 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::25 4954 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::26 5339 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::27 5747 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::28 6156 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::29 6357 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::30 4787 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::31 4236 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::32 4138 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::33 191 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::34 168 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::35 135 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::36 120 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::38 89 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::39 84 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::40 75 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::41 73 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::44 51 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::45 45 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::47 32 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::48 26 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::49 29 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
201system.physmem.bytesPerActivate::samples 196319 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::mean 333.816859 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::gmean 191.183939 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::stdev 355.380336 # Bytes accessed per row activation
205system.physmem.bytesPerActivate::0-127 65406 33.32% 33.32% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::128-255 61086 31.12% 64.43% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::256-383 15476 7.88% 72.31% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::384-511 3179 1.62% 73.93% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::512-639 3479 1.77% 75.71% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::640-767 2336 1.19% 76.90% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::768-895 2511 1.28% 78.18% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::896-1023 34323 17.48% 95.66% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::1024-1151 8523 4.34% 100.00% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::total 196319 # Bytes accessed per row activation
215system.physmem.rdPerTurnAround::samples 4003 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::mean 214.941294 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::gmean 35.155298 # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::stdev 2727.024521 # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::0-4095 3978 99.38% 99.38% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.68% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.75% # Reads before turning the bus around for writes
222system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.85% # Reads before turning the bus around for writes
223system.physmem.rdPerTurnAround::16384-20479 1 0.02% 99.88% # Reads before turning the bus around for writes
224system.physmem.rdPerTurnAround::32768-36863 1 0.02% 99.90% # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::36864-40959 1 0.02% 99.93% # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::69632-73727 1 0.02% 99.98% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::126976-131071 1 0.02% 100.00% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::total 4003 # Reads before turning the bus around for writes
230system.physmem.wrPerTurnAround::samples 4003 # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::mean 16.550087 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::gmean 16.475287 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::stdev 1.816460 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::16 3400 84.94% 84.94% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::17 19 0.47% 85.41% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::18 373 9.32% 94.73% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::19 54 1.35% 96.08% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::20 20 0.50% 96.58% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::21 27 0.67% 97.25% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::22 15 0.37% 97.63% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::23 21 0.52% 98.15% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::24 14 0.35% 98.50% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::25 14 0.35% 98.85% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::26 14 0.35% 99.20% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::27 6 0.15% 99.35% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::28 7 0.17% 99.53% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::29 6 0.15% 99.68% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::30 1 0.02% 99.70% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::31 3 0.07% 99.78% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::32 4 0.10% 99.88% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::33 1 0.02% 99.90% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::34 2 0.05% 99.95% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::35 1 0.02% 99.98% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::38 1 0.02% 100.00% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::total 4003 # Writes before turning the bus around for reads
256system.physmem.totQLat 27518767878 # Total ticks spent queuing
257system.physmem.totMemAccLat 45476861628 # Total ticks spent from burst creation until serviced by the DRAM
258system.physmem.totBusLat 4788825000 # Total ticks spent in databus transfers
259system.physmem.avgQLat 28732.28 # Average queueing delay per DRAM burst
260system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
261system.physmem.avgMemAccLat 47482.28 # Average memory access latency per DRAM burst
262system.physmem.avgRdBW 180.78 # Average DRAM read bandwidth in MiByte/s
263system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s
264system.physmem.avgRdBWSys 180.84 # Average system read bandwidth in MiByte/s
265system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s
266system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
267system.physmem.busUtil 1.51 # Data bus utilization in percentage
268system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads
269system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes
270system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
271system.physmem.avgWrQLen 25.37 # Average write queue length when enqueuing
272system.physmem.readRowHits 804881 # Number of row buffer hits during reads
273system.physmem.writeRowHits 22802 # Number of row buffer hits during writes
274system.physmem.readRowHitRate 84.04 # Row buffer hit rate for reads
275system.physmem.writeRowHitRate 34.40 # Row buffer hit rate for writes
276system.physmem.avgGap 330982.45 # Average gap between requests
277system.physmem.pageHitRate 80.82 # Row buffer hit rate, read and write combined
278system.physmem_0.actEnergy 901474980 # Energy for activate commands per rank (pJ)
279system.physmem_0.preEnergy 479122545 # Energy for precharge commands per rank (pJ)
280system.physmem_0.readEnergy 5703739020 # Energy for read commands per rank (pJ)
281system.physmem_0.writeEnergy 174499380 # Energy for write commands per rank (pJ)
282system.physmem_0.refreshEnergy 27325665120.000008 # Energy for refresh commands per rank (pJ)
283system.physmem_0.actBackEnergy 14491103160 # Energy for active background per rank (pJ)
284system.physmem_0.preBackEnergy 673386240 # Energy for precharge background per rank (pJ)
285system.physmem_0.actPowerDownEnergy 138371323560 # Energy for active power-down per rank (pJ)
286system.physmem_0.prePowerDownEnergy 679220160 # Energy for precharge power-down per rank (pJ)
287system.physmem_0.selfRefreshEnergy 661319340.000000 # Energy for self refresh per rank (pJ)
288system.physmem_0.totalEnergy 189506984115 # Total energy per rank (pJ)
289system.physmem_0.averagePower 558.903308 # Core power per rank (mW)
290system.physmem_0.totalIdleTime 305432505529 # Total Idle time Per DRAM Rank
291system.physmem_0.memoryStateTime::IDLE 523884278 # Time in different power states
292system.physmem_0.memoryStateTime::REF 11566244000 # Time in different power states
293system.physmem_0.memoryStateTime::SREF 219111500 # Time in different power states
294system.physmem_0.memoryStateTime::PRE_PDN 1768844578 # Time in different power states
295system.physmem_0.memoryStateTime::ACT 21546721193 # Time in different power states
296system.physmem_0.memoryStateTime::ACT_PDN 303444549451 # Time in different power states
297system.physmem_1.actEnergy 500335500 # Energy for activate commands per rank (pJ)
298system.physmem_1.preEnergy 265908060 # Energy for precharge commands per rank (pJ)
299system.physmem_1.readEnergy 1134695940 # Energy for read commands per rank (pJ)
300system.physmem_1.writeEnergy 171325620 # Energy for write commands per rank (pJ)
301system.physmem_1.refreshEnergy 25432573920.000004 # Energy for refresh commands per rank (pJ)
302system.physmem_1.actBackEnergy 6980276430 # Energy for active background per rank (pJ)
303system.physmem_1.preBackEnergy 1364879040 # Energy for precharge background per rank (pJ)
304system.physmem_1.actPowerDownEnergy 70621447890 # Energy for active power-down per rank (pJ)
305system.physmem_1.prePowerDownEnergy 30989177760 # Energy for precharge power-down per rank (pJ)
306system.physmem_1.selfRefreshEnergy 25472740305 # Energy for self refresh per rank (pJ)
307system.physmem_1.totalEnergy 162933984825 # Total energy per rank (pJ)
308system.physmem_1.averagePower 480.532913 # Core power per rank (mW)
309system.physmem_1.totalIdleTime 320205691246 # Total Idle time Per DRAM Rank
310system.physmem_1.memoryStateTime::IDLE 2610959521 # Time in different power states
311system.physmem_1.memoryStateTime::REF 10814464000 # Time in different power states
312system.physmem_1.memoryStateTime::SREF 84633345250 # Time in different power states
313system.physmem_1.memoryStateTime::PRE_PDN 80700935022 # Time in different power states
314system.physmem_1.memoryStateTime::ACT 5438217483 # Time in different power states
315system.physmem_1.memoryStateTime::ACT_PDN 154871433724 # Time in different power states
316system.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
317system.cpu.branchPred.lookups 175312537 # Number of BP lookups
318system.cpu.branchPred.condPredicted 119126010 # Number of conditional branches predicted
319system.cpu.branchPred.condIncorrect 4023429 # Number of conditional branches incorrect
320system.cpu.branchPred.BTBLookups 95987051 # Number of BTB lookups
321system.cpu.branchPred.BTBHits 67762694 # Number of BTB hits
322system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
323system.cpu.branchPred.BTBHitPct 70.595662 # BTB Hit Percentage
324system.cpu.branchPred.usedRAS 18784914 # Number of times the RAS was used to get a target.
325system.cpu.branchPred.RASInCorrect 1299715 # Number of incorrect RAS predictions.
326system.cpu.branchPred.indirectLookups 16714738 # Number of indirect predictor lookups.
327system.cpu.branchPred.indirectHits 16702890 # Number of indirect target hits.
328system.cpu.branchPred.indirectMisses 11848 # Number of indirect misses.
329system.cpu.branchPredindirectMispredicted 1279488 # Number of mispredicted indirect branches.
330system.cpu_clk_domain.clock 500 # Clock period in ticks
331system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
332system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
333system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
334system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
335system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
336system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
337system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
338system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
339system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
340system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
341system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
342system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
343system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
344system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
345system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
346system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
347system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
348system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
349system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
350system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
351system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
352system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
353system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
354system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
355system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
356system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
357system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
358system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
359system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
360system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
361system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
362system.cpu.dtb.walker.walks 0 # Table walker walks requested
363system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
364system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
365system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
366system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
367system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
368system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
369system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
370system.cpu.dtb.inst_hits 0 # ITB inst hits
371system.cpu.dtb.inst_misses 0 # ITB inst misses
372system.cpu.dtb.read_hits 0 # DTB read hits
373system.cpu.dtb.read_misses 0 # DTB read misses
374system.cpu.dtb.write_hits 0 # DTB write hits
375system.cpu.dtb.write_misses 0 # DTB write misses
376system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
377system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
378system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
379system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
380system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
381system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
382system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
383system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
384system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
385system.cpu.dtb.read_accesses 0 # DTB read accesses
386system.cpu.dtb.write_accesses 0 # DTB write accesses
387system.cpu.dtb.inst_accesses 0 # ITB inst accesses
388system.cpu.dtb.hits 0 # DTB hits
389system.cpu.dtb.misses 0 # DTB misses
390system.cpu.dtb.accesses 0 # DTB accesses
391system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
392system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
393system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
394system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
395system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
396system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
397system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
398system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
399system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
400system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
401system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
402system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
403system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
404system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
405system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
406system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
407system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
408system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
409system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
410system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
411system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
412system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
413system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
414system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
415system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
416system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
417system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
418system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
419system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
420system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
421system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
422system.cpu.itb.walker.walks 0 # Table walker walks requested
423system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
424system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
425system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
426system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
427system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
428system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
429system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
430system.cpu.itb.inst_hits 0 # ITB inst hits
431system.cpu.itb.inst_misses 0 # ITB inst misses
432system.cpu.itb.read_hits 0 # DTB read hits
433system.cpu.itb.read_misses 0 # DTB read misses
434system.cpu.itb.write_hits 0 # DTB write hits
435system.cpu.itb.write_misses 0 # DTB write misses
436system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
437system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
438system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
439system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
440system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
441system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
442system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
443system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
444system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
445system.cpu.itb.read_accesses 0 # DTB read accesses
446system.cpu.itb.write_accesses 0 # DTB write accesses
447system.cpu.itb.inst_accesses 0 # ITB inst accesses
448system.cpu.itb.hits 0 # DTB hits
449system.cpu.itb.misses 0 # DTB misses
450system.cpu.itb.accesses 0 # DTB accesses
451system.cpu.workload.num_syscalls 673 # Number of system calls
452system.cpu.pwrStateResidencyTicks::ON 339069355000 # Cumulative time (in ticks) in various power states
453system.cpu.numCycles 678138711 # number of cpu cycles simulated
454system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
455system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
456system.cpu.fetch.icacheStallCycles 35026134 # Number of cycles fetch is stalled on an Icache miss
457system.cpu.fetch.Insts 824295259 # Number of instructions fetch has processed
458system.cpu.fetch.Branches 175312537 # Number of branches that fetch encountered
459system.cpu.fetch.predictedBranches 103250498 # Number of branches that fetch has predicted taken
460system.cpu.fetch.Cycles 638595633 # Number of cycles fetch has run and was not squashing or blocked
461system.cpu.fetch.SquashCycles 8083491 # Number of cycles fetch has spent squashing
462system.cpu.fetch.MiscStallCycles 2728 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
463system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps
464system.cpu.fetch.IcacheWaitRetryStallCycles 3109 # Number of stall cycles due to full MSHR
465system.cpu.fetch.CacheLines 247757876 # Number of cache lines fetched
466system.cpu.fetch.IcacheSquashes 12590 # Number of outstanding Icache misses that were squashed
467system.cpu.fetch.rateDist::samples 677669366 # Number of instructions fetched each cycle (Total)
468system.cpu.fetch.rateDist::mean 1.498301 # Number of instructions fetched each cycle (Total)
469system.cpu.fetch.rateDist::stdev 1.263018 # Number of instructions fetched each cycle (Total)
470system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
471system.cpu.fetch.rateDist::0 215620652 31.82% 31.82% # Number of instructions fetched each cycle (Total)
472system.cpu.fetch.rateDist::1 148930568 21.98% 53.79% # Number of instructions fetched each cycle (Total)
473system.cpu.fetch.rateDist::2 72932404 10.76% 64.56% # Number of instructions fetched each cycle (Total)
474system.cpu.fetch.rateDist::3 240185742 35.44% 100.00% # Number of instructions fetched each cycle (Total)
475system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
476system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
477system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
478system.cpu.fetch.rateDist::total 677669366 # Number of instructions fetched each cycle (Total)
479system.cpu.fetch.branchRate 0.258520 # Number of branch fetches per cycle
480system.cpu.fetch.rate 1.215526 # Number of inst fetches per cycle
481system.cpu.decode.IdleCycles 75794919 # Number of cycles decode is idle
482system.cpu.decode.BlockedCycles 258105460 # Number of cycles decode is blocked
483system.cpu.decode.RunCycles 277738151 # Number of cycles decode is running
484system.cpu.decode.UnblockCycles 62003234 # Number of cycles decode is unblocking
485system.cpu.decode.SquashCycles 4027602 # Number of cycles decode is squashing
486system.cpu.decode.BranchResolved 64856939 # Number of times decode resolved a branch
487system.cpu.decode.BranchMispred 14426 # Number of times decode detected a branch misprediction
488system.cpu.decode.DecodedInsts 924580293 # Number of instructions handled by decode
489system.cpu.decode.SquashedInsts 10545635 # Number of squashed instructions handled by decode
490system.cpu.rename.SquashCycles 4027602 # Number of cycles rename is squashing
491system.cpu.rename.IdleCycles 118744370 # Number of cycles rename is idle
492system.cpu.rename.BlockCycles 157469679 # Number of cycles rename is blocking
493system.cpu.rename.serializeStallCycles 209680 # count of cycles rename stalled for serializing inst
494system.cpu.rename.RunCycles 295125429 # Number of cycles rename is running
495system.cpu.rename.UnblockCycles 102092606 # Number of cycles rename is unblocking
496system.cpu.rename.RenamedInsts 906546743 # Number of instructions processed by rename
497system.cpu.rename.SquashedInsts 6881182 # Number of squashed instructions processed by rename
498system.cpu.rename.ROBFullEvents 27980774 # Number of times rename has blocked due to ROB full
499system.cpu.rename.IQFullEvents 2218296 # Number of times rename has blocked due to IQ full
500system.cpu.rename.LQFullEvents 49244088 # Number of times rename has blocked due to LQ full
501system.cpu.rename.SQFullEvents 491152 # Number of times rename has blocked due to SQ full
502system.cpu.rename.RenamedOperands 980952632 # Number of destination operands rename has renamed
503system.cpu.rename.RenameLookups 4318034270 # Number of register rename lookups that rename has made
504system.cpu.rename.int_rename_lookups 1001843328 # Number of integer rename lookups
505system.cpu.rename.fp_rename_lookups 34457465 # Number of floating rename lookups
506system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed
507system.cpu.rename.UndoneMaps 106174402 # Number of HB maps that are undone due to squashing
508system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed
509system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed
510system.cpu.rename.skidInsts 138250974 # count of insts added to the skid buffer
511system.cpu.memDep0.insertedLoads 271864033 # Number of loads inserted to the mem dependence unit.
512system.cpu.memDep0.insertedStores 160594184 # Number of stores inserted to the mem dependence unit.
513system.cpu.memDep0.conflictingLoads 6150346 # Number of conflicting loads.
514system.cpu.memDep0.conflictingStores 12039275 # Number of conflicting stores.
515system.cpu.iq.iqInstsAdded 899826395 # Number of instructions added to the IQ (excludes non-spec)
516system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ
517system.cpu.iq.iqInstsIssued 860048195 # Number of instructions issued
518system.cpu.iq.iqSquashedInstsIssued 9222152 # Number of squashed instructions issued
519system.cpu.iq.iqSquashedInstsExamined 111114019 # Number of squashed instructions iterated over during squash; mainly for profiling
520system.cpu.iq.iqSquashedOperandsExamined 244270336 # Number of squashed operands that are examined and possibly removed from graph
521system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed
522system.cpu.iq.issued_per_cycle::samples 677669366 # Number of insts issued each cycle
523system.cpu.iq.issued_per_cycle::mean 1.269127 # Number of insts issued each cycle
524system.cpu.iq.issued_per_cycle::stdev 1.103925 # Number of insts issued each cycle
525system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
526system.cpu.iq.issued_per_cycle::0 215576710 31.81% 31.81% # Number of insts issued each cycle
527system.cpu.iq.issued_per_cycle::1 182398349 26.92% 58.73% # Number of insts issued each cycle
528system.cpu.iq.issued_per_cycle::2 173866168 25.66% 84.38% # Number of insts issued each cycle
529system.cpu.iq.issued_per_cycle::3 93397486 13.78% 98.17% # Number of insts issued each cycle
530system.cpu.iq.issued_per_cycle::4 12428213 1.83% 100.00% # Number of insts issued each cycle
531system.cpu.iq.issued_per_cycle::5 2440 0.00% 100.00% # Number of insts issued each cycle
532system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
533system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
534system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
535system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
536system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
537system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
538system.cpu.iq.issued_per_cycle::total 677669366 # Number of insts issued each cycle
539system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
540system.cpu.iq.fu_full::IntAlu 66592795 23.99% 23.99% # attempts to use FU when none available
541system.cpu.iq.fu_full::IntMult 18143 0.01% 23.99% # attempts to use FU when none available
542system.cpu.iq.fu_full::IntDiv 0 0.00% 23.99% # attempts to use FU when none available
543system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.99% # attempts to use FU when none available
544system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.99% # attempts to use FU when none available
545system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.99% # attempts to use FU when none available
546system.cpu.iq.fu_full::FloatMult 0 0.00% 23.99% # attempts to use FU when none available
547system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 23.99% # attempts to use FU when none available
548system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.99% # attempts to use FU when none available
549system.cpu.iq.fu_full::FloatMisc 0 0.00% 23.99% # attempts to use FU when none available
550system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.99% # attempts to use FU when none available
551system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.99% # attempts to use FU when none available
552system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.99% # attempts to use FU when none available
553system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.99% # attempts to use FU when none available
554system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.99% # attempts to use FU when none available
555system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.99% # attempts to use FU when none available
556system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.99% # attempts to use FU when none available
557system.cpu.iq.fu_full::SimdMult 0 0.00% 23.99% # attempts to use FU when none available
558system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.99% # attempts to use FU when none available
559system.cpu.iq.fu_full::SimdShift 0 0.00% 23.99% # attempts to use FU when none available
560system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.99% # attempts to use FU when none available
561system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.99% # attempts to use FU when none available
562system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.99% # attempts to use FU when none available
563system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.99% # attempts to use FU when none available
564system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.99% # attempts to use FU when none available
565system.cpu.iq.fu_full::SimdFloatCvt 636888 0.23% 24.22% # attempts to use FU when none available
566system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.22% # attempts to use FU when none available
567system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.22% # attempts to use FU when none available
568system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.22% # attempts to use FU when none available
569system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.22% # attempts to use FU when none available
570system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.22% # attempts to use FU when none available
571system.cpu.iq.fu_full::MemRead 132895197 47.87% 72.10% # attempts to use FU when none available
572system.cpu.iq.fu_full::MemWrite 66486163 23.95% 96.04% # attempts to use FU when none available
573system.cpu.iq.fu_full::FloatMemRead 5670687 2.04% 98.09% # attempts to use FU when none available
574system.cpu.iq.fu_full::FloatMemWrite 5308776 1.91% 100.00% # attempts to use FU when none available
575system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
576system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
577system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
578system.cpu.iq.FU_type_0::IntAlu 413112342 48.03% 48.03% # Type of FU issued
579system.cpu.iq.FU_type_0::IntMult 5187450 0.60% 48.64% # Type of FU issued
580system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued
581system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued
582system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued
583system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued
584system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued
585system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 48.64% # Type of FU issued
586system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued
587system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 48.64% # Type of FU issued
588system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued
589system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued
590system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued
591system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued
592system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued
593system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued
594system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued
595system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued
596system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued
597system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued
598system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued
599system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued
600system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued
601system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued
602system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.37% 49.08% # Type of FU issued
603system.cpu.iq.FU_type_0::SimdFloatCvt 2550158 0.30% 49.38% # Type of FU issued
604system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued
605system.cpu.iq.FU_type_0::SimdFloatMisc 11478201 1.33% 50.71% # Type of FU issued
606system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued
607system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued
608system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued
609system.cpu.iq.FU_type_0::MemRead 259635092 30.19% 80.90% # Type of FU issued
610system.cpu.iq.FU_type_0::MemWrite 153408617 17.84% 98.74% # Type of FU issued
611system.cpu.iq.FU_type_0::FloatMemRead 7019173 0.82% 99.55% # Type of FU issued
612system.cpu.iq.FU_type_0::FloatMemWrite 3831959 0.45% 100.00% # Type of FU issued
613system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
614system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
615system.cpu.iq.FU_type_0::total 860048195 # Type of FU issued
616system.cpu.iq.rate 1.268248 # Inst issue rate
617system.cpu.iq.fu_busy_cnt 277608649 # FU busy when requested
618system.cpu.iq.fu_busy_rate 0.322783 # FU busy rate (busy events/executed inst)
619system.cpu.iq.int_inst_queue_reads 2621941266 # Number of integer instruction queue reads
620system.cpu.iq.int_inst_queue_writes 980329396 # Number of integer instruction queue writes
621system.cpu.iq.int_inst_queue_wakeup_accesses 820105906 # Number of integer instruction queue wakeup accesses
622system.cpu.iq.fp_inst_queue_reads 62655291 # Number of floating instruction queue reads
623system.cpu.iq.fp_inst_queue_writes 30642249 # Number of floating instruction queue writes
624system.cpu.iq.fp_inst_queue_wakeup_accesses 24878687 # Number of floating instruction queue wakeup accesses
625system.cpu.iq.int_alu_accesses 1100523479 # Number of integer alu accesses
626system.cpu.iq.fp_alu_accesses 37133365 # Number of floating point alu accesses
627system.cpu.iew.lsq.thread0.forwLoads 13978556 # Number of loads that had data forwarded from stores
628system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
629system.cpu.iew.lsq.thread0.squashedLoads 19623095 # Number of loads squashed
630system.cpu.iew.lsq.thread0.ignoredResponses 150 # Number of memory responses ignored because the instruction is squashed
631system.cpu.iew.lsq.thread0.memOrderViolation 18653 # Number of memory ordering violations
632system.cpu.iew.lsq.thread0.squashedStores 31613688 # Number of stores squashed
633system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
634system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
635system.cpu.iew.lsq.thread0.rescheduledLoads 1918749 # Number of loads that were rescheduled
636system.cpu.iew.lsq.thread0.cacheBlocked 18225 # Number of times an access to memory failed due to the cache being blocked
637system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
638system.cpu.iew.iewSquashCycles 4027602 # Number of cycles IEW is squashing
639system.cpu.iew.iewBlockCycles 10592950 # Number of cycles IEW is blocking
640system.cpu.iew.iewUnblockCycles 5943 # Number of cycles IEW is unblocking
641system.cpu.iew.iewDispatchedInsts 899848973 # Number of instructions dispatched to IQ
642system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
643system.cpu.iew.iewDispLoadInsts 271864033 # Number of dispatched load instructions
644system.cpu.iew.iewDispStoreInsts 160594184 # Number of dispatched store instructions
645system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions
646system.cpu.iew.iewIQFullEvents 932 # Number of times the IQ has become full, causing a stall
647system.cpu.iew.iewLSQFullEvents 3107 # Number of times the LSQ has become full, causing a stall
648system.cpu.iew.memOrderViolationEvents 18653 # Number of memory order violations
649system.cpu.iew.predictedTakenIncorrect 3297561 # Number of branches that were predicted taken incorrectly
650system.cpu.iew.predictedNotTakenIncorrect 3294434 # Number of branches that were predicted not taken incorrectly
651system.cpu.iew.branchMispredicts 6591995 # Number of branch mispredicts detected at execute
652system.cpu.iew.iewExecutedInsts 850188945 # Number of executed instructions
653system.cpu.iew.iewExecLoadInsts 263367686 # Number of load instructions executed
654system.cpu.iew.iewExecSquashedInsts 9859250 # Number of squashed instructions skipped in execute
655system.cpu.iew.exec_swp 0 # number of swp insts executed
656system.cpu.iew.exec_nop 9996 # number of nop insts executed
657system.cpu.iew.exec_refs 416059985 # number of memory reference insts executed
658system.cpu.iew.exec_branches 143387028 # Number of branches executed
659system.cpu.iew.exec_stores 152692299 # Number of stores executed
660system.cpu.iew.exec_rate 1.253710 # Inst execution rate
661system.cpu.iew.wb_sent 846316526 # cumulative count of insts sent to commit
662system.cpu.iew.wb_count 844984593 # cumulative count of insts written-back
663system.cpu.iew.wb_producers 486213090 # num instructions producing a value
664system.cpu.iew.wb_consumers 804713496 # num instructions consuming a value
665system.cpu.iew.wb_rate 1.246035 # insts written-back per cycle
666system.cpu.iew.wb_fanout 0.604206 # average fanout of values written-back
667system.cpu.commit.commitSquashedInsts 103170323 # The number of squashed insts skipped by commit
668system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards
669system.cpu.commit.branchMispredicts 4009286 # The number of times a branch was mispredicted
670system.cpu.commit.committed_per_cycle::samples 663080037 # Number of insts commited each cycle
671system.cpu.commit.committed_per_cycle::mean 1.189495 # Number of insts commited each cycle
672system.cpu.commit.committed_per_cycle::stdev 2.047357 # Number of insts commited each cycle
673system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
674system.cpu.commit.committed_per_cycle::0 372743600 56.21% 56.21% # Number of insts commited each cycle
675system.cpu.commit.committed_per_cycle::1 137229465 20.70% 76.91% # Number of insts commited each cycle
676system.cpu.commit.committed_per_cycle::2 51343947 7.74% 84.65% # Number of insts commited each cycle
677system.cpu.commit.committed_per_cycle::3 28225650 4.26% 88.91% # Number of insts commited each cycle
678system.cpu.commit.committed_per_cycle::4 14387181 2.17% 91.08% # Number of insts commited each cycle
679system.cpu.commit.committed_per_cycle::5 14772519 2.23% 93.31% # Number of insts commited each cycle
680system.cpu.commit.committed_per_cycle::6 7871150 1.19% 94.49% # Number of insts commited each cycle
681system.cpu.commit.committed_per_cycle::7 6554658 0.99% 95.48% # Number of insts commited each cycle
682system.cpu.commit.committed_per_cycle::8 29951867 4.52% 100.00% # Number of insts commited each cycle
683system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
684system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
685system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
686system.cpu.commit.committed_per_cycle::total 663080037 # Number of insts commited each cycle
687system.cpu.commit.committedInsts 640654411 # Number of instructions committed
688system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed
689system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
690system.cpu.commit.refs 381221434 # Number of memory references committed
691system.cpu.commit.loads 252240938 # Number of loads committed
692system.cpu.commit.membars 5740 # Number of memory barriers committed
693system.cpu.commit.branches 137364860 # Number of branches committed
694system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions.
695system.cpu.commit.int_insts 682251399 # Number of committed integer instructions.
696system.cpu.commit.function_calls 19275340 # Number of function calls committed.
697system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
698system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction
699system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
700system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
701system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
702system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
703system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
704system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
705system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction
706system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
707system.cpu.commit.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction
708system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
709system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
710system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
711system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
712system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
713system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
714system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
715system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
716system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
717system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
718system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
719system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
720system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
721system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
722system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
723system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
724system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
725system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
726system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
727system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
728system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
729system.cpu.commit.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction
730system.cpu.commit.op_class_0::MemWrite 125149822 15.87% 98.62% # Class of committed instruction
731system.cpu.commit.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction
732system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction
733system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
734system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
735system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction
736system.cpu.commit.bw_lim_events 29951867 # number cycles where commit BW limit reached
737system.cpu.rob.rob_reads 1525019812 # The number of ROB reads
738system.cpu.rob.rob_writes 1798395927 # The number of ROB writes
739system.cpu.timesIdled 10540 # Number of times that the entire CPU went into an idle state and unscheduled itself
740system.cpu.idleCycles 469345 # Total number of cycles that the CPU has spent unscheduled due to idling
741system.cpu.committedInsts 640649299 # Number of Instructions Simulated
742system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated
743system.cpu.cpi 1.058518 # CPI: Cycles Per Instruction
744system.cpu.cpi_total 1.058518 # CPI: Total CPI of All Threads
745system.cpu.ipc 0.944717 # IPC: Instructions Per Cycle
746system.cpu.ipc_total 0.944717 # IPC: Total IPC of All Threads
747system.cpu.int_regfile_reads 868485327 # number of integer regfile reads
748system.cpu.int_regfile_writes 500716513 # number of integer regfile writes
749system.cpu.fp_regfile_reads 30616072 # number of floating regfile reads
750system.cpu.fp_regfile_writes 22959512 # number of floating regfile writes
751system.cpu.cc_regfile_reads 3322428373 # number of cc regfile reads
752system.cpu.cc_regfile_writes 369236255 # number of cc regfile writes
753system.cpu.misc_regfile_reads 606835918 # number of misc regfile reads
754system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
755system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
756system.cpu.dcache.tags.replacements 2756526 # number of replacements
757system.cpu.dcache.tags.tagsinuse 511.910931 # Cycle average of tags in use
758system.cpu.dcache.tags.total_refs 371056816 # Total number of references to valid blocks.
759system.cpu.dcache.tags.sampled_refs 2757038 # Sample count of references to valid blocks.
760system.cpu.dcache.tags.avg_refs 134.585311 # Average number of references to valid blocks.
761system.cpu.dcache.tags.warmup_cycle 286323500 # Cycle when the warmup percentage was hit.
762system.cpu.dcache.tags.occ_blocks::cpu.data 511.910931 # Average occupied blocks per requestor
763system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy
764system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy
765system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
766system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
767system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
768system.cpu.dcache.tags.age_task_id_blocks_1024::2 176 # Occupied blocks per task id
769system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id
770system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
771system.cpu.dcache.tags.tag_accesses 751754868 # Number of tag accesses
772system.cpu.dcache.tags.data_accesses 751754868 # Number of data accesses
773system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
774system.cpu.dcache.ReadReq_hits::cpu.data 243133490 # number of ReadReq hits
775system.cpu.dcache.ReadReq_hits::total 243133490 # number of ReadReq hits
776system.cpu.dcache.WriteReq_hits::cpu.data 127906319 # number of WriteReq hits
777system.cpu.dcache.WriteReq_hits::total 127906319 # number of WriteReq hits
778system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits
779system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits
780system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
781system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
782system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
783system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
784system.cpu.dcache.demand_hits::cpu.data 371039809 # number of demand (read+write) hits
785system.cpu.dcache.demand_hits::total 371039809 # number of demand (read+write) hits
786system.cpu.dcache.overall_hits::cpu.data 371042966 # number of overall hits
787system.cpu.dcache.overall_hits::total 371042966 # number of overall hits
788system.cpu.dcache.ReadReq_misses::cpu.data 2398664 # number of ReadReq misses
789system.cpu.dcache.ReadReq_misses::total 2398664 # number of ReadReq misses
790system.cpu.dcache.WriteReq_misses::cpu.data 1045158 # number of WriteReq misses
791system.cpu.dcache.WriteReq_misses::total 1045158 # number of WriteReq misses
792system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses
793system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses
794system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
795system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
796system.cpu.dcache.demand_misses::cpu.data 3443822 # number of demand (read+write) misses
797system.cpu.dcache.demand_misses::total 3443822 # number of demand (read+write) misses
798system.cpu.dcache.overall_misses::cpu.data 3444469 # number of overall misses
799system.cpu.dcache.overall_misses::total 3444469 # number of overall misses
800system.cpu.dcache.ReadReq_miss_latency::cpu.data 80554008500 # number of ReadReq miss cycles
801system.cpu.dcache.ReadReq_miss_latency::total 80554008500 # number of ReadReq miss cycles
802system.cpu.dcache.WriteReq_miss_latency::cpu.data 9982772350 # number of WriteReq miss cycles
803system.cpu.dcache.WriteReq_miss_latency::total 9982772350 # number of WriteReq miss cycles
804system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles
805system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles
806system.cpu.dcache.demand_miss_latency::cpu.data 90536780850 # number of demand (read+write) miss cycles
807system.cpu.dcache.demand_miss_latency::total 90536780850 # number of demand (read+write) miss cycles
808system.cpu.dcache.overall_miss_latency::cpu.data 90536780850 # number of overall miss cycles
809system.cpu.dcache.overall_miss_latency::total 90536780850 # number of overall miss cycles
810system.cpu.dcache.ReadReq_accesses::cpu.data 245532154 # number of ReadReq accesses(hits+misses)
811system.cpu.dcache.ReadReq_accesses::total 245532154 # number of ReadReq accesses(hits+misses)
812system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
813system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
814system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses)
815system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses)
816system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses)
817system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses)
818system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
819system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
820system.cpu.dcache.demand_accesses::cpu.data 374483631 # number of demand (read+write) accesses
821system.cpu.dcache.demand_accesses::total 374483631 # number of demand (read+write) accesses
822system.cpu.dcache.overall_accesses::cpu.data 374487435 # number of overall (read+write) accesses
823system.cpu.dcache.overall_accesses::total 374487435 # number of overall (read+write) accesses
824system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009769 # miss rate for ReadReq accesses
825system.cpu.dcache.ReadReq_miss_rate::total 0.009769 # miss rate for ReadReq accesses
826system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008105 # miss rate for WriteReq accesses
827system.cpu.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses
828system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses
829system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses
830system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses
831system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses
832system.cpu.dcache.demand_miss_rate::cpu.data 0.009196 # miss rate for demand accesses
833system.cpu.dcache.demand_miss_rate::total 0.009196 # miss rate for demand accesses
834system.cpu.dcache.overall_miss_rate::cpu.data 0.009198 # miss rate for overall accesses
835system.cpu.dcache.overall_miss_rate::total 0.009198 # miss rate for overall accesses
836system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33582.864670 # average ReadReq miss latency
837system.cpu.dcache.ReadReq_avg_miss_latency::total 33582.864670 # average ReadReq miss latency
838system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9551.448059 # average WriteReq miss latency
839system.cpu.dcache.WriteReq_avg_miss_latency::total 9551.448059 # average WriteReq miss latency
840system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency
841system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency
842system.cpu.dcache.demand_avg_miss_latency::cpu.data 26289.622649 # average overall miss latency
843system.cpu.dcache.demand_avg_miss_latency::total 26289.622649 # average overall miss latency
844system.cpu.dcache.overall_avg_miss_latency::cpu.data 26284.684475 # average overall miss latency
845system.cpu.dcache.overall_avg_miss_latency::total 26284.684475 # average overall miss latency
846system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
847system.cpu.dcache.blocked_cycles::no_targets 344610 # number of cycles access was blocked
848system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
849system.cpu.dcache.blocked::no_targets 4869 # number of cycles access was blocked
850system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
851system.cpu.dcache.avg_blocked_cycles::no_targets 70.776340 # average number of cycles each access was blocked
852system.cpu.dcache.writebacks::writebacks 2756526 # number of writebacks
853system.cpu.dcache.writebacks::total 2756526 # number of writebacks
854system.cpu.dcache.ReadReq_mshr_hits::cpu.data 363119 # number of ReadReq MSHR hits
855system.cpu.dcache.ReadReq_mshr_hits::total 363119 # number of ReadReq MSHR hits
856system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323999 # number of WriteReq MSHR hits
857system.cpu.dcache.WriteReq_mshr_hits::total 323999 # number of WriteReq MSHR hits
858system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
859system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
860system.cpu.dcache.demand_mshr_hits::cpu.data 687118 # number of demand (read+write) MSHR hits
861system.cpu.dcache.demand_mshr_hits::total 687118 # number of demand (read+write) MSHR hits
862system.cpu.dcache.overall_mshr_hits::cpu.data 687118 # number of overall MSHR hits
863system.cpu.dcache.overall_mshr_hits::total 687118 # number of overall MSHR hits
864system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035545 # number of ReadReq MSHR misses
865system.cpu.dcache.ReadReq_mshr_misses::total 2035545 # number of ReadReq MSHR misses
866system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721159 # number of WriteReq MSHR misses
867system.cpu.dcache.WriteReq_mshr_misses::total 721159 # number of WriteReq MSHR misses
868system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses
869system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses
870system.cpu.dcache.demand_mshr_misses::cpu.data 2756704 # number of demand (read+write) MSHR misses
871system.cpu.dcache.demand_mshr_misses::total 2756704 # number of demand (read+write) MSHR misses
872system.cpu.dcache.overall_mshr_misses::cpu.data 2757346 # number of overall MSHR misses
873system.cpu.dcache.overall_mshr_misses::total 2757346 # number of overall MSHR misses
874system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75270268500 # number of ReadReq MSHR miss cycles
875system.cpu.dcache.ReadReq_mshr_miss_latency::total 75270268500 # number of ReadReq MSHR miss cycles
876system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5954605850 # number of WriteReq MSHR miss cycles
877system.cpu.dcache.WriteReq_mshr_miss_latency::total 5954605850 # number of WriteReq MSHR miss cycles
878system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5576500 # number of SoftPFReq MSHR miss cycles
879system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5576500 # number of SoftPFReq MSHR miss cycles
880system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81224874350 # number of demand (read+write) MSHR miss cycles
881system.cpu.dcache.demand_mshr_miss_latency::total 81224874350 # number of demand (read+write) MSHR miss cycles
882system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81230450850 # number of overall MSHR miss cycles
883system.cpu.dcache.overall_mshr_miss_latency::total 81230450850 # number of overall MSHR miss cycles
884system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses
885system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses
886system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses
887system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses
888system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses
889system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses
890system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses
891system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses
892system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses
893system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses
894system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36977.943745 # average ReadReq mshr miss latency
895system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36977.943745 # average ReadReq mshr miss latency
896system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8256.994435 # average WriteReq mshr miss latency
897system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8256.994435 # average WriteReq mshr miss latency
898system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8686.137072 # average SoftPFReq mshr miss latency
899system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8686.137072 # average SoftPFReq mshr miss latency
900system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29464.488879 # average overall mshr miss latency
901system.cpu.dcache.demand_avg_mshr_miss_latency::total 29464.488879 # average overall mshr miss latency
902system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29459.651001 # average overall mshr miss latency
903system.cpu.dcache.overall_avg_mshr_miss_latency::total 29459.651001 # average overall mshr miss latency
904system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
905system.cpu.icache.tags.replacements 1980658 # number of replacements
906system.cpu.icache.tags.tagsinuse 510.043873 # Cycle average of tags in use
907system.cpu.icache.tags.total_refs 245773558 # Total number of references to valid blocks.
908system.cpu.icache.tags.sampled_refs 1981168 # Sample count of references to valid blocks.
909system.cpu.icache.tags.avg_refs 124.054880 # Average number of references to valid blocks.
910system.cpu.icache.tags.warmup_cycle 275783500 # Cycle when the warmup percentage was hit.
911system.cpu.icache.tags.occ_blocks::cpu.inst 510.043873 # Average occupied blocks per requestor
912system.cpu.icache.tags.occ_percent::cpu.inst 0.996179 # Average percentage of cache occupancy
913system.cpu.icache.tags.occ_percent::total 0.996179 # Average percentage of cache occupancy
914system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
915system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
916system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
917system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
918system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
919system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id
920system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
921system.cpu.icache.tags.tag_accesses 497497160 # Number of tag accesses
922system.cpu.icache.tags.data_accesses 497497160 # Number of data accesses
923system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
924system.cpu.icache.ReadReq_hits::cpu.inst 245773612 # number of ReadReq hits
925system.cpu.icache.ReadReq_hits::total 245773612 # number of ReadReq hits
926system.cpu.icache.demand_hits::cpu.inst 245773612 # number of demand (read+write) hits
927system.cpu.icache.demand_hits::total 245773612 # number of demand (read+write) hits
928system.cpu.icache.overall_hits::cpu.inst 245773612 # number of overall hits
929system.cpu.icache.overall_hits::total 245773612 # number of overall hits
930system.cpu.icache.ReadReq_misses::cpu.inst 1984230 # number of ReadReq misses
931system.cpu.icache.ReadReq_misses::total 1984230 # number of ReadReq misses
932system.cpu.icache.demand_misses::cpu.inst 1984230 # number of demand (read+write) misses
933system.cpu.icache.demand_misses::total 1984230 # number of demand (read+write) misses
934system.cpu.icache.overall_misses::cpu.inst 1984230 # number of overall misses
935system.cpu.icache.overall_misses::total 1984230 # number of overall misses
936system.cpu.icache.ReadReq_miss_latency::cpu.inst 16225163428 # number of ReadReq miss cycles
937system.cpu.icache.ReadReq_miss_latency::total 16225163428 # number of ReadReq miss cycles
938system.cpu.icache.demand_miss_latency::cpu.inst 16225163428 # number of demand (read+write) miss cycles
939system.cpu.icache.demand_miss_latency::total 16225163428 # number of demand (read+write) miss cycles
940system.cpu.icache.overall_miss_latency::cpu.inst 16225163428 # number of overall miss cycles
941system.cpu.icache.overall_miss_latency::total 16225163428 # number of overall miss cycles
942system.cpu.icache.ReadReq_accesses::cpu.inst 247757842 # number of ReadReq accesses(hits+misses)
943system.cpu.icache.ReadReq_accesses::total 247757842 # number of ReadReq accesses(hits+misses)
944system.cpu.icache.demand_accesses::cpu.inst 247757842 # number of demand (read+write) accesses
945system.cpu.icache.demand_accesses::total 247757842 # number of demand (read+write) accesses
946system.cpu.icache.overall_accesses::cpu.inst 247757842 # number of overall (read+write) accesses
947system.cpu.icache.overall_accesses::total 247757842 # number of overall (read+write) accesses
948system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008009 # miss rate for ReadReq accesses
949system.cpu.icache.ReadReq_miss_rate::total 0.008009 # miss rate for ReadReq accesses
950system.cpu.icache.demand_miss_rate::cpu.inst 0.008009 # miss rate for demand accesses
951system.cpu.icache.demand_miss_rate::total 0.008009 # miss rate for demand accesses
952system.cpu.icache.overall_miss_rate::cpu.inst 0.008009 # miss rate for overall accesses
953system.cpu.icache.overall_miss_rate::total 0.008009 # miss rate for overall accesses
954system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8177.057815 # average ReadReq miss latency
955system.cpu.icache.ReadReq_avg_miss_latency::total 8177.057815 # average ReadReq miss latency
956system.cpu.icache.demand_avg_miss_latency::cpu.inst 8177.057815 # average overall miss latency
957system.cpu.icache.demand_avg_miss_latency::total 8177.057815 # average overall miss latency
958system.cpu.icache.overall_avg_miss_latency::cpu.inst 8177.057815 # average overall miss latency
959system.cpu.icache.overall_avg_miss_latency::total 8177.057815 # average overall miss latency
960system.cpu.icache.blocked_cycles::no_mshrs 86855 # number of cycles access was blocked
961system.cpu.icache.blocked_cycles::no_targets 219 # number of cycles access was blocked
962system.cpu.icache.blocked::no_mshrs 3239 # number of cycles access was blocked
963system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked
964system.cpu.icache.avg_blocked_cycles::no_mshrs 26.815375 # average number of cycles each access was blocked
965system.cpu.icache.avg_blocked_cycles::no_targets 31.285714 # average number of cycles each access was blocked
966system.cpu.icache.writebacks::writebacks 1980658 # number of writebacks
967system.cpu.icache.writebacks::total 1980658 # number of writebacks
968system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2752 # number of ReadReq MSHR hits
969system.cpu.icache.ReadReq_mshr_hits::total 2752 # number of ReadReq MSHR hits
970system.cpu.icache.demand_mshr_hits::cpu.inst 2752 # number of demand (read+write) MSHR hits
971system.cpu.icache.demand_mshr_hits::total 2752 # number of demand (read+write) MSHR hits
972system.cpu.icache.overall_mshr_hits::cpu.inst 2752 # number of overall MSHR hits
973system.cpu.icache.overall_mshr_hits::total 2752 # number of overall MSHR hits
974system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1981478 # number of ReadReq MSHR misses
975system.cpu.icache.ReadReq_mshr_misses::total 1981478 # number of ReadReq MSHR misses
976system.cpu.icache.demand_mshr_misses::cpu.inst 1981478 # number of demand (read+write) MSHR misses
977system.cpu.icache.demand_mshr_misses::total 1981478 # number of demand (read+write) MSHR misses
978system.cpu.icache.overall_mshr_misses::cpu.inst 1981478 # number of overall MSHR misses
979system.cpu.icache.overall_mshr_misses::total 1981478 # number of overall MSHR misses
980system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15191208442 # number of ReadReq MSHR miss cycles
981system.cpu.icache.ReadReq_mshr_miss_latency::total 15191208442 # number of ReadReq MSHR miss cycles
982system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15191208442 # number of demand (read+write) MSHR miss cycles
983system.cpu.icache.demand_mshr_miss_latency::total 15191208442 # number of demand (read+write) MSHR miss cycles
984system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15191208442 # number of overall MSHR miss cycles
985system.cpu.icache.overall_mshr_miss_latency::total 15191208442 # number of overall MSHR miss cycles
986system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for ReadReq accesses
987system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007998 # mshr miss rate for ReadReq accesses
988system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for demand accesses
989system.cpu.icache.demand_mshr_miss_rate::total 0.007998 # mshr miss rate for demand accesses
990system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for overall accesses
991system.cpu.icache.overall_mshr_miss_rate::total 0.007998 # mshr miss rate for overall accesses
992system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.604647 # average ReadReq mshr miss latency
993system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.604647 # average ReadReq mshr miss latency
994system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.604647 # average overall mshr miss latency
995system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.604647 # average overall mshr miss latency
996system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.604647 # average overall mshr miss latency
997system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.604647 # average overall mshr miss latency
998system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
999system.cpu.l2cache.prefetcher.num_hwpf_issued 1350180 # number of hwpf issued
1000system.cpu.l2cache.prefetcher.pfIdentified 1355046 # number of prefetch candidates identified
1001system.cpu.l2cache.prefetcher.pfBufferHit 4259 # number of redundant prefetches already in prefetch queue
1002system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1003system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1004system.cpu.l2cache.prefetcher.pfSpanPage 4789962 # number of prefetches not generated due to page crossing
1005system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
1006system.cpu.l2cache.tags.replacements 297363 # number of replacements
1007system.cpu.l2cache.tags.tagsinuse 16097.095848 # Cycle average of tags in use
1008system.cpu.l2cache.tags.total_refs 3953275 # Total number of references to valid blocks.
1009system.cpu.l2cache.tags.sampled_refs 313560 # Sample count of references to valid blocks.
1010system.cpu.l2cache.tags.avg_refs 12.607715 # Average number of references to valid blocks.
1011system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1012system.cpu.l2cache.tags.occ_blocks::writebacks 15676.959856 # Average occupied blocks per requestor
1013system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.135992 # Average occupied blocks per requestor
1014system.cpu.l2cache.tags.occ_percent::writebacks 0.956846 # Average percentage of cache occupancy
1015system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025643 # Average percentage of cache occupancy
1016system.cpu.l2cache.tags.occ_percent::total 0.982489 # Average percentage of cache occupancy
1017system.cpu.l2cache.tags.occ_task_id_blocks::1022 460 # Occupied blocks per task id
1018system.cpu.l2cache.tags.occ_task_id_blocks::1024 15737 # Occupied blocks per task id
1019system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id
1020system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id
1021system.cpu.l2cache.tags.age_task_id_blocks_1022::3 274 # Occupied blocks per task id
1022system.cpu.l2cache.tags.age_task_id_blocks_1022::4 116 # Occupied blocks per task id
1023system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
1024system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id
1025system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1553 # Occupied blocks per task id
1026system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3714 # Occupied blocks per task id
1027system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9969 # Occupied blocks per task id
1028system.cpu.l2cache.tags.occ_task_id_percent::1022 0.028076 # Percentage of cache occupancy per task id
1029system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960510 # Percentage of cache occupancy per task id
1030system.cpu.l2cache.tags.tag_accesses 145611380 # Number of tag accesses
1031system.cpu.l2cache.tags.data_accesses 145611380 # Number of data accesses
1032system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
1033system.cpu.l2cache.WritebackDirty_hits::writebacks 735645 # number of WritebackDirty hits
1034system.cpu.l2cache.WritebackDirty_hits::total 735645 # number of WritebackDirty hits
1035system.cpu.l2cache.WritebackClean_hits::writebacks 3358020 # number of WritebackClean hits
1036system.cpu.l2cache.WritebackClean_hits::total 3358020 # number of WritebackClean hits
1037system.cpu.l2cache.ReadExReq_hits::cpu.data 718668 # number of ReadExReq hits
1038system.cpu.l2cache.ReadExReq_hits::total 718668 # number of ReadExReq hits
1039system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976918 # number of ReadCleanReq hits
1040system.cpu.l2cache.ReadCleanReq_hits::total 1976918 # number of ReadCleanReq hits
1041system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1285460 # number of ReadSharedReq hits
1042system.cpu.l2cache.ReadSharedReq_hits::total 1285460 # number of ReadSharedReq hits
1043system.cpu.l2cache.demand_hits::cpu.inst 1976918 # number of demand (read+write) hits
1044system.cpu.l2cache.demand_hits::cpu.data 2004128 # number of demand (read+write) hits
1045system.cpu.l2cache.demand_hits::total 3981046 # number of demand (read+write) hits
1046system.cpu.l2cache.overall_hits::cpu.inst 1976918 # number of overall hits
1047system.cpu.l2cache.overall_hits::cpu.data 2004128 # number of overall hits
1048system.cpu.l2cache.overall_hits::total 3981046 # number of overall hits
1049system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses
1050system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses
1051system.cpu.l2cache.ReadExReq_misses::cpu.data 2183 # number of ReadExReq misses
1052system.cpu.l2cache.ReadExReq_misses::total 2183 # number of ReadExReq misses
1053system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4253 # number of ReadCleanReq misses
1054system.cpu.l2cache.ReadCleanReq_misses::total 4253 # number of ReadCleanReq misses
1055system.cpu.l2cache.ReadSharedReq_misses::cpu.data 750727 # number of ReadSharedReq misses
1056system.cpu.l2cache.ReadSharedReq_misses::total 750727 # number of ReadSharedReq misses
1057system.cpu.l2cache.demand_misses::cpu.inst 4253 # number of demand (read+write) misses
1058system.cpu.l2cache.demand_misses::cpu.data 752910 # number of demand (read+write) misses
1059system.cpu.l2cache.demand_misses::total 757163 # number of demand (read+write) misses
1060system.cpu.l2cache.overall_misses::cpu.inst 4253 # number of overall misses
1061system.cpu.l2cache.overall_misses::cpu.data 752910 # number of overall misses
1062system.cpu.l2cache.overall_misses::total 757163 # number of overall misses
1063system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 189493000 # number of ReadExReq miss cycles
1064system.cpu.l2cache.ReadExReq_miss_latency::total 189493000 # number of ReadExReq miss cycles
1065system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 353014500 # number of ReadCleanReq miss cycles
1066system.cpu.l2cache.ReadCleanReq_miss_latency::total 353014500 # number of ReadCleanReq miss cycles
1067system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63858972500 # number of ReadSharedReq miss cycles
1068system.cpu.l2cache.ReadSharedReq_miss_latency::total 63858972500 # number of ReadSharedReq miss cycles
1069system.cpu.l2cache.demand_miss_latency::cpu.inst 353014500 # number of demand (read+write) miss cycles
1070system.cpu.l2cache.demand_miss_latency::cpu.data 64048465500 # number of demand (read+write) miss cycles
1071system.cpu.l2cache.demand_miss_latency::total 64401480000 # number of demand (read+write) miss cycles
1072system.cpu.l2cache.overall_miss_latency::cpu.inst 353014500 # number of overall miss cycles
1073system.cpu.l2cache.overall_miss_latency::cpu.data 64048465500 # number of overall miss cycles
1074system.cpu.l2cache.overall_miss_latency::total 64401480000 # number of overall miss cycles
1075system.cpu.l2cache.WritebackDirty_accesses::writebacks 735645 # number of WritebackDirty accesses(hits+misses)
1076system.cpu.l2cache.WritebackDirty_accesses::total 735645 # number of WritebackDirty accesses(hits+misses)
1077system.cpu.l2cache.WritebackClean_accesses::writebacks 3358020 # number of WritebackClean accesses(hits+misses)
1078system.cpu.l2cache.WritebackClean_accesses::total 3358020 # number of WritebackClean accesses(hits+misses)
1079system.cpu.l2cache.UpgradeReq_accesses::cpu.data 308 # number of UpgradeReq accesses(hits+misses)
1080system.cpu.l2cache.UpgradeReq_accesses::total 308 # number of UpgradeReq accesses(hits+misses)
1081system.cpu.l2cache.ReadExReq_accesses::cpu.data 720851 # number of ReadExReq accesses(hits+misses)
1082system.cpu.l2cache.ReadExReq_accesses::total 720851 # number of ReadExReq accesses(hits+misses)
1083system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1981171 # number of ReadCleanReq accesses(hits+misses)
1084system.cpu.l2cache.ReadCleanReq_accesses::total 1981171 # number of ReadCleanReq accesses(hits+misses)
1085system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036187 # number of ReadSharedReq accesses(hits+misses)
1086system.cpu.l2cache.ReadSharedReq_accesses::total 2036187 # number of ReadSharedReq accesses(hits+misses)
1087system.cpu.l2cache.demand_accesses::cpu.inst 1981171 # number of demand (read+write) accesses
1088system.cpu.l2cache.demand_accesses::cpu.data 2757038 # number of demand (read+write) accesses
1089system.cpu.l2cache.demand_accesses::total 4738209 # number of demand (read+write) accesses
1090system.cpu.l2cache.overall_accesses::cpu.inst 1981171 # number of overall (read+write) accesses
1091system.cpu.l2cache.overall_accesses::cpu.data 2757038 # number of overall (read+write) accesses
1092system.cpu.l2cache.overall_accesses::total 4738209 # number of overall (read+write) accesses
1093system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1094system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1095system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003028 # miss rate for ReadExReq accesses
1096system.cpu.l2cache.ReadExReq_miss_rate::total 0.003028 # miss rate for ReadExReq accesses
1097system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002147 # miss rate for ReadCleanReq accesses
1098system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002147 # miss rate for ReadCleanReq accesses
1099system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368693 # miss rate for ReadSharedReq accesses
1100system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368693 # miss rate for ReadSharedReq accesses
1101system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002147 # miss rate for demand accesses
1102system.cpu.l2cache.demand_miss_rate::cpu.data 0.273087 # miss rate for demand accesses
1103system.cpu.l2cache.demand_miss_rate::total 0.159799 # miss rate for demand accesses
1104system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002147 # miss rate for overall accesses
1105system.cpu.l2cache.overall_miss_rate::cpu.data 0.273087 # miss rate for overall accesses
1106system.cpu.l2cache.overall_miss_rate::total 0.159799 # miss rate for overall accesses
1107system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86803.939533 # average ReadExReq miss latency
1108system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86803.939533 # average ReadExReq miss latency
1109system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83003.644486 # average ReadCleanReq miss latency
1110system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83003.644486 # average ReadCleanReq miss latency
1111system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85062.842418 # average ReadSharedReq miss latency
1112system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85062.842418 # average ReadSharedReq miss latency
1113system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83003.644486 # average overall miss latency
1114system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85067.890585 # average overall miss latency
1115system.cpu.l2cache.demand_avg_miss_latency::total 85056.295672 # average overall miss latency
1116system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83003.644486 # average overall miss latency
1117system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85067.890585 # average overall miss latency
1118system.cpu.l2cache.overall_avg_miss_latency::total 85056.295672 # average overall miss latency
1119system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1120system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1121system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1122system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1123system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1124system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1125system.cpu.l2cache.unused_prefetches 3562 # number of HardPF blocks evicted w/o reference
1126system.cpu.l2cache.writebacks::writebacks 66350 # number of writebacks
1127system.cpu.l2cache.writebacks::total 66350 # number of writebacks
1128system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 796 # number of ReadExReq MSHR hits
1129system.cpu.l2cache.ReadExReq_mshr_hits::total 796 # number of ReadExReq MSHR hits
1130system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
1131system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
1132system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1085 # number of ReadSharedReq MSHR hits
1133system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1085 # number of ReadSharedReq MSHR hits
1134system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1135system.cpu.l2cache.demand_mshr_hits::cpu.data 1881 # number of demand (read+write) MSHR hits
1136system.cpu.l2cache.demand_mshr_hits::total 1883 # number of demand (read+write) MSHR hits
1137system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1138system.cpu.l2cache.overall_mshr_hits::cpu.data 1881 # number of overall MSHR hits
1139system.cpu.l2cache.overall_mshr_hits::total 1883 # number of overall MSHR hits
1140system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202894 # number of HardPFReq MSHR misses
1141system.cpu.l2cache.HardPFReq_mshr_misses::total 202894 # number of HardPFReq MSHR misses
1142system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses
1143system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses
1144system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses
1145system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses
1146system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4251 # number of ReadCleanReq MSHR misses
1147system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4251 # number of ReadCleanReq MSHR misses
1148system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 749642 # number of ReadSharedReq MSHR misses
1149system.cpu.l2cache.ReadSharedReq_mshr_misses::total 749642 # number of ReadSharedReq MSHR misses
1150system.cpu.l2cache.demand_mshr_misses::cpu.inst 4251 # number of demand (read+write) MSHR misses
1151system.cpu.l2cache.demand_mshr_misses::cpu.data 751029 # number of demand (read+write) MSHR misses
1152system.cpu.l2cache.demand_mshr_misses::total 755280 # number of demand (read+write) MSHR misses
1153system.cpu.l2cache.overall_mshr_misses::cpu.inst 4251 # number of overall MSHR misses
1154system.cpu.l2cache.overall_mshr_misses::cpu.data 751029 # number of overall MSHR misses
1155system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202894 # number of overall MSHR misses
1156system.cpu.l2cache.overall_mshr_misses::total 958174 # number of overall MSHR misses
1157system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20344447507 # number of HardPFReq MSHR miss cycles
1158system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20344447507 # number of HardPFReq MSHR miss cycles
1159system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4667000 # number of UpgradeReq MSHR miss cycles
1160system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4667000 # number of UpgradeReq MSHR miss cycles
1161system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 140070000 # number of ReadExReq MSHR miss cycles
1162system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 140070000 # number of ReadExReq MSHR miss cycles
1163system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 327411500 # number of ReadCleanReq MSHR miss cycles
1164system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 327411500 # number of ReadCleanReq MSHR miss cycles
1165system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59289686000 # number of ReadSharedReq MSHR miss cycles
1166system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59289686000 # number of ReadSharedReq MSHR miss cycles
1167system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 327411500 # number of demand (read+write) MSHR miss cycles
1168system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59429756000 # number of demand (read+write) MSHR miss cycles
1169system.cpu.l2cache.demand_mshr_miss_latency::total 59757167500 # number of demand (read+write) MSHR miss cycles
1170system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 327411500 # number of overall MSHR miss cycles
1171system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59429756000 # number of overall MSHR miss cycles
1172system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20344447507 # number of overall MSHR miss cycles
1173system.cpu.l2cache.overall_mshr_miss_latency::total 80101615007 # number of overall MSHR miss cycles
1174system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1175system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1176system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1177system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1178system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses
1179system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses
1180system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for ReadCleanReq accesses
1181system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002146 # mshr miss rate for ReadCleanReq accesses
1182system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.368160 # mshr miss rate for ReadSharedReq accesses
1183system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.368160 # mshr miss rate for ReadSharedReq accesses
1184system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for demand accesses
1185system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272404 # mshr miss rate for demand accesses
1186system.cpu.l2cache.demand_mshr_miss_rate::total 0.159402 # mshr miss rate for demand accesses
1187system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for overall accesses
1188system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272404 # mshr miss rate for overall accesses
1189system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1190system.cpu.l2cache.overall_mshr_miss_rate::total 0.202223 # mshr miss rate for overall accesses
1191system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100271.311655 # average HardPFReq mshr miss latency
1192system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100271.311655 # average HardPFReq mshr miss latency
1193system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15152.597403 # average UpgradeReq mshr miss latency
1194system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15152.597403 # average UpgradeReq mshr miss latency
1195system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100987.743331 # average ReadExReq mshr miss latency
1196system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100987.743331 # average ReadExReq mshr miss latency
1197system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77019.877676 # average ReadCleanReq mshr miss latency
1198system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77019.877676 # average ReadCleanReq mshr miss latency
1199system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79090.667279 # average ReadSharedReq mshr miss latency
1200system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79090.667279 # average ReadSharedReq mshr miss latency
1201system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77019.877676 # average overall mshr miss latency
1202system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79131.106788 # average overall mshr miss latency
1203system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79119.223996 # average overall mshr miss latency
1204system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77019.877676 # average overall mshr miss latency
1205system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79131.106788 # average overall mshr miss latency
1206system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100271.311655 # average overall mshr miss latency
1207system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83598.193029 # average overall mshr miss latency
1208system.cpu.toL2Bus.snoop_filter.tot_requests 9476008 # Total number of requests made to the snoop filter.
1209system.cpu.toL2Bus.snoop_filter.hit_single_requests 4737217 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1210system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644846 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1211system.cpu.toL2Bus.snoop_filter.tot_snoops 94 # Total number of snoops made to the snoop filter.
1212system.cpu.toL2Bus.snoop_filter.hit_single_snoops 93 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1213system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1214system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
1215system.cpu.toL2Bus.trans_dist::ReadResp 4017663 # Transaction distribution
1216system.cpu.toL2Bus.trans_dist::WritebackDirty 801995 # Transaction distribution
1217system.cpu.toL2Bus.trans_dist::WritebackClean 4001539 # Transaction distribution
1218system.cpu.toL2Bus.trans_dist::CleanEvict 231013 # Transaction distribution
1219system.cpu.toL2Bus.trans_dist::HardPFReq 255559 # Transaction distribution
1220system.cpu.toL2Bus.trans_dist::UpgradeReq 308 # Transaction distribution
1221system.cpu.toL2Bus.trans_dist::UpgradeResp 308 # Transaction distribution
1222system.cpu.toL2Bus.trans_dist::ReadExReq 720851 # Transaction distribution
1223system.cpu.toL2Bus.trans_dist::ReadExResp 720851 # Transaction distribution
1224system.cpu.toL2Bus.trans_dist::ReadCleanReq 1981478 # Transaction distribution
1225system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036187 # Transaction distribution
1226system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5943305 # Packet count per connected master and slave (bytes)
1227system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8271218 # Packet count per connected master and slave (bytes)
1228system.cpu.toL2Bus.pkt_count::total 14214523 # Packet count per connected master and slave (bytes)
1229system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253556928 # Cumulative packet size per connected master and slave (bytes)
1230system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352868096 # Cumulative packet size per connected master and slave (bytes)
1231system.cpu.toL2Bus.pkt_size::total 606425024 # Cumulative packet size per connected master and slave (bytes)
1232system.cpu.toL2Bus.snoops 553229 # Total snoops (count)
1233system.cpu.toL2Bus.snoopTraffic 4266048 # Total snoop traffic (bytes)
1234system.cpu.toL2Bus.snoop_fanout::samples 5291746 # Request fanout histogram
1235system.cpu.toL2Bus.snoop_fanout::mean 0.121883 # Request fanout histogram
1236system.cpu.toL2Bus.snoop_fanout::stdev 0.327151 # Request fanout histogram
1237system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1238system.cpu.toL2Bus.snoop_fanout::0 4646773 87.81% 87.81% # Request fanout histogram
1239system.cpu.toL2Bus.snoop_fanout::1 644972 12.19% 100.00% # Request fanout histogram
1240system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
1241system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1242system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1243system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1244system.cpu.toL2Bus.snoop_fanout::total 5291746 # Request fanout histogram
1245system.cpu.toL2Bus.reqLayer0.occupancy 9475188000 # Layer occupancy (ticks)
1246system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%)
1247system.cpu.toL2Bus.respLayer0.occupancy 2972215996 # Layer occupancy (ticks)
1248system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
1249system.cpu.toL2Bus.respLayer1.occupancy 4135722477 # Layer occupancy (ticks)
1250system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
1251system.membus.snoop_filter.tot_requests 1255754 # Total number of requests made to the snoop filter.
1252system.membus.snoop_filter.hit_single_requests 941197 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1253system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1254system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1255system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1256system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1257system.membus.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states
1258system.membus.trans_dist::ReadResp 956694 # Transaction distribution
1259system.membus.trans_dist::WritebackDirty 66350 # Transaction distribution
1260system.membus.trans_dist::CleanEvict 231013 # Transaction distribution
1261system.membus.trans_dist::UpgradeReq 308 # Transaction distribution
1262system.membus.trans_dist::ReadExReq 1387 # Transaction distribution
1263system.membus.trans_dist::ReadExResp 1387 # Transaction distribution
1264system.membus.trans_dist::ReadSharedReq 956696 # Transaction distribution
1265system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2213835 # Packet count per connected master and slave (bytes)
1266system.membus.pkt_count::total 2213835 # Packet count per connected master and slave (bytes)
1267system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65563584 # Cumulative packet size per connected master and slave (bytes)
1268system.membus.pkt_size::total 65563584 # Cumulative packet size per connected master and slave (bytes)
1269system.membus.snoops 0 # Total snoops (count)
1270system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1271system.membus.snoop_fanout::samples 958391 # Request fanout histogram
1272system.membus.snoop_fanout::mean 0 # Request fanout histogram
1273system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1274system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1275system.membus.snoop_fanout::0 958391 100.00% 100.00% # Request fanout histogram
1276system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1277system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1278system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1279system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1280system.membus.snoop_fanout::total 958391 # Request fanout histogram
1281system.membus.reqLayer0.occupancy 1760245062 # Layer occupancy (ticks)
1282system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
1283system.membus.respLayer1.occupancy 5035040414 # Layer occupancy (ticks)
1284system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
1285
1286---------- End Simulation Statistics ----------