1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.326731 # Number of seconds simulated
4sim_ticks 326731324000 # Number of ticks simulated
5final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 188423 # Simulator instruction rate (inst/s)
8host_op_rate 231974 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 96095829 # Simulator tick rate (ticks/s)
10host_mem_usage 319396 # Number of bytes of host memory used
11host_seconds 3400.06 # Real time elapsed on the host
12sim_insts 640649299 # Number of instructions simulated
13sim_ops 788724958 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory
19system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory
23system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory
--- 266 unchanged lines hidden (view full) ---
290system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ)
291system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ)
292system.physmem_1.averagePower 704.579541 # Core power per rank (mW)
293system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states
294system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states
295system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
296system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states
297system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
298system.cpu.branchPred.lookups 174663372 # Number of BP lookups
299system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted
300system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect
301system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups
302system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits
303system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
304system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage
305system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target.
306system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions.
307system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups.
308system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits.
309system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses.
310system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches.
311system.cpu_clk_domain.clock 500 # Clock period in ticks
312system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
333system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
334system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
335system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
336system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
337system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
338system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
339system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
340system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
341system.cpu.dtb.walker.walks 0 # Table walker walks requested
342system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
343system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
344system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
345system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
346system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
347system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
348system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
362system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
363system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
364system.cpu.dtb.read_accesses 0 # DTB read accesses
365system.cpu.dtb.write_accesses 0 # DTB write accesses
366system.cpu.dtb.inst_accesses 0 # ITB inst accesses
367system.cpu.dtb.hits 0 # DTB hits
368system.cpu.dtb.misses 0 # DTB misses
369system.cpu.dtb.accesses 0 # DTB accesses
370system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
391system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
392system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
393system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
394system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
395system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
396system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
397system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
398system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
399system.cpu.itb.walker.walks 0 # Table walker walks requested
400system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
401system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
402system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
403system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
404system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
405system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
406system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 14 unchanged lines hidden (view full) ---
421system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
422system.cpu.itb.read_accesses 0 # DTB read accesses
423system.cpu.itb.write_accesses 0 # DTB write accesses
424system.cpu.itb.inst_accesses 0 # ITB inst accesses
425system.cpu.itb.hits 0 # DTB hits
426system.cpu.itb.misses 0 # DTB misses
427system.cpu.itb.accesses 0 # DTB accesses
428system.cpu.workload.num_syscalls 673 # Number of system calls
429system.cpu.numCycles 653462649 # number of cpu cycles simulated
430system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
431system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
432system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss
433system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed
434system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered
435system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken
436system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked
--- 274 unchanged lines hidden (view full) ---
711system.cpu.int_regfile_reads 868460109 # number of integer regfile reads
712system.cpu.int_regfile_writes 500697086 # number of integer regfile writes
713system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads
714system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes
715system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads
716system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes
717system.cpu.misc_regfile_reads 606830949 # number of misc regfile reads
718system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
719system.cpu.dcache.tags.replacements 2756452 # number of replacements
720system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use
721system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks.
722system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks.
723system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks.
724system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit.
725system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor
726system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy
727system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy
728system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
729system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
730system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
731system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id
732system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id
733system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
734system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses
735system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses
736system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits
737system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits
738system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits
739system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits
740system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits
741system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits
742system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits
743system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits
--- 114 unchanged lines hidden (view full) ---
858system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency
859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency
860system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency
861system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency
862system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency
863system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency
864system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency
865system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency
866system.cpu.icache.tags.replacements 1979880 # number of replacements
867system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use
868system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks.
869system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks.
870system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks.
871system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit.
872system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor
873system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy
874system.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy
875system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
876system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
877system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
878system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
879system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id
880system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
881system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses
882system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses
883system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits
884system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits
885system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits
886system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits
887system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits
888system.cpu.icache.overall_hits::total 245759426 # number of overall hits
889system.cpu.icache.ReadReq_misses::cpu.inst 1983591 # number of ReadReq misses
890system.cpu.icache.ReadReq_misses::total 1983591 # number of ReadReq misses
--- 58 unchanged lines hidden (view full) ---
949system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses
950system.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses
951system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency
952system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency
953system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
954system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
955system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
956system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
957system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued
958system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified
959system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue
960system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
961system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
962system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing
963system.cpu.l2cache.tags.replacements 301370 # number of replacements
964system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use
965system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks.
966system.cpu.l2cache.tags.sampled_refs 317734 # Sample count of references to valid blocks.
967system.cpu.l2cache.tags.avg_refs 22.730041 # Average number of references to valid blocks.
968system.cpu.l2cache.tags.warmup_cycle 44242160500 # Cycle when the warmup percentage was hit.
969system.cpu.l2cache.tags.occ_blocks::writebacks 9843.702780 # Average occupied blocks per requestor
970system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6506.729901 # Average occupied blocks per requestor
--- 10 unchanged lines hidden (view full) ---
981system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
982system.cpu.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
983system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2583 # Occupied blocks per task id
984system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6932 # Occupied blocks per task id
985system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 # Percentage of cache occupancy per task id
986system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id
987system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses
988system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses
989system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits
990system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits
991system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits
992system.cpu.l2cache.WritebackClean_hits::total 3356496 # number of WritebackClean hits
993system.cpu.l2cache.ReadExReq_hits::cpu.data 718501 # number of ReadExReq hits
994system.cpu.l2cache.ReadExReq_hits::total 718501 # number of ReadExReq hits
995system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976843 # number of ReadCleanReq hits
996system.cpu.l2cache.ReadCleanReq_hits::total 1976843 # number of ReadCleanReq hits
--- 165 unchanged lines hidden (view full) ---
1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency
1163system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency
1164system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter.
1165system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1166system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1167system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter.
1168system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1169system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1170system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution
1171system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution
1172system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution
1173system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution
1174system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution
1175system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution
1176system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution
1177system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution
--- 19 unchanged lines hidden (view full) ---
1197system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1198system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram
1199system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks)
1200system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%)
1201system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks)
1202system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
1203system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks)
1204system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
1205system.membus.trans_dist::ReadResp 951856 # Transaction distribution
1206system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution
1207system.membus.trans_dist::CleanEvict 227102 # Transaction distribution
1208system.membus.trans_dist::UpgradeReq 185 # Transaction distribution
1209system.membus.trans_dist::ReadExReq 1383 # Transaction distribution
1210system.membus.trans_dist::ReadExResp 1383 # Transaction distribution
1211system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution
1212system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes)
--- 20 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.326731 # Number of seconds simulated
4sim_ticks 326731324000 # Number of ticks simulated
5final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 188423 # Simulator instruction rate (inst/s)
8host_op_rate 231974 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 96095829 # Simulator tick rate (ticks/s)
10host_mem_usage 319396 # Number of bytes of host memory used
11host_seconds 3400.06 # Real time elapsed on the host
12sim_insts 640649299 # Number of instructions simulated
13sim_ops 788724958 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory
19system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory
23system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory
--- 266 unchanged lines hidden (view full) ---
290system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ)
291system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ)
292system.physmem_1.averagePower 704.579541 # Core power per rank (mW)
293system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states
294system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states
295system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
296system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states
297system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
298system.cpu.branchPred.lookups 174663372 # Number of BP lookups
299system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted
300system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect
301system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups
302system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits
303system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
304system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage
305system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target.
306system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions.
307system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups.
308system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits.
309system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses.
310system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches.
311system.cpu_clk_domain.clock 500 # Clock period in ticks
312system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
333system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
334system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
335system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
336system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
337system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
338system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
339system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
340system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
341system.cpu.dtb.walker.walks 0 # Table walker walks requested
342system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
343system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
344system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
345system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
346system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
347system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
348system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
362system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
363system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
364system.cpu.dtb.read_accesses 0 # DTB read accesses
365system.cpu.dtb.write_accesses 0 # DTB write accesses
366system.cpu.dtb.inst_accesses 0 # ITB inst accesses
367system.cpu.dtb.hits 0 # DTB hits
368system.cpu.dtb.misses 0 # DTB misses
369system.cpu.dtb.accesses 0 # DTB accesses
370system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
391system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
392system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
393system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
394system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
395system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
396system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
397system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
398system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
399system.cpu.itb.walker.walks 0 # Table walker walks requested
400system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
401system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
402system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
403system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
404system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
405system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
406system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 14 unchanged lines hidden (view full) ---
421system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
422system.cpu.itb.read_accesses 0 # DTB read accesses
423system.cpu.itb.write_accesses 0 # DTB write accesses
424system.cpu.itb.inst_accesses 0 # ITB inst accesses
425system.cpu.itb.hits 0 # DTB hits
426system.cpu.itb.misses 0 # DTB misses
427system.cpu.itb.accesses 0 # DTB accesses
428system.cpu.workload.num_syscalls 673 # Number of system calls
429system.cpu.numCycles 653462649 # number of cpu cycles simulated
430system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
431system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
432system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss
433system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed
434system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered
435system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken
436system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked
--- 274 unchanged lines hidden (view full) ---
711system.cpu.int_regfile_reads 868460109 # number of integer regfile reads
712system.cpu.int_regfile_writes 500697086 # number of integer regfile writes
713system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads
714system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes
715system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads
716system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes
717system.cpu.misc_regfile_reads 606830949 # number of misc regfile reads
718system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
719system.cpu.dcache.tags.replacements 2756452 # number of replacements
720system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use
721system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks.
722system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks.
723system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks.
724system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit.
725system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor
726system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy
727system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy
728system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
729system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
730system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
731system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id
732system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id
733system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
734system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses
735system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses
736system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits
737system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits
738system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits
739system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits
740system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits
741system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits
742system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits
743system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits
--- 114 unchanged lines hidden (view full) ---
858system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency
859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency
860system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency
861system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency
862system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency
863system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency
864system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency
865system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency
866system.cpu.icache.tags.replacements 1979880 # number of replacements
867system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use
868system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks.
869system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks.
870system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks.
871system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit.
872system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor
873system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy
874system.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy
875system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
876system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
877system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
878system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
879system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id
880system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
881system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses
882system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses
883system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits
884system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits
885system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits
886system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits
887system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits
888system.cpu.icache.overall_hits::total 245759426 # number of overall hits
889system.cpu.icache.ReadReq_misses::cpu.inst 1983591 # number of ReadReq misses
890system.cpu.icache.ReadReq_misses::total 1983591 # number of ReadReq misses
--- 58 unchanged lines hidden (view full) ---
949system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses
950system.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses
951system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency
952system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency
953system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
954system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
955system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
956system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
957system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued
958system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified
959system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue
960system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
961system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
962system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing
963system.cpu.l2cache.tags.replacements 301370 # number of replacements
964system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use
965system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks.
966system.cpu.l2cache.tags.sampled_refs 317734 # Sample count of references to valid blocks.
967system.cpu.l2cache.tags.avg_refs 22.730041 # Average number of references to valid blocks.
968system.cpu.l2cache.tags.warmup_cycle 44242160500 # Cycle when the warmup percentage was hit.
969system.cpu.l2cache.tags.occ_blocks::writebacks 9843.702780 # Average occupied blocks per requestor
970system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6506.729901 # Average occupied blocks per requestor
--- 10 unchanged lines hidden (view full) ---
981system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
982system.cpu.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
983system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2583 # Occupied blocks per task id
984system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6932 # Occupied blocks per task id
985system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 # Percentage of cache occupancy per task id
986system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id
987system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses
988system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses
989system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits
990system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits
991system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits
992system.cpu.l2cache.WritebackClean_hits::total 3356496 # number of WritebackClean hits
993system.cpu.l2cache.ReadExReq_hits::cpu.data 718501 # number of ReadExReq hits
994system.cpu.l2cache.ReadExReq_hits::total 718501 # number of ReadExReq hits
995system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976843 # number of ReadCleanReq hits
996system.cpu.l2cache.ReadCleanReq_hits::total 1976843 # number of ReadCleanReq hits
--- 165 unchanged lines hidden (view full) ---
1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency
1163system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency
1164system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter.
1165system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1166system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1167system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter.
1168system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1169system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1170system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution
1171system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution
1172system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution
1173system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution
1174system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution
1175system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution
1176system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution
1177system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution
--- 19 unchanged lines hidden (view full) ---
1197system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1198system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram
1199system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks)
1200system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%)
1201system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks)
1202system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
1203system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks)
1204system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
1205system.membus.trans_dist::ReadResp 951856 # Transaction distribution
1206system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution
1207system.membus.trans_dist::CleanEvict 227102 # Transaction distribution
1208system.membus.trans_dist::UpgradeReq 185 # Transaction distribution
1209system.membus.trans_dist::ReadExReq 1383 # Transaction distribution
1210system.membus.trans_dist::ReadExResp 1383 # Transaction distribution
1211system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution
1212system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes)
--- 20 unchanged lines hidden ---