| config.ini (11680:b4d943429dc6) | config.ini (11954:19e1cd4edfd2) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 51 unchanged lines hidden (view full) --- 60LQEntries=16 61LSQCheckLoads=true 62LSQDepCheckShift=0 63SQEntries=16 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 51 unchanged lines hidden (view full) --- 60LQEntries=16 61LSQCheckLoads=true 62LSQDepCheckShift=0 63SQEntries=16 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred |
| 68cachePorts=200 | 68cacheStorePorts=200 |
| 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 --- 59 unchanged lines hidden (view full) --- 136smtLSQThreshold=100 137smtNumFetchingThreads=1 138smtROBPolicy=Partitioned 139smtROBThreshold=100 140socket_id=0 141squashWidth=8 142store_set_clear_period=250000 143switched_out=false | 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 --- 59 unchanged lines hidden (view full) --- 136smtLSQThreshold=100 137smtNumFetchingThreads=1 138smtROBPolicy=Partitioned 139smtROBThreshold=100 140socket_id=0 141squashWidth=8 142store_set_clear_period=250000 143switched_out=false |
| 144syscallRetryLatency=10000 |
|
| 144system=system 145tracer=system.cpu.tracer 146trapLatency=13 147wbWidth=8 148workload=system.cpu.workload 149dcache_port=system.cpu.dcache.cpu_side 150icache_port=system.cpu.icache.cpu_side 151 --- 19 unchanged lines hidden (view full) --- 171 172[system.cpu.dcache] 173type=Cache 174children=tags 175addr_ranges=0:18446744073709551615:0:0:0:0 176assoc=2 177clk_domain=system.cpu_clk_domain 178clusivity=mostly_incl | 145system=system 146tracer=system.cpu.tracer 147trapLatency=13 148wbWidth=8 149workload=system.cpu.workload 150dcache_port=system.cpu.dcache.cpu_side 151icache_port=system.cpu.icache.cpu_side 152 --- 19 unchanged lines hidden (view full) --- 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl |
| 180data_latency=2 |
|
| 179default_p_state=UNDEFINED 180demand_mshr_reserve=1 181eventq_index=0 | 181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 |
| 182hit_latency=2 | |
| 183is_read_only=false 184max_miss_count=0 185mshrs=6 186p_state_clk_gate_bins=20 187p_state_clk_gate_max=1000000000000 188p_state_clk_gate_min=1000 189power_model=Null 190prefetch_on_access=false 191prefetcher=Null 192response_latency=2 193sequential_access=false 194size=32768 195system=system | 184is_read_only=false 185max_miss_count=0 186mshrs=6 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=32768 196system=system |
| 197tag_latency=2 |
|
| 196tags=system.cpu.dcache.tags 197tgts_per_mshr=8 198write_buffers=16 199writeback_clean=true 200cpu_side=system.cpu.dcache_port 201mem_side=system.cpu.toL2Bus.slave[1] 202 203[system.cpu.dcache.tags] 204type=LRU 205assoc=2 206block_size=64 207clk_domain=system.cpu_clk_domain | 198tags=system.cpu.dcache.tags 199tgts_per_mshr=8 200write_buffers=16 201writeback_clean=true 202cpu_side=system.cpu.dcache_port 203mem_side=system.cpu.toL2Bus.slave[1] 204 205[system.cpu.dcache.tags] 206type=LRU 207assoc=2 208block_size=64 209clk_domain=system.cpu_clk_domain |
| 210data_latency=2 |
|
| 208default_p_state=UNDEFINED 209eventq_index=0 | 211default_p_state=UNDEFINED 212eventq_index=0 |
| 210hit_latency=2 | |
| 211p_state_clk_gate_bins=20 212p_state_clk_gate_max=1000000000000 213p_state_clk_gate_min=1000 214power_model=Null 215sequential_access=false 216size=32768 | 213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=32768 |
| 219tag_latency=2 |
|
| 217 218[system.cpu.dstage2_mmu] 219type=ArmStage2MMU 220children=stage2_tlb 221eventq_index=0 222stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 223sys=system 224tlb=system.cpu.dtb --- 86 unchanged lines hidden (view full) --- 311type=OpDesc 312eventq_index=0 313opClass=IprAccess 314opLat=3 315pipelined=true 316 317[system.cpu.fuPool.FUList2] 318type=FUDesc | 220 221[system.cpu.dstage2_mmu] 222type=ArmStage2MMU 223children=stage2_tlb 224eventq_index=0 225stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 226sys=system 227tlb=system.cpu.dtb --- 86 unchanged lines hidden (view full) --- 314type=OpDesc 315eventq_index=0 316opClass=IprAccess 317opLat=3 318pipelined=true 319 320[system.cpu.fuPool.FUList2] 321type=FUDesc |
| 319children=opList | 322children=opList0 opList1 |
| 320count=1 321eventq_index=0 | 323count=1 324eventq_index=0 |
| 322opList=system.cpu.fuPool.FUList2.opList | 325opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 |
| 323 | 326 |
| 324[system.cpu.fuPool.FUList2.opList] | 327[system.cpu.fuPool.FUList2.opList0] |
| 325type=OpDesc 326eventq_index=0 327opClass=MemRead 328opLat=2 329pipelined=true 330 | 328type=OpDesc 329eventq_index=0 330opClass=MemRead 331opLat=2 332pipelined=true 333 |
| 334[system.cpu.fuPool.FUList2.opList1] 335type=OpDesc 336eventq_index=0 337opClass=FloatMemRead 338opLat=2 339pipelined=true 340 |
|
| 331[system.cpu.fuPool.FUList3] 332type=FUDesc | 341[system.cpu.fuPool.FUList3] 342type=FUDesc |
| 333children=opList | 343children=opList0 opList1 |
| 334count=1 335eventq_index=0 | 344count=1 345eventq_index=0 |
| 336opList=system.cpu.fuPool.FUList3.opList | 346opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 |
| 337 | 347 |
| 338[system.cpu.fuPool.FUList3.opList] | 348[system.cpu.fuPool.FUList3.opList0] |
| 339type=OpDesc 340eventq_index=0 341opClass=MemWrite 342opLat=2 343pipelined=true 344 | 349type=OpDesc 350eventq_index=0 351opClass=MemWrite 352opLat=2 353pipelined=true 354 |
| 355[system.cpu.fuPool.FUList3.opList1] 356type=OpDesc 357eventq_index=0 358opClass=FloatMemWrite 359opLat=2 360pipelined=true 361 |
|
| 345[system.cpu.fuPool.FUList4] 346type=FUDesc | 362[system.cpu.fuPool.FUList4] 363type=FUDesc |
| 347children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 | 364children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 |
| 348count=2 349eventq_index=0 | 365count=2 366eventq_index=0 |
| 350opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 | 367opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 |
| 351 352[system.cpu.fuPool.FUList4.opList00] 353type=OpDesc 354eventq_index=0 355opClass=SimdAdd 356opLat=4 357pipelined=true 358 --- 115 unchanged lines hidden (view full) --- 474opClass=SimdFloatMult 475opLat=3 476pipelined=true 477 478[system.cpu.fuPool.FUList4.opList18] 479type=OpDesc 480eventq_index=0 481opClass=SimdFloatMultAcc | 368 369[system.cpu.fuPool.FUList4.opList00] 370type=OpDesc 371eventq_index=0 372opClass=SimdAdd 373opLat=4 374pipelined=true 375 --- 115 unchanged lines hidden (view full) --- 491opClass=SimdFloatMult 492opLat=3 493pipelined=true 494 495[system.cpu.fuPool.FUList4.opList18] 496type=OpDesc 497eventq_index=0 498opClass=SimdFloatMultAcc |
| 482opLat=1 | 499opLat=5 |
| 483pipelined=true 484 485[system.cpu.fuPool.FUList4.opList19] 486type=OpDesc 487eventq_index=0 488opClass=SimdFloatSqrt 489opLat=9 490pipelined=true --- 35 unchanged lines hidden (view full) --- 526 527[system.cpu.fuPool.FUList4.opList25] 528type=OpDesc 529eventq_index=0 530opClass=FloatMult 531opLat=4 532pipelined=true 533 | 500pipelined=true 501 502[system.cpu.fuPool.FUList4.opList19] 503type=OpDesc 504eventq_index=0 505opClass=SimdFloatSqrt 506opLat=9 507pipelined=true --- 35 unchanged lines hidden (view full) --- 543 544[system.cpu.fuPool.FUList4.opList25] 545type=OpDesc 546eventq_index=0 547opClass=FloatMult 548opLat=4 549pipelined=true 550 |
| 551[system.cpu.fuPool.FUList4.opList26] 552type=OpDesc 553eventq_index=0 554opClass=FloatMultAcc 555opLat=5 556pipelined=true 557 558[system.cpu.fuPool.FUList4.opList27] 559type=OpDesc 560eventq_index=0 561opClass=FloatMisc 562opLat=3 563pipelined=true 564 |
|
| 534[system.cpu.icache] 535type=Cache 536children=tags 537addr_ranges=0:18446744073709551615:0:0:0:0 538assoc=2 539clk_domain=system.cpu_clk_domain 540clusivity=mostly_incl | 565[system.cpu.icache] 566type=Cache 567children=tags 568addr_ranges=0:18446744073709551615:0:0:0:0 569assoc=2 570clk_domain=system.cpu_clk_domain 571clusivity=mostly_incl |
| 572data_latency=1 |
|
| 541default_p_state=UNDEFINED 542demand_mshr_reserve=1 543eventq_index=0 | 573default_p_state=UNDEFINED 574demand_mshr_reserve=1 575eventq_index=0 |
| 544hit_latency=1 | |
| 545is_read_only=true 546max_miss_count=0 547mshrs=2 548p_state_clk_gate_bins=20 549p_state_clk_gate_max=1000000000000 550p_state_clk_gate_min=1000 551power_model=Null 552prefetch_on_access=false 553prefetcher=Null 554response_latency=1 555sequential_access=false 556size=32768 557system=system | 576is_read_only=true 577max_miss_count=0 578mshrs=2 579p_state_clk_gate_bins=20 580p_state_clk_gate_max=1000000000000 581p_state_clk_gate_min=1000 582power_model=Null 583prefetch_on_access=false 584prefetcher=Null 585response_latency=1 586sequential_access=false 587size=32768 588system=system |
| 589tag_latency=1 |
|
| 558tags=system.cpu.icache.tags 559tgts_per_mshr=8 560write_buffers=8 561writeback_clean=true 562cpu_side=system.cpu.icache_port 563mem_side=system.cpu.toL2Bus.slave[0] 564 565[system.cpu.icache.tags] 566type=LRU 567assoc=2 568block_size=64 569clk_domain=system.cpu_clk_domain | 590tags=system.cpu.icache.tags 591tgts_per_mshr=8 592write_buffers=8 593writeback_clean=true 594cpu_side=system.cpu.icache_port 595mem_side=system.cpu.toL2Bus.slave[0] 596 597[system.cpu.icache.tags] 598type=LRU 599assoc=2 600block_size=64 601clk_domain=system.cpu_clk_domain |
| 602data_latency=1 |
|
| 570default_p_state=UNDEFINED 571eventq_index=0 | 603default_p_state=UNDEFINED 604eventq_index=0 |
| 572hit_latency=1 | |
| 573p_state_clk_gate_bins=20 574p_state_clk_gate_max=1000000000000 575p_state_clk_gate_min=1000 576power_model=Null 577sequential_access=false 578size=32768 | 605p_state_clk_gate_bins=20 606p_state_clk_gate_max=1000000000000 607p_state_clk_gate_min=1000 608power_model=Null 609sequential_access=false 610size=32768 |
| 611tag_latency=1 |
|
| 579 580[system.cpu.interrupts] 581type=ArmInterrupts 582eventq_index=0 583 584[system.cpu.isa] 585type=ArmISA 586decoderFlavour=Generic 587eventq_index=0 588fpsid=1090793632 589id_aa64afr0_el1=0 590id_aa64afr1_el1=0 591id_aa64dfr0_el1=1052678 592id_aa64dfr1_el1=0 593id_aa64isar0_el1=0 594id_aa64isar1_el1=0 595id_aa64mmfr0_el1=15728642 596id_aa64mmfr1_el1=0 | 612 613[system.cpu.interrupts] 614type=ArmInterrupts 615eventq_index=0 616 617[system.cpu.isa] 618type=ArmISA 619decoderFlavour=Generic 620eventq_index=0 621fpsid=1090793632 622id_aa64afr0_el1=0 623id_aa64afr1_el1=0 624id_aa64dfr0_el1=1052678 625id_aa64dfr1_el1=0 626id_aa64isar0_el1=0 627id_aa64isar1_el1=0 628id_aa64mmfr0_el1=15728642 629id_aa64mmfr1_el1=0 |
| 597id_aa64pfr0_el1=34 598id_aa64pfr1_el1=0 | |
| 599id_isar0=34607377 600id_isar1=34677009 601id_isar2=555950401 602id_isar3=17899825 603id_isar4=268501314 604id_isar5=0 605id_mmfr0=270536963 606id_mmfr1=0 607id_mmfr2=19070976 608id_mmfr3=34611729 | 630id_isar0=34607377 631id_isar1=34677009 632id_isar2=555950401 633id_isar3=17899825 634id_isar4=268501314 635id_isar5=0 636id_mmfr0=270536963 637id_mmfr1=0 638id_mmfr2=19070976 639id_mmfr3=34611729 |
| 609id_pfr0=49 610id_pfr1=4113 | |
| 611midr=1091551472 612pmu=Null 613system=system 614 615[system.cpu.istage2_mmu] 616type=ArmStage2MMU 617children=stage2_tlb 618eventq_index=0 --- 46 unchanged lines hidden (view full) --- 665 666[system.cpu.l2cache] 667type=Cache 668children=prefetcher tags 669addr_ranges=0:18446744073709551615:0:0:0:0 670assoc=16 671clk_domain=system.cpu_clk_domain 672clusivity=mostly_excl | 640midr=1091551472 641pmu=Null 642system=system 643 644[system.cpu.istage2_mmu] 645type=ArmStage2MMU 646children=stage2_tlb 647eventq_index=0 --- 46 unchanged lines hidden (view full) --- 694 695[system.cpu.l2cache] 696type=Cache 697children=prefetcher tags 698addr_ranges=0:18446744073709551615:0:0:0:0 699assoc=16 700clk_domain=system.cpu_clk_domain 701clusivity=mostly_excl |
| 702data_latency=12 |
|
| 673default_p_state=UNDEFINED 674demand_mshr_reserve=1 675eventq_index=0 | 703default_p_state=UNDEFINED 704demand_mshr_reserve=1 705eventq_index=0 |
| 676hit_latency=12 | |
| 677is_read_only=false 678max_miss_count=0 679mshrs=16 680p_state_clk_gate_bins=20 681p_state_clk_gate_max=1000000000000 682p_state_clk_gate_min=1000 683power_model=Null 684prefetch_on_access=true 685prefetcher=system.cpu.l2cache.prefetcher 686response_latency=12 687sequential_access=false 688size=1048576 689system=system | 706is_read_only=false 707max_miss_count=0 708mshrs=16 709p_state_clk_gate_bins=20 710p_state_clk_gate_max=1000000000000 711p_state_clk_gate_min=1000 712power_model=Null 713prefetch_on_access=true 714prefetcher=system.cpu.l2cache.prefetcher 715response_latency=12 716sequential_access=false 717size=1048576 718system=system |
| 719tag_latency=12 |
|
| 690tags=system.cpu.l2cache.tags 691tgts_per_mshr=8 692write_buffers=8 693writeback_clean=false 694cpu_side=system.cpu.toL2Bus.master[0] 695mem_side=system.membus.slave[1] 696 697[system.cpu.l2cache.prefetcher] --- 26 unchanged lines hidden (view full) --- 724thresh_conf=4 725use_master_id=true 726 727[system.cpu.l2cache.tags] 728type=RandomRepl 729assoc=16 730block_size=64 731clk_domain=system.cpu_clk_domain | 720tags=system.cpu.l2cache.tags 721tgts_per_mshr=8 722write_buffers=8 723writeback_clean=false 724cpu_side=system.cpu.toL2Bus.master[0] 725mem_side=system.membus.slave[1] 726 727[system.cpu.l2cache.prefetcher] --- 26 unchanged lines hidden (view full) --- 754thresh_conf=4 755use_master_id=true 756 757[system.cpu.l2cache.tags] 758type=RandomRepl 759assoc=16 760block_size=64 761clk_domain=system.cpu_clk_domain |
| 762data_latency=12 |
|
| 732default_p_state=UNDEFINED 733eventq_index=0 | 763default_p_state=UNDEFINED 764eventq_index=0 |
| 734hit_latency=12 | |
| 735p_state_clk_gate_bins=20 736p_state_clk_gate_max=1000000000000 737p_state_clk_gate_min=1000 738power_model=Null 739sequential_access=false 740size=1048576 | 765p_state_clk_gate_bins=20 766p_state_clk_gate_max=1000000000000 767p_state_clk_gate_min=1000 768power_model=Null 769sequential_access=false 770size=1048576 |
| 771tag_latency=12 |
|
| 741 742[system.cpu.toL2Bus] 743type=CoherentXBar 744children=snoop_filter 745clk_domain=system.cpu_clk_domain 746default_p_state=UNDEFINED 747eventq_index=0 748forward_latency=0 --- 19 unchanged lines hidden (view full) --- 768max_capacity=8388608 769system=system 770 771[system.cpu.tracer] 772type=ExeTracer 773eventq_index=0 774 775[system.cpu.workload] | 772 773[system.cpu.toL2Bus] 774type=CoherentXBar 775children=snoop_filter 776clk_domain=system.cpu_clk_domain 777default_p_state=UNDEFINED 778eventq_index=0 779forward_latency=0 --- 19 unchanged lines hidden (view full) --- 799max_capacity=8388608 800system=system 801 802[system.cpu.tracer] 803type=ExeTracer 804eventq_index=0 805 806[system.cpu.workload] |
| 776type=LiveProcess | 807type=Process |
| 777cmd=perlbmk -I. -I lib mdred.makerand.pl 778cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing 779drivers= 780egid=100 781env= 782errout=cerr 783euid=100 784eventq_index=0 | 808cmd=perlbmk -I. -I lib mdred.makerand.pl 809cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing 810drivers= 811egid=100 812env= 813errout=cerr 814euid=100 815eventq_index=0 |
| 785executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk | 816executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk |
| 786gid=100 787input=cin 788kvmInSE=false 789max_stack_size=67108864 790output=cout | 817gid=100 818input=cin 819kvmInSE=false 820max_stack_size=67108864 821output=cout |
| 822pgid=100 |
|
| 791pid=100 | 823pid=100 |
| 792ppid=99 | 824ppid=0 |
| 793simpoint=0 794system=system 795uid=100 796useArchPT=false 797 798[system.cpu_clk_domain] 799type=SrcClockDomain 800clock=500 --- 130 unchanged lines hidden --- | 825simpoint=0 826system=system 827uid=100 828useArchPT=false 829 830[system.cpu_clk_domain] 831type=SrcClockDomain 832clock=500 --- 130 unchanged lines hidden --- |