1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 51 unchanged lines hidden (view full) --- 60LQEntries=16 61LSQCheckLoads=true 62LSQDepCheckShift=0 63SQEntries=16 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred |
68cacheStorePorts=200 |
69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 --- 59 unchanged lines hidden (view full) --- 136smtLSQThreshold=100 137smtNumFetchingThreads=1 138smtROBPolicy=Partitioned 139smtROBThreshold=100 140socket_id=0 141squashWidth=8 142store_set_clear_period=250000 143switched_out=false |
144syscallRetryLatency=10000 |
145system=system 146tracer=system.cpu.tracer 147trapLatency=13 148wbWidth=8 149workload=system.cpu.workload 150dcache_port=system.cpu.dcache.cpu_side 151icache_port=system.cpu.icache.cpu_side 152 --- 19 unchanged lines hidden (view full) --- 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl |
180data_latency=2 |
181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 |
184is_read_only=false 185max_miss_count=0 186mshrs=6 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=32768 196system=system |
197tag_latency=2 |
198tags=system.cpu.dcache.tags 199tgts_per_mshr=8 200write_buffers=16 201writeback_clean=true 202cpu_side=system.cpu.dcache_port 203mem_side=system.cpu.toL2Bus.slave[1] 204 205[system.cpu.dcache.tags] 206type=LRU 207assoc=2 208block_size=64 209clk_domain=system.cpu_clk_domain |
210data_latency=2 |
211default_p_state=UNDEFINED 212eventq_index=0 |
213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=32768 |
219tag_latency=2 |
220 221[system.cpu.dstage2_mmu] 222type=ArmStage2MMU 223children=stage2_tlb 224eventq_index=0 225stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 226sys=system 227tlb=system.cpu.dtb --- 86 unchanged lines hidden (view full) --- 314type=OpDesc 315eventq_index=0 316opClass=IprAccess 317opLat=3 318pipelined=true 319 320[system.cpu.fuPool.FUList2] 321type=FUDesc |
322children=opList0 opList1 |
323count=1 324eventq_index=0 |
325opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 |
326 |
327[system.cpu.fuPool.FUList2.opList0] |
328type=OpDesc 329eventq_index=0 330opClass=MemRead 331opLat=2 332pipelined=true 333 |
334[system.cpu.fuPool.FUList2.opList1] 335type=OpDesc 336eventq_index=0 337opClass=FloatMemRead 338opLat=2 339pipelined=true 340 |
341[system.cpu.fuPool.FUList3] 342type=FUDesc |
343children=opList0 opList1 |
344count=1 345eventq_index=0 |
346opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 |
347 |
348[system.cpu.fuPool.FUList3.opList0] |
349type=OpDesc 350eventq_index=0 351opClass=MemWrite 352opLat=2 353pipelined=true 354 |
355[system.cpu.fuPool.FUList3.opList1] 356type=OpDesc 357eventq_index=0 358opClass=FloatMemWrite 359opLat=2 360pipelined=true 361 |
362[system.cpu.fuPool.FUList4] 363type=FUDesc |
364children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 |
365count=2 366eventq_index=0 |
367opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 |
368 369[system.cpu.fuPool.FUList4.opList00] 370type=OpDesc 371eventq_index=0 372opClass=SimdAdd 373opLat=4 374pipelined=true 375 --- 115 unchanged lines hidden (view full) --- 491opClass=SimdFloatMult 492opLat=3 493pipelined=true 494 495[system.cpu.fuPool.FUList4.opList18] 496type=OpDesc 497eventq_index=0 498opClass=SimdFloatMultAcc |
499opLat=5 |
500pipelined=true 501 502[system.cpu.fuPool.FUList4.opList19] 503type=OpDesc 504eventq_index=0 505opClass=SimdFloatSqrt 506opLat=9 507pipelined=true --- 35 unchanged lines hidden (view full) --- 543 544[system.cpu.fuPool.FUList4.opList25] 545type=OpDesc 546eventq_index=0 547opClass=FloatMult 548opLat=4 549pipelined=true 550 |
551[system.cpu.fuPool.FUList4.opList26] 552type=OpDesc 553eventq_index=0 554opClass=FloatMultAcc 555opLat=5 556pipelined=true 557 558[system.cpu.fuPool.FUList4.opList27] 559type=OpDesc 560eventq_index=0 561opClass=FloatMisc 562opLat=3 563pipelined=true 564 |
565[system.cpu.icache] 566type=Cache 567children=tags 568addr_ranges=0:18446744073709551615:0:0:0:0 569assoc=2 570clk_domain=system.cpu_clk_domain 571clusivity=mostly_incl |
572data_latency=1 |
573default_p_state=UNDEFINED 574demand_mshr_reserve=1 575eventq_index=0 |
576is_read_only=true 577max_miss_count=0 578mshrs=2 579p_state_clk_gate_bins=20 580p_state_clk_gate_max=1000000000000 581p_state_clk_gate_min=1000 582power_model=Null 583prefetch_on_access=false 584prefetcher=Null 585response_latency=1 586sequential_access=false 587size=32768 588system=system |
589tag_latency=1 |
590tags=system.cpu.icache.tags 591tgts_per_mshr=8 592write_buffers=8 593writeback_clean=true 594cpu_side=system.cpu.icache_port 595mem_side=system.cpu.toL2Bus.slave[0] 596 597[system.cpu.icache.tags] 598type=LRU 599assoc=2 600block_size=64 601clk_domain=system.cpu_clk_domain |
602data_latency=1 |
603default_p_state=UNDEFINED 604eventq_index=0 |
605p_state_clk_gate_bins=20 606p_state_clk_gate_max=1000000000000 607p_state_clk_gate_min=1000 608power_model=Null 609sequential_access=false 610size=32768 |
611tag_latency=1 |
612 613[system.cpu.interrupts] 614type=ArmInterrupts 615eventq_index=0 616 617[system.cpu.isa] 618type=ArmISA 619decoderFlavour=Generic 620eventq_index=0 621fpsid=1090793632 622id_aa64afr0_el1=0 623id_aa64afr1_el1=0 624id_aa64dfr0_el1=1052678 625id_aa64dfr1_el1=0 626id_aa64isar0_el1=0 627id_aa64isar1_el1=0 628id_aa64mmfr0_el1=15728642 629id_aa64mmfr1_el1=0 |
630id_isar0=34607377 631id_isar1=34677009 632id_isar2=555950401 633id_isar3=17899825 634id_isar4=268501314 635id_isar5=0 636id_mmfr0=270536963 637id_mmfr1=0 638id_mmfr2=19070976 639id_mmfr3=34611729 |
640midr=1091551472 641pmu=Null 642system=system 643 644[system.cpu.istage2_mmu] 645type=ArmStage2MMU 646children=stage2_tlb 647eventq_index=0 --- 46 unchanged lines hidden (view full) --- 694 695[system.cpu.l2cache] 696type=Cache 697children=prefetcher tags 698addr_ranges=0:18446744073709551615:0:0:0:0 699assoc=16 700clk_domain=system.cpu_clk_domain 701clusivity=mostly_excl |
702data_latency=12 |
703default_p_state=UNDEFINED 704demand_mshr_reserve=1 705eventq_index=0 |
706is_read_only=false 707max_miss_count=0 708mshrs=16 709p_state_clk_gate_bins=20 710p_state_clk_gate_max=1000000000000 711p_state_clk_gate_min=1000 712power_model=Null 713prefetch_on_access=true 714prefetcher=system.cpu.l2cache.prefetcher 715response_latency=12 716sequential_access=false 717size=1048576 718system=system |
719tag_latency=12 |
720tags=system.cpu.l2cache.tags 721tgts_per_mshr=8 722write_buffers=8 723writeback_clean=false 724cpu_side=system.cpu.toL2Bus.master[0] 725mem_side=system.membus.slave[1] 726 727[system.cpu.l2cache.prefetcher] --- 26 unchanged lines hidden (view full) --- 754thresh_conf=4 755use_master_id=true 756 757[system.cpu.l2cache.tags] 758type=RandomRepl 759assoc=16 760block_size=64 761clk_domain=system.cpu_clk_domain |
762data_latency=12 |
763default_p_state=UNDEFINED 764eventq_index=0 |
765p_state_clk_gate_bins=20 766p_state_clk_gate_max=1000000000000 767p_state_clk_gate_min=1000 768power_model=Null 769sequential_access=false 770size=1048576 |
771tag_latency=12 |
772 773[system.cpu.toL2Bus] 774type=CoherentXBar 775children=snoop_filter 776clk_domain=system.cpu_clk_domain 777default_p_state=UNDEFINED 778eventq_index=0 779forward_latency=0 --- 19 unchanged lines hidden (view full) --- 799max_capacity=8388608 800system=system 801 802[system.cpu.tracer] 803type=ExeTracer 804eventq_index=0 805 806[system.cpu.workload] |
807type=Process |
808cmd=perlbmk -I. -I lib mdred.makerand.pl 809cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing 810drivers= 811egid=100 812env= 813errout=cerr 814euid=100 815eventq_index=0 |
816executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk |
817gid=100 818input=cin 819kvmInSE=false 820max_stack_size=67108864 821output=cout |
822pgid=100 |
823pid=100 |
824ppid=0 |
825simpoint=0 826system=system 827uid=100 828useArchPT=false 829 830[system.cpu_clk_domain] 831type=SrcClockDomain 832clock=500 --- 130 unchanged lines hidden --- |