| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.512877 # Number of seconds simulated 4sim_ticks 512876814500 # Number of ticks simulated 5final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.525654 # Number of seconds simulated 4sim_ticks 525654485500 # Number of ticks simulated 5final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 169706 # Simulator instruction rate (inst/s) 8host_op_rate 208931 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 135858559 # Simulator tick rate (ticks/s) 10host_mem_usage 281524 # Number of bytes of host memory used 11host_seconds 3775.08 # Real time elapsed on the host | 7host_inst_rate 213828 # Simulator instruction rate (inst/s) 8host_op_rate 263250 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 175444467 # Simulator tick rate (ticks/s) 10host_mem_usage 278324 # Number of bytes of host memory used 11host_seconds 2996.13 # Real time elapsed on the host |
| 12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory 19system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory 19system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory |
| 29system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s) | 29system.physmem.bw_read::cpu.inst 312296 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 35145702 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 35457999 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 312296 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 312296 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 8047628 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 8047628 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 8047628 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 312296 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 35145702 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 43505627 # Total bandwidth to/from this memory (bytes/s) |
| 40system.physmem.readReqs 291229 # Number of read requests accepted 41system.physmem.writeReqs 66098 # Number of write requests accepted 42system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue | 40system.physmem.readReqs 291229 # Number of read requests accepted 41system.physmem.writeReqs 66098 # Number of write requests accepted 42system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue |
| 44system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue 46system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM | 44system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue 46system.physmem.bytesWritten 4229248 # Total number of bytes written to DRAM |
| 47system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side | 47system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side |
| 49system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue | 49system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue |
| 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 52system.physmem.perBankRdBursts::0 18285 # Per bank write bursts 53system.physmem.perBankRdBursts::1 18130 # Per bank write bursts 54system.physmem.perBankRdBursts::2 18219 # Per bank write bursts 55system.physmem.perBankRdBursts::3 18177 # Per bank write bursts | 52system.physmem.perBankRdBursts::0 18281 # Per bank write bursts 53system.physmem.perBankRdBursts::1 18133 # Per bank write bursts 54system.physmem.perBankRdBursts::2 18221 # Per bank write bursts 55system.physmem.perBankRdBursts::3 18176 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::4 18285 # Per bank write bursts | 56system.physmem.perBankRdBursts::4 18285 # Per bank write bursts |
| 57system.physmem.perBankRdBursts::5 18413 # Per bank write bursts 58system.physmem.perBankRdBursts::6 18173 # Per bank write bursts 59system.physmem.perBankRdBursts::7 17985 # Per bank write bursts 60system.physmem.perBankRdBursts::8 18026 # Per bank write bursts 61system.physmem.perBankRdBursts::9 18055 # Per bank write bursts 62system.physmem.perBankRdBursts::10 18102 # Per bank write bursts 63system.physmem.perBankRdBursts::11 18206 # Per bank write bursts 64system.physmem.perBankRdBursts::12 18220 # Per bank write bursts 65system.physmem.perBankRdBursts::13 18274 # Per bank write bursts 66system.physmem.perBankRdBursts::14 18073 # Per bank write bursts 67system.physmem.perBankRdBursts::15 18262 # Per bank write bursts | 57system.physmem.perBankRdBursts::5 18412 # Per bank write bursts 58system.physmem.perBankRdBursts::6 18178 # Per bank write bursts 59system.physmem.perBankRdBursts::7 17990 # Per bank write bursts 60system.physmem.perBankRdBursts::8 18034 # Per bank write bursts 61system.physmem.perBankRdBursts::9 18056 # Per bank write bursts 62system.physmem.perBankRdBursts::10 18101 # Per bank write bursts 63system.physmem.perBankRdBursts::11 18200 # Per bank write bursts 64system.physmem.perBankRdBursts::12 18218 # Per bank write bursts 65system.physmem.perBankRdBursts::13 18271 # Per bank write bursts 66system.physmem.perBankRdBursts::14 18077 # Per bank write bursts 67system.physmem.perBankRdBursts::15 18258 # Per bank write bursts |
| 68system.physmem.perBankWrBursts::0 4171 # Per bank write bursts | 68system.physmem.perBankWrBursts::0 4171 # Per bank write bursts |
| 69system.physmem.perBankWrBursts::1 4098 # Per bank write bursts 70system.physmem.perBankWrBursts::2 4134 # Per bank write bursts | 69system.physmem.perBankWrBursts::1 4099 # Per bank write bursts 70system.physmem.perBankWrBursts::2 4135 # Per bank write bursts |
| 71system.physmem.perBankWrBursts::3 4146 # Per bank write bursts | 71system.physmem.perBankWrBursts::3 4146 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::4 4223 # Per bank write bursts | 72system.physmem.perBankWrBursts::4 4224 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::5 4224 # Per bank write bursts | 73system.physmem.perBankWrBursts::5 4224 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::6 4173 # Per bank write bursts 75system.physmem.perBankWrBursts::7 4092 # Per bank write bursts 76system.physmem.perBankWrBursts::8 4093 # Per bank write bursts | 74system.physmem.perBankWrBursts::6 4174 # Per bank write bursts 75system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 76system.physmem.perBankWrBursts::8 4096 # Per bank write bursts |
| 77system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 78system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::11 4097 # Per bank write bursts | 77system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 78system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::11 4097 # Per bank write bursts |
| 80system.physmem.perBankWrBursts::12 4095 # Per bank write bursts | 80system.physmem.perBankWrBursts::12 4098 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::14 4096 # Per bank write bursts | 81system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::14 4096 # Per bank write bursts |
| 83system.physmem.perBankWrBursts::15 4138 # Per bank write bursts | 83system.physmem.perBankWrBursts::15 4140 # Per bank write bursts |
| 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 86system.physmem.totGap 512876719500 # Total gap between requests | 86system.physmem.totGap 525654384500 # Total gap between requests |
| 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 291229 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 66098 # Write request sizes (log2) | 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 291229 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 66098 # Write request sizes (log2) |
| 101system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::0 290516 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 889 # What write queue length does an incoming req see |
| 150system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see | 150system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see | 151system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 4019 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 4020 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 4022 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 4021 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 4019 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 166system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 197system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes | 197system.physmem.bytesPerActivate::samples 102767 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 222.307005 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 147.372317 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 261.848294 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 36138 35.16% 35.16% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 41898 40.77% 75.93% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 13163 12.81% 88.74% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 1012 0.98% 89.73% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 489 0.48% 90.20% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 1030 1.00% 91.21% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 399 0.39% 91.59% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 484 0.47% 92.07% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 8154 7.93% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 102767 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 48.497387 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 34.151985 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 506.429034 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 4017 99.95% 99.95% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes | 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads 226system.physmem.totQLat 2756382250 # Total ticks spent queuing 227system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM 228system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers 229system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst | 218system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.442399 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.422334 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.830212 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 3130 77.88% 77.88% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 889 22.12% 100.00% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads 226system.physmem.totQLat 15538679500 # Total ticks spent queuing 227system.physmem.totMemAccLat 20992885750 # Total ticks spent from burst creation until serviced by the DRAM 228system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers 229system.physmem.avgQLat 53417.53 # Average queueing delay per DRAM burst |
| 230system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 230system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 231system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst 232system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s 233system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s 234system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s 235system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s | 231system.physmem.avgMemAccLat 72167.53 # Average memory access latency per DRAM burst 232system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s 233system.physmem.avgWrBW 8.05 # Average achieved write bandwidth in MiByte/s 234system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s 235system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s |
| 236system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 236system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 237system.physmem.busUtil 0.35 # Data bus utilization in percentage | 237system.physmem.busUtil 0.34 # Data bus utilization in percentage |
| 238system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads 239system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 240system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 238system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads 239system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 240system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 241system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing 242system.physmem.readRowHits 194946 # Number of row buffer hits during reads 243system.physmem.writeRowHits 51576 # Number of row buffer hits during writes 244system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads 245system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes 246system.physmem.avgGap 1435314.77 # Average gap between requests 247system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined 248system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ) 249system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ) 250system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ) 251system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) 252system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) 253system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ) 254system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ) 255system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ) 256system.physmem_0.averagePower 694.111511 # Core power per rank (mW) 257system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states 258system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states 259system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 260system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states 261system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 262system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ) 263system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ) 264system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) 265system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) 266system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) 267system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ) 268system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ) 269system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ) 270system.physmem_1.averagePower 694.035798 # Core power per rank (mW) 271system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states 272system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states 273system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 274system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states 275system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 276system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states 277system.cpu.branchPred.lookups 147261658 # Number of BP lookups | 241system.physmem.avgWrQLen 19.65 # Average write queue length when enqueuing 242system.physmem.readRowHits 202495 # Number of row buffer hits during reads 243system.physmem.writeRowHits 51707 # Number of row buffer hits during writes 244system.physmem.readRowHitRate 69.61 # Row buffer hit rate for reads 245system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes 246system.physmem.avgGap 1471073.79 # Average gap between requests 247system.physmem.pageHitRate 71.21 # Row buffer hit rate, read and write combined 248system.physmem_0.actEnergy 367124520 # Energy for activate commands per rank (pJ) 249system.physmem_0.preEnergy 195116130 # Energy for precharge commands per rank (pJ) 250system.physmem_0.readEnergy 1040126640 # Energy for read commands per rank (pJ) 251system.physmem_0.writeEnergy 173653740 # Energy for write commands per rank (pJ) 252system.physmem_0.refreshEnergy 28870255440.000008 # Energy for refresh commands per rank (pJ) 253system.physmem_0.actBackEnergy 8266537290 # Energy for active background per rank (pJ) 254system.physmem_0.preBackEnergy 1634065440 # Energy for precharge background per rank (pJ) 255system.physmem_0.actPowerDownEnergy 57360982710 # Energy for active power-down per rank (pJ) 256system.physmem_0.prePowerDownEnergy 51276223200 # Energy for precharge power-down per rank (pJ) 257system.physmem_0.selfRefreshEnergy 64953258915 # Energy for self refresh per rank (pJ) 258system.physmem_0.totalEnergy 214157919585 # Total energy per rank (pJ) 259system.physmem_0.averagePower 407.411950 # Core power per rank (mW) 260system.physmem_0.totalIdleTime 503225172750 # Total Idle time Per DRAM Rank 261system.physmem_0.memoryStateTime::IDLE 3206676000 # Time in different power states 262system.physmem_0.memoryStateTime::REF 12282762000 # Time in different power states 263system.physmem_0.memoryStateTime::SREF 243901523000 # Time in different power states 264system.physmem_0.memoryStateTime::PRE_PDN 133531907000 # Time in different power states 265system.physmem_0.memoryStateTime::ACT 6939814000 # Time in different power states 266system.physmem_0.memoryStateTime::ACT_PDN 125791803500 # Time in different power states 267system.physmem_1.actEnergy 366660420 # Energy for activate commands per rank (pJ) 268system.physmem_1.preEnergy 194884635 # Energy for precharge commands per rank (pJ) 269system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ) 270system.physmem_1.writeEnergy 171294300 # Energy for write commands per rank (pJ) 271system.physmem_1.refreshEnergy 28737493200.000008 # Energy for refresh commands per rank (pJ) 272system.physmem_1.actBackEnergy 8178131430 # Energy for active background per rank (pJ) 273system.physmem_1.preBackEnergy 1630074720 # Energy for precharge background per rank (pJ) 274system.physmem_1.actPowerDownEnergy 56926536120 # Energy for active power-down per rank (pJ) 275system.physmem_1.prePowerDownEnergy 51134645280 # Energy for precharge power-down per rank (pJ) 276system.physmem_1.selfRefreshEnergy 65306601210 # Energy for self refresh per rank (pJ) 277system.physmem_1.totalEnergy 213703234155 # Total energy per rank (pJ) 278system.physmem_1.averagePower 406.546781 # Core power per rank (mW) 279system.physmem_1.totalIdleTime 503430400500 # Total Idle time Per DRAM Rank 280system.physmem_1.memoryStateTime::IDLE 3200172000 # Time in different power states 281system.physmem_1.memoryStateTime::REF 12226116000 # Time in different power states 282system.physmem_1.memoryStateTime::SREF 245428473250 # Time in different power states 283system.physmem_1.memoryStateTime::PRE_PDN 133163073250 # Time in different power states 284system.physmem_1.memoryStateTime::ACT 6797797000 # Time in different power states 285system.physmem_1.memoryStateTime::ACT_PDN 124838854000 # Time in different power states 286system.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states 287system.cpu.branchPred.lookups 147261657 # Number of BP lookups |
| 278system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted 279system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect | 288system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect |
| 280system.cpu.branchPred.BTBLookups 89949366 # Number of BTB lookups 281system.cpu.branchPred.BTBHits 63294628 # Number of BTB hits | 290system.cpu.branchPred.BTBLookups 89949365 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 63294627 # Number of BTB hits |
| 282system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 283system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage 284system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target. 285system.cpu.branchPred.RASInCorrect 1312 # Number of incorrect RAS predictions. 286system.cpu.branchPred.indirectLookups 15995155 # Number of indirect predictor lookups. 287system.cpu.branchPred.indirectHits 15988941 # Number of indirect target hits. 288system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. 289system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. 290system.cpu_clk_domain.clock 500 # Clock period in ticks | 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 293system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 1312 # Number of incorrect RAS predictions. 296system.cpu.branchPred.indirectLookups 15995155 # Number of indirect predictor lookups. 297system.cpu.branchPred.indirectHits 15988941 # Number of indirect target hits. 298system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. 299system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. 300system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 291system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 301system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 292system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 313system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 314system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 315system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 316system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 317system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 318system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 319system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 320system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 302system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 323system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 324system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 325system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 326system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 327system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 328system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 329system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 330system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 321system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 331system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 322system.cpu.dtb.walker.walks 0 # Table walker walks requested 323system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 343system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 344system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 345system.cpu.dtb.read_accesses 0 # DTB read accesses 346system.cpu.dtb.write_accesses 0 # DTB write accesses 347system.cpu.dtb.inst_accesses 0 # ITB inst accesses 348system.cpu.dtb.hits 0 # DTB hits 349system.cpu.dtb.misses 0 # DTB misses 350system.cpu.dtb.accesses 0 # DTB accesses | 332system.cpu.dtb.walker.walks 0 # Table walker walks requested 333system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 353system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 354system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.dtb.read_accesses 0 # DTB read accesses 356system.cpu.dtb.write_accesses 0 # DTB write accesses 357system.cpu.dtb.inst_accesses 0 # ITB inst accesses 358system.cpu.dtb.hits 0 # DTB hits 359system.cpu.dtb.misses 0 # DTB misses 360system.cpu.dtb.accesses 0 # DTB accesses |
| 351system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 361system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 352system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 373system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 375system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 376system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 377system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 378system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 379system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 380system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 362system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 383system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 384system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 386system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 387system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 388system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 389system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 390system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 381system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 391system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 382system.cpu.itb.walker.walks 0 # Table walker walks requested 383system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 384system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 404system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 405system.cpu.itb.read_accesses 0 # DTB read accesses 406system.cpu.itb.write_accesses 0 # DTB write accesses 407system.cpu.itb.inst_accesses 0 # ITB inst accesses 408system.cpu.itb.hits 0 # DTB hits 409system.cpu.itb.misses 0 # DTB misses 410system.cpu.itb.accesses 0 # DTB accesses 411system.cpu.workload.num_syscalls 673 # Number of system calls | 392system.cpu.itb.walker.walks 0 # Table walker walks requested 393system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 414system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 415system.cpu.itb.read_accesses 0 # DTB read accesses 416system.cpu.itb.write_accesses 0 # DTB write accesses 417system.cpu.itb.inst_accesses 0 # ITB inst accesses 418system.cpu.itb.hits 0 # DTB hits 419system.cpu.itb.misses 0 # DTB misses 420system.cpu.itb.accesses 0 # DTB accesses 421system.cpu.workload.num_syscalls 673 # Number of system calls |
| 412system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states 413system.cpu.numCycles 1025753629 # number of cpu cycles simulated | 422system.cpu.pwrStateResidencyTicks::ON 525654485500 # Cumulative time (in ticks) in various power states 423system.cpu.numCycles 1051308971 # number of cpu cycles simulated |
| 414system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 415system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 416system.cpu.committedInsts 640655085 # Number of instructions committed 417system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed | 424system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 425system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 426system.cpu.committedInsts 640655085 # Number of instructions committed 427system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed |
| 418system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit | 428system.cpu.discardedOps 8621767 # Number of ops (including micro ops) which were discarded before commit |
| 419system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 429system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 420system.cpu.cpi 1.601101 # CPI: cycles per instruction 421system.cpu.ipc 0.624570 # IPC: instructions per cycle | 430system.cpu.cpi 1.640991 # CPI: cycles per instruction 431system.cpu.ipc 0.609388 # IPC: instructions per cycle |
| 422system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 423system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction 424system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 425system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 426system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 427system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 428system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 429system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 449system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 450system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 451system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 452system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 453system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction 454system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 455system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 456system.cpu.op_class_0::total 788730744 # Class of committed instruction | 432system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 433system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction 434system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 435system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 436system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 437system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 438system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 439system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 459system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 460system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 461system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 462system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 463system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction 464system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 465system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 466system.cpu.op_class_0::total 788730744 # Class of committed instruction |
| 457system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked 458system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped 459system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 467system.cpu.tickCycles 955911046 # Number of cycles that the object actually ticked 468system.cpu.idleCycles 95397925 # Total number of cycles that the object has spent stopped 469system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 460system.cpu.dcache.tags.replacements 778100 # number of replacements | 470system.cpu.dcache.tags.replacements 778100 # number of replacements |
| 461system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use | 471system.cpu.dcache.tags.tagsinuse 4092.108689 # Cycle average of tags in use |
| 462system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. 463system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. 464system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. | 472system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. 473system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. 474system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. |
| 465system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit. 466system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor 467system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy 468system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy | 475system.cpu.dcache.tags.warmup_cycle 850386500 # Cycle when the warmup percentage was hit. 476system.cpu.dcache.tags.occ_blocks::cpu.data 4092.108689 # Average occupied blocks per requestor 477system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy 478system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy |
| 469system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 470system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id | 479system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 480system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id |
| 471system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 472system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id 473system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id 474system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id | 481system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id 482system.cpu.dcache.tags.age_task_id_blocks_1024::2 970 # Occupied blocks per task id 483system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id 484system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id |
| 475system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 476system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses 477system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses | 485system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 486system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses 487system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses |
| 478system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 488system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 479system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits 480system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits 481system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits 482system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits 483system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits 484system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits 485system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 486system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits --- 8 unchanged lines hidden (view full) --- 495system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses 496system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses 497system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses 498system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses 499system.cpu.dcache.demand_misses::cpu.data 850904 # number of demand (read+write) misses 500system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses 501system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses 502system.cpu.dcache.overall_misses::total 851045 # number of overall misses | 489system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits 490system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits 491system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits 492system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits 493system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits 494system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits 495system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 496system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits --- 8 unchanged lines hidden (view full) --- 505system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses 506system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses 507system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses 508system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses 509system.cpu.dcache.demand_misses::cpu.data 850904 # number of demand (read+write) misses 510system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses 511system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses 512system.cpu.dcache.overall_misses::total 851045 # number of overall misses |
| 503system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles 504system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles 505system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles 506system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles 507system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles 508system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles 509system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles 510system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles | 513system.cpu.dcache.ReadReq_miss_latency::cpu.data 37269485500 # number of ReadReq miss cycles 514system.cpu.dcache.ReadReq_miss_latency::total 37269485500 # number of ReadReq miss cycles 515system.cpu.dcache.WriteReq_miss_latency::cpu.data 10946218000 # number of WriteReq miss cycles 516system.cpu.dcache.WriteReq_miss_latency::total 10946218000 # number of WriteReq miss cycles 517system.cpu.dcache.demand_miss_latency::cpu.data 48215703500 # number of demand (read+write) miss cycles 518system.cpu.dcache.demand_miss_latency::total 48215703500 # number of demand (read+write) miss cycles 519system.cpu.dcache.overall_miss_latency::cpu.data 48215703500 # number of overall miss cycles 520system.cpu.dcache.overall_miss_latency::total 48215703500 # number of overall miss cycles |
| 511system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) 512system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) 513system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 514system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 515system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) 516system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) 517system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 518system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 527system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 528system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 529system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses 530system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses 531system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 # miss rate for demand accesses 532system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses 533system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses 534system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses | 521system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) 522system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) 523system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 524system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 525system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) 526system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) 527system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 528system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 537system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 538system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 539system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses 540system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses 541system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 # miss rate for demand accesses 542system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses 543system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses 544system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses |
| 535system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency 536system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency 537system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency 538system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency 539system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency 540system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency 541system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency 542system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency | 545system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072 # average ReadReq miss latency 546system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072 # average ReadReq miss latency 547system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752 # average WriteReq miss latency 548system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752 # average WriteReq miss latency 549system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129 # average overall miss latency 550system.cpu.dcache.demand_avg_miss_latency::total 56664.093129 # average overall miss latency 551system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098 # average overall miss latency 552system.cpu.dcache.overall_avg_miss_latency::total 56654.705098 # average overall miss latency |
| 543system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 544system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 545system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 546system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 547system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 548system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 549system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks 550system.cpu.dcache.writebacks::total 88688 # number of writebacks --- 10 unchanged lines hidden (view full) --- 561system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 562system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 563system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 564system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 565system.cpu.dcache.demand_mshr_misses::cpu.data 782057 # number of demand (read+write) MSHR misses 566system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses 567system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses 568system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses | 553system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 554system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 555system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 556system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 557system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 558system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 559system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks 560system.cpu.dcache.writebacks::total 88688 # number of writebacks --- 10 unchanged lines hidden (view full) --- 571system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 572system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 573system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 574system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 575system.cpu.dcache.demand_mshr_misses::cpu.data 782057 # number of demand (read+write) MSHR misses 576system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses 577system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses 578system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses |
| 569system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles 570system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles 571system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles 572system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles 573system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles 574system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles 575system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles 576system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles 577system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles 578system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles | 579system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36547770500 # number of ReadReq MSHR miss cycles 580system.cpu.dcache.ReadReq_mshr_miss_latency::total 36547770500 # number of ReadReq MSHR miss cycles 581system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5489520000 # number of WriteReq MSHR miss cycles 582system.cpu.dcache.WriteReq_mshr_miss_latency::total 5489520000 # number of WriteReq MSHR miss cycles 583system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles 584system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles 585system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42037290500 # number of demand (read+write) MSHR miss cycles 586system.cpu.dcache.demand_mshr_miss_latency::total 42037290500 # number of demand (read+write) MSHR miss cycles 587system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42039092500 # number of overall MSHR miss cycles 588system.cpu.dcache.overall_mshr_miss_latency::total 42039092500 # number of overall MSHR miss cycles |
| 579system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 580system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 581system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 582system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 583system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses 584system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses 585system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 586system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 587system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 588system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses | 589system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 590system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 591system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 592system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 593system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses 594system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses 595system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 596system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 597system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 598system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses |
| 589system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency 590system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency 591system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency 592system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency 593system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency 594system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency 595system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency 596system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency 597system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency 598system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency 599system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 599system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680 # average ReadReq mshr miss latency 600system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680 # average ReadReq mshr miss latency 601system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540 # average WriteReq mshr miss latency 602system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540 # average WriteReq mshr miss latency 603system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency 604system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency 605system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959 # average overall mshr miss latency 606system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959 # average overall mshr miss latency 607system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703 # average overall mshr miss latency 608system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703 # average overall mshr miss latency 609system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 600system.cpu.icache.tags.replacements 24885 # number of replacements | 610system.cpu.icache.tags.replacements 24885 # number of replacements |
| 601system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use 602system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks. | 611system.cpu.icache.tags.tagsinuse 1711.889727 # Cycle average of tags in use 612system.cpu.icache.tags.total_refs 257789639 # Total number of references to valid blocks. |
| 603system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. | 613system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. |
| 604system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks. | 614system.cpu.icache.tags.avg_refs 9678.241440 # Average number of references to valid blocks. |
| 605system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 615system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 606system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor 607system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy 608system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy | 616system.cpu.icache.tags.occ_blocks::cpu.inst 1711.889727 # Average occupied blocks per requestor 617system.cpu.icache.tags.occ_percent::cpu.inst 0.835884 # Average percentage of cache occupancy 618system.cpu.icache.tags.occ_percent::total 0.835884 # Average percentage of cache occupancy |
| 609system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id 610system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 611system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id 613system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id | 619system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id 620system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 621system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 622system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id 623system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id |
| 614system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses 615system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses 616system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states 617system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits 618system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits 619system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits 620system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits 621system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits 622system.cpu.icache.overall_hits::total 257789646 # number of overall hits | 624system.cpu.icache.tags.tag_accesses 515659188 # Number of tag accesses 625system.cpu.icache.tags.data_accesses 515659188 # Number of data accesses 626system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states 627system.cpu.icache.ReadReq_hits::cpu.inst 257789639 # number of ReadReq hits 628system.cpu.icache.ReadReq_hits::total 257789639 # number of ReadReq hits 629system.cpu.icache.demand_hits::cpu.inst 257789639 # number of demand (read+write) hits 630system.cpu.icache.demand_hits::total 257789639 # number of demand (read+write) hits 631system.cpu.icache.overall_hits::cpu.inst 257789639 # number of overall hits 632system.cpu.icache.overall_hits::total 257789639 # number of overall hits |
| 623system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses 624system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses 625system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses 626system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses 627system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses 628system.cpu.icache.overall_misses::total 26637 # number of overall misses | 633system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses 634system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses 635system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses 636system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses 637system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses 638system.cpu.icache.overall_misses::total 26637 # number of overall misses |
| 629system.cpu.icache.ReadReq_miss_latency::cpu.inst 518689000 # number of ReadReq miss cycles 630system.cpu.icache.ReadReq_miss_latency::total 518689000 # number of ReadReq miss cycles 631system.cpu.icache.demand_miss_latency::cpu.inst 518689000 # number of demand (read+write) miss cycles 632system.cpu.icache.demand_miss_latency::total 518689000 # number of demand (read+write) miss cycles 633system.cpu.icache.overall_miss_latency::cpu.inst 518689000 # number of overall miss cycles 634system.cpu.icache.overall_miss_latency::total 518689000 # number of overall miss cycles 635system.cpu.icache.ReadReq_accesses::cpu.inst 257816283 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses) 637system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses 638system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses 639system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses 640system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses | 639system.cpu.icache.ReadReq_miss_latency::cpu.inst 539890500 # number of ReadReq miss cycles 640system.cpu.icache.ReadReq_miss_latency::total 539890500 # number of ReadReq miss cycles 641system.cpu.icache.demand_miss_latency::cpu.inst 539890500 # number of demand (read+write) miss cycles 642system.cpu.icache.demand_miss_latency::total 539890500 # number of demand (read+write) miss cycles 643system.cpu.icache.overall_miss_latency::cpu.inst 539890500 # number of overall miss cycles 644system.cpu.icache.overall_miss_latency::total 539890500 # number of overall miss cycles 645system.cpu.icache.ReadReq_accesses::cpu.inst 257816276 # number of ReadReq accesses(hits+misses) 646system.cpu.icache.ReadReq_accesses::total 257816276 # number of ReadReq accesses(hits+misses) 647system.cpu.icache.demand_accesses::cpu.inst 257816276 # number of demand (read+write) accesses 648system.cpu.icache.demand_accesses::total 257816276 # number of demand (read+write) accesses 649system.cpu.icache.overall_accesses::cpu.inst 257816276 # number of overall (read+write) accesses 650system.cpu.icache.overall_accesses::total 257816276 # number of overall (read+write) accesses |
| 641system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses 642system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses 643system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses 644system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses 645system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses 646system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses | 651system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses 652system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses 653system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses 654system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses 655system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses 656system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses |
| 647system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency 648system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency 649system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency 650system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency | 657system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392 # average ReadReq miss latency 658system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392 # average ReadReq miss latency 659system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency 660system.cpu.icache.demand_avg_miss_latency::total 20268.442392 # average overall miss latency 661system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency 662system.cpu.icache.overall_avg_miss_latency::total 20268.442392 # average overall miss latency |
| 653system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 658system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.icache.writebacks::writebacks 24885 # number of writebacks 660system.cpu.icache.writebacks::total 24885 # number of writebacks 661system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26637 # number of ReadReq MSHR misses 662system.cpu.icache.ReadReq_mshr_misses::total 26637 # number of ReadReq MSHR misses 663system.cpu.icache.demand_mshr_misses::cpu.inst 26637 # number of demand (read+write) MSHR misses 664system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses 665system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses 666system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses | 663system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 664system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 665system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 666system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 667system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 668system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 669system.cpu.icache.writebacks::writebacks 24885 # number of writebacks 670system.cpu.icache.writebacks::total 24885 # number of writebacks 671system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26637 # number of ReadReq MSHR misses 672system.cpu.icache.ReadReq_mshr_misses::total 26637 # number of ReadReq MSHR misses 673system.cpu.icache.demand_mshr_misses::cpu.inst 26637 # number of demand (read+write) MSHR misses 674system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses 675system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses 676system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses |
| 667system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles 668system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles 669system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles 670system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles 671system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles 672system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles | 677system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 513254500 # number of ReadReq MSHR miss cycles 678system.cpu.icache.ReadReq_mshr_miss_latency::total 513254500 # number of ReadReq MSHR miss cycles 679system.cpu.icache.demand_mshr_miss_latency::cpu.inst 513254500 # number of demand (read+write) MSHR miss cycles 680system.cpu.icache.demand_mshr_miss_latency::total 513254500 # number of demand (read+write) MSHR miss cycles 681system.cpu.icache.overall_mshr_miss_latency::cpu.inst 513254500 # number of overall MSHR miss cycles 682system.cpu.icache.overall_mshr_miss_latency::total 513254500 # number of overall MSHR miss cycles |
| 673system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses 674system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses 675system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses 676system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses 677system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses 678system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses | 683system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses 684system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses 685system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses 686system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses 687system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses 688system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses |
| 679system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency 680system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency 681system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency 682system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency 683system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency 684system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency 685system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 689system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934 # average ReadReq mshr miss latency 690system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934 # average ReadReq mshr miss latency 691system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency 692system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency 693system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency 694system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency 695system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 686system.cpu.l2cache.tags.replacements 258837 # number of replacements | 696system.cpu.l2cache.tags.replacements 258837 # number of replacements |
| 687system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use | 697system.cpu.l2cache.tags.tagsinuse 32651.524409 # Cycle average of tags in use |
| 688system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks. 689system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks. 690system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks. | 698system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks. 699system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks. 700system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks. |
| 691system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit. 692system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor 693system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor 694system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor 695system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy 696system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy 697system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy 698system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy | 701system.cpu.l2cache.tags.warmup_cycle 3958369000 # Cycle when the warmup percentage was hit. 702system.cpu.l2cache.tags.occ_blocks::writebacks 41.514151 # Average occupied blocks per requestor 703system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.268254 # Average occupied blocks per requestor 704system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004 # Average occupied blocks per requestor 705system.cpu.l2cache.tags.occ_percent::writebacks 0.001267 # Average percentage of cache occupancy 706system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002724 # Average percentage of cache occupancy 707system.cpu.l2cache.tags.occ_percent::cpu.data 0.992454 # Average percentage of cache occupancy 708system.cpu.l2cache.tags.occ_percent::total 0.996445 # Average percentage of cache occupancy |
| 699system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 700system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 701system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id | 709system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 710system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 711system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id |
| 702system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id | 712system.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id 713system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id 714system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29221 # Occupied blocks per task id |
| 705system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 706system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses 707system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses | 715system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 716system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses 717system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses |
| 708system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 718system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 709system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits 710system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits 711system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits 712system.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits 713system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 714system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 715system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits 716system.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 729system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses 730system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses 731system.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses 732system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses 733system.cpu.l2cache.demand_misses::total 291260 # number of demand (read+write) misses 734system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses 735system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses 736system.cpu.l2cache.overall_misses::total 291260 # number of overall misses | 719system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits 720system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits 721system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits 722system.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits 723system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 724system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 725system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits 726system.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 739system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses 740system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses 741system.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses 742system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses 743system.cpu.l2cache.demand_misses::total 291260 # number of demand (read+write) misses 744system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses 745system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses 746system.cpu.l2cache.overall_misses::total 291260 # number of overall misses |
| 737system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles 738system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles 739system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles 740system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles 741system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles 742system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles 743system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles 744system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles 745system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles 746system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles 747system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles 748system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles | 747system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5351609000 # number of ReadExReq miss cycles 748system.cpu.l2cache.ReadExReq_miss_latency::total 5351609000 # number of ReadExReq miss cycles 749system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 219318000 # number of ReadCleanReq miss cycles 750system.cpu.l2cache.ReadCleanReq_miss_latency::total 219318000 # number of ReadCleanReq miss cycles 751system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30330402000 # number of ReadSharedReq miss cycles 752system.cpu.l2cache.ReadSharedReq_miss_latency::total 30330402000 # number of ReadSharedReq miss cycles 753system.cpu.l2cache.demand_miss_latency::cpu.inst 219318000 # number of demand (read+write) miss cycles 754system.cpu.l2cache.demand_miss_latency::cpu.data 35682011000 # number of demand (read+write) miss cycles 755system.cpu.l2cache.demand_miss_latency::total 35901329000 # number of demand (read+write) miss cycles 756system.cpu.l2cache.overall_miss_latency::cpu.inst 219318000 # number of overall miss cycles 757system.cpu.l2cache.overall_miss_latency::cpu.data 35682011000 # number of overall miss cycles 758system.cpu.l2cache.overall_miss_latency::total 35901329000 # number of overall miss cycles |
| 749system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses) 750system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses) 751system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) 752system.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses) 753system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 754system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 755system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26637 # number of ReadCleanReq accesses(hits+misses) 756system.cpu.l2cache.ReadCleanReq_accesses::total 26637 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 769system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses 770system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses 771system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses 772system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses 773system.cpu.l2cache.demand_miss_rate::total 0.360099 # miss rate for demand accesses 774system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses 775system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses 776system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses | 759system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses) 760system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses) 761system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) 762system.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses) 763system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 764system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 765system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26637 # number of ReadCleanReq accesses(hits+misses) 766system.cpu.l2cache.ReadCleanReq_accesses::total 26637 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 779system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses 780system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses 781system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses 782system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses 783system.cpu.l2cache.demand_miss_rate::total 0.360099 # miss rate for demand accesses 784system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses 785system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses 786system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses |
| 777system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency 778system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency 779system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency 780system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency 781system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency 782system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency 783system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency 784system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency 785system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency 786system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency 787system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency 788system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency | 787system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789 # average ReadExReq miss latency 788system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789 # average ReadExReq miss latency 789system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191 # average ReadCleanReq miss latency 790system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191 # average ReadCleanReq miss latency 791system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313 # average ReadSharedReq miss latency 792system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313 # average ReadSharedReq miss latency 793system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency 794system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency 795system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489 # average overall miss latency 796system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency 797system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency 798system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489 # average overall miss latency |
| 789system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 790system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 791system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 792system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 793system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 794system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 795system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 796system.cpu.l2cache.writebacks::total 66098 # number of writebacks --- 14 unchanged lines hidden (view full) --- 811system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses 812system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses 813system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses 814system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses 815system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses 816system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses 817system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses 818system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses | 799system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 800system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 801system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 802system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 803system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 804system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 805system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 806system.cpu.l2cache.writebacks::total 66098 # number of writebacks --- 14 unchanged lines hidden (view full) --- 821system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses 822system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses 823system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses 824system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses 825system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses 826system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses 827system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses 828system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses |
| 819system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles 820system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles 821system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles 822system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles 823system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles 824system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles 825system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles 826system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles 827system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles 828system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles 829system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles 830system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles | 829system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4690699000 # number of ReadExReq MSHR miss cycles 830system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4690699000 # number of ReadExReq MSHR miss cycles 831system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193386000 # number of ReadCleanReq MSHR miss cycles 832system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193386000 # number of ReadCleanReq MSHR miss cycles 833system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28102659500 # number of ReadSharedReq MSHR miss cycles 834system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28102659500 # number of ReadSharedReq MSHR miss cycles 835system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193386000 # number of demand (read+write) MSHR miss cycles 836system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32793358500 # number of demand (read+write) MSHR miss cycles 837system.cpu.l2cache.demand_mshr_miss_latency::total 32986744500 # number of demand (read+write) MSHR miss cycles 838system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193386000 # number of overall MSHR miss cycles 839system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32793358500 # number of overall MSHR miss cycles 840system.cpu.l2cache.overall_mshr_miss_latency::total 32986744500 # number of overall MSHR miss cycles |
| 831system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 832system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 833system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses 834system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses 835system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses 836system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses 837system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses 838system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses 839system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses 840system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses 841system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses 842system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses | 841system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 842system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 843system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses 844system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses 845system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses 846system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses 847system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses 848system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses 849system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses 850system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses 851system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses 852system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses |
| 843system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency 844system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency 845system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency 846system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency 847system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency 848system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency 849system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency 850system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency 851system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency 852system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency 853system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency 854system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency | 853system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789 # average ReadExReq mshr miss latency 854system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789 # average ReadExReq mshr miss latency 855system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070 # average ReadCleanReq mshr miss latency 856system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070 # average ReadCleanReq mshr miss latency 857system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138 # average ReadSharedReq mshr miss latency 858system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138 # average ReadSharedReq mshr miss latency 859system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency 860system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency 861system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency 862system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency 863system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency 864system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency |
| 855system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. 856system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. 857system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 858system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. 859system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 860system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 865system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. 866system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. 867system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 868system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. 869system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 870system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 861system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 871system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 862system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 867system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution --- 23 unchanged lines hidden (view full) --- 893system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) 894system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 895system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter. 896system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data. 897system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 898system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 899system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 900system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 872system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution 875system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution 876system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 877system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution 879system.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution --- 23 unchanged lines hidden (view full) --- 903system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) 904system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 905system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter. 906system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data. 907system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 908system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 909system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 910system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 901system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states | 911system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states |
| 902system.membus.trans_dist::ReadResp 225138 # Transaction distribution 903system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 904system.membus.trans_dist::CleanEvict 190702 # Transaction distribution 905system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 906system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 907system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution 908system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes) 909system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 916system.membus.snoop_fanout::stdev 0 # Request fanout histogram 917system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 918system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram 919system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 920system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 921system.membus.snoop_fanout::min_value 0 # Request fanout histogram 922system.membus.snoop_fanout::max_value 0 # Request fanout histogram 923system.membus.snoop_fanout::total 291229 # Request fanout histogram | 912system.membus.trans_dist::ReadResp 225138 # Transaction distribution 913system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 914system.membus.trans_dist::CleanEvict 190702 # Transaction distribution 915system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 916system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 917system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution 918system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes) 919system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 926system.membus.snoop_fanout::stdev 0 # Request fanout histogram 927system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 928system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram 929system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 930system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 931system.membus.snoop_fanout::min_value 0 # Request fanout histogram 932system.membus.snoop_fanout::max_value 0 # Request fanout histogram 933system.membus.snoop_fanout::total 291229 # Request fanout histogram |
| 924system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks) | 934system.membus.reqLayer0.occupancy 917205000 # Layer occupancy (ticks) |
| 925system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) | 935system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 926system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks) | 936system.membus.respLayer1.occupancy 1553500250 # Layer occupancy (ticks) |
| 927system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 928 929---------- End Simulation Statistics ---------- | 937system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 938 939---------- End Simulation Statistics ---------- |