Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt

stats.txt (11507:be6065c1d8d2)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.489946 # Number of seconds simulated 4sim_ticks 489945697500 # Number of ticks simulated 5final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.489946 # Number of seconds simulated 4sim_ticks 489945697500 # Number of ticks simulated 5final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 152136 # Simulator instruction rate (inst/s) 8host_op_rate 187299 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 116346895 # Simulator tick rate (ticks/s) 10host_mem_usage 275904 # Number of bytes of host memory used 11host_seconds 4211.08 # Real time elapsed on the host	7host_inst_rate 287135 # Simulator instruction rate (inst/s) 8host_op_rate 353501 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 219588415 # Simulator tick rate (ticks/s) 10host_mem_usage 322476 # Number of bytes of host memory used 11host_seconds 2231.20 # Real time elapsed on the host
12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory --- 243 unchanged lines hidden (view full) --- 267system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ) 268system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ) 269system.physmem_1.averagePower 695.442012 # Core power per rank (mW) 270system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states 271system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states 272system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 273system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states 274system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states	17system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory 19system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory --- 243 unchanged lines hidden (view full) --- 268system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ) 269system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ) 270system.physmem_1.averagePower 695.442012 # Core power per rank (mW) 271system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states 272system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states 273system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 274system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states 275system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
	276system.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
275system.cpu.branchPred.lookups 144591747 # Number of BP lookups 276system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted 277system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect 278system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups 279system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits 280system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 281system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage 282system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target. 283system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions. 284system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups. 285system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits. 286system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses. 287system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches. 288system.cpu_clk_domain.clock 500 # Clock period in ticks	277system.cpu.branchPred.lookups 144591747 # Number of BP lookups 278system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted 279system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect 280system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups 281system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits 282system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 283system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage 284system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target. 285system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions. 286system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups. 287system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits. 288system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses. 289system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches. 290system.cpu_clk_domain.clock 500 # Clock period in ticks
	291system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
289system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 310system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 311system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 312system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 313system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 314system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 315system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 316system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 317system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	292system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 313system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 314system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 315system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 316system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 317system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 318system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 319system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 320system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	321system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
318system.cpu.dtb.walker.walks 0 # Table walker walks requested 319system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 339system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 340system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 341system.cpu.dtb.read_accesses 0 # DTB read accesses 342system.cpu.dtb.write_accesses 0 # DTB write accesses 343system.cpu.dtb.inst_accesses 0 # ITB inst accesses 344system.cpu.dtb.hits 0 # DTB hits 345system.cpu.dtb.misses 0 # DTB misses 346system.cpu.dtb.accesses 0 # DTB accesses	322system.cpu.dtb.walker.walks 0 # Table walker walks requested 323system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 343system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 344system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 345system.cpu.dtb.read_accesses 0 # DTB read accesses 346system.cpu.dtb.write_accesses 0 # DTB write accesses 347system.cpu.dtb.inst_accesses 0 # ITB inst accesses 348system.cpu.dtb.hits 0 # DTB hits 349system.cpu.dtb.misses 0 # DTB misses 350system.cpu.dtb.accesses 0 # DTB accesses
	351system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
347system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 368system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 369system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 370system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 371system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 372system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 373system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 374system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 375system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	352system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 373system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 375system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 376system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 377system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 378system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 379system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 380system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	381system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
376system.cpu.itb.walker.walks 0 # Table walker walks requested 377system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 398system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 399system.cpu.itb.read_accesses 0 # DTB read accesses 400system.cpu.itb.write_accesses 0 # DTB write accesses 401system.cpu.itb.inst_accesses 0 # ITB inst accesses 402system.cpu.itb.hits 0 # DTB hits 403system.cpu.itb.misses 0 # DTB misses 404system.cpu.itb.accesses 0 # DTB accesses 405system.cpu.workload.num_syscalls 673 # Number of system calls	382system.cpu.itb.walker.walks 0 # Table walker walks requested 383system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 384system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 404system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 405system.cpu.itb.read_accesses 0 # DTB read accesses 406system.cpu.itb.write_accesses 0 # DTB write accesses 407system.cpu.itb.inst_accesses 0 # ITB inst accesses 408system.cpu.itb.hits 0 # DTB hits 409system.cpu.itb.misses 0 # DTB misses 410system.cpu.itb.accesses 0 # DTB accesses 411system.cpu.workload.num_syscalls 673 # Number of system calls
	412system.cpu.pwrStateResidencyTicks::ON 489945697500 # Cumulative time (in ticks) in various power states
406system.cpu.numCycles 979891395 # number of cpu cycles simulated 407system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 408system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 409system.cpu.committedInsts 640655085 # Number of instructions committed 410system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed 411system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit 412system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 413system.cpu.cpi 1.529515 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 444system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 445system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 446system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction 447system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 448system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 449system.cpu.op_class_0::total 788730744 # Class of committed instruction 450system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked 451system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped	413system.cpu.numCycles 979891395 # number of cpu cycles simulated 414system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 415system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 416system.cpu.committedInsts 640655085 # Number of instructions committed 417system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed 418system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit 419system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 420system.cpu.cpi 1.529515 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 451system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 452system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 453system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction 454system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 455system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 456system.cpu.op_class_0::total 788730744 # Class of committed instruction 457system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked 458system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped
	459system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
452system.cpu.dcache.tags.replacements 778302 # number of replacements 453system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use 454system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks. 455system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks. 456system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks. 457system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit. 458system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor 459system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy 460system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy 461system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 462system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 463system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 464system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id 465system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id 466system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id 467system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 468system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses 469system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses	460system.cpu.dcache.tags.replacements 778302 # number of replacements 461system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use 462system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks. 463system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks. 464system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks. 465system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit. 466system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor 467system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy 468system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy 469system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 470system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 471system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 472system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id 473system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id 474system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id 475system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 476system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses 477system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses
	478system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
470system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits 471system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits 472system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits 473system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits 474system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits 475system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits 476system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 477system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 582system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency 583system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency 584system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency 585system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency 586system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency 587system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency 588system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency 589system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency	479system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits 480system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits 481system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits 482system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits 483system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits 484system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits 485system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 486system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 591system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency 592system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency 593system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency 594system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency 595system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency 596system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency 597system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency 598system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency
	599system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
590system.cpu.icache.tags.replacements 24859 # number of replacements 591system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use 592system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks. 593system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks. 594system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks. 595system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 596system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor 597system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy 598system.cpu.icache.tags.occ_percent::total 0.836373 # Average percentage of cache occupancy 599system.cpu.icache.tags.occ_task_id_blocks::1024 1753 # Occupied blocks per task id 600system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 601system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 602system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 # Occupied blocks per task id 603system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id 604system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses 605system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses	600system.cpu.icache.tags.replacements 24859 # number of replacements 601system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use 602system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks. 603system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks. 604system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks. 605system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 606system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor 607system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy 608system.cpu.icache.tags.occ_percent::total 0.836373 # Average percentage of cache occupancy 609system.cpu.icache.tags.occ_task_id_blocks::1024 1753 # Occupied blocks per task id 610system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 611system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 # Occupied blocks per task id 613system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id 614system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses 615system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses
	616system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
606system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits 607system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits 608system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits 609system.cpu.icache.demand_hits::total 252585994 # number of demand (read+write) hits 610system.cpu.icache.overall_hits::cpu.inst 252585994 # number of overall hits 611system.cpu.icache.overall_hits::total 252585994 # number of overall hits 612system.cpu.icache.ReadReq_misses::cpu.inst 26613 # number of ReadReq misses 613system.cpu.icache.ReadReq_misses::total 26613 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 666system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses 667system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency 669system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency 670system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency 671system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency 672system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency 673system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency	617system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits 618system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits 619system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits 620system.cpu.icache.demand_hits::total 252585994 # number of demand (read+write) hits 621system.cpu.icache.overall_hits::cpu.inst 252585994 # number of overall hits 622system.cpu.icache.overall_hits::total 252585994 # number of overall hits 623system.cpu.icache.ReadReq_misses::cpu.inst 26613 # number of ReadReq misses 624system.cpu.icache.ReadReq_misses::total 26613 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 677system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses 678system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses 679system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency 680system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency 681system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency 682system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency 683system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency 684system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
	685system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
674system.cpu.l2cache.tags.replacements 258808 # number of replacements 675system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use 676system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks. 677system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks. 678system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks. 679system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 680system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor 681system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 688system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 689system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 690system.cpu.l2cache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id 691system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3136 # Occupied blocks per task id 692system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 # Occupied blocks per task id 693system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id 694system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses 695system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses	686system.cpu.l2cache.tags.replacements 258808 # number of replacements 687system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use 688system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks. 689system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks. 690system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks. 691system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 692system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor 693system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 700system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 701system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 702system.cpu.l2cache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3136 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 # Occupied blocks per task id 705system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id 706system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses 707system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses
	708system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
696system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits 697system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits 698system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits 699system.cpu.l2cache.WritebackClean_hits::total 23528 # number of WritebackClean hits 700system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 701system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 702system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24049 # number of ReadCleanReq hits 703system.cpu.l2cache.ReadCleanReq_hits::total 24049 # number of ReadCleanReq hits --- 136 unchanged lines hidden (view full) --- 840system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency 841system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency 842system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter. 843system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 844system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 845system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. 846system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 847system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	709system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits 710system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits 711system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits 712system.cpu.l2cache.WritebackClean_hits::total 23528 # number of WritebackClean hits 713system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 714system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 715system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24049 # number of ReadCleanReq hits 716system.cpu.l2cache.ReadCleanReq_hits::total 24049 # number of ReadCleanReq hits --- 136 unchanged lines hidden (view full) --- 853system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency 854system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency 855system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter. 856system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 857system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 858system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. 859system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 860system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	861system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
848system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution 849system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution 850system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution 851system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution 852system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 853system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 854system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution 855system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 872system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 873system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram 874system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks) 875system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 876system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks) 877system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 878system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks) 879system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)	862system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 867system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 886system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 887system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram 888system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks) 889system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 890system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks) 891system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 892system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks) 893system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
	894system.membus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
880system.membus.trans_dist::ReadResp 225121 # Transaction distribution 881system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 882system.membus.trans_dist::CleanEvict 190682 # Transaction distribution 883system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 884system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 885system.membus.trans_dist::ReadSharedReq 225121 # Transaction distribution 886system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839204 # Packet count per connected master and slave (bytes) 887system.membus.pkt_count::total 839204 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden ---	895system.membus.trans_dist::ReadResp 225121 # Transaction distribution 896system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 897system.membus.trans_dist::CleanEvict 190682 # Transaction distribution 898system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 899system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 900system.membus.trans_dist::ReadSharedReq 225121 # Transaction distribution 901system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839204 # Packet count per connected master and slave (bytes) 902system.membus.pkt_count::total 839204 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.489946 # Number of seconds simulated
4sim_ticks 489945697500 # Number of ticks simulated
5final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 152136 # Simulator instruction rate (inst/s)
8host_op_rate 187299 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 116346895 # Simulator tick rate (ticks/s)
10host_mem_usage 275904 # Number of bytes of host memory used
11host_seconds 4211.08 # Real time elapsed on the host

7host_inst_rate 287135 # Simulator instruction rate (inst/s)
8host_op_rate 353501 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 219588415 # Simulator tick rate (ticks/s)
10host_mem_usage 322476 # Number of bytes of host memory used
11host_seconds 2231.20 # Real time elapsed on the host

12sim_insts 640655085 # Number of instructions simulated
13sim_ops 788730744 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory
18system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory

--- 243 unchanged lines hidden (view full) ---

267system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ)
268system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ)
269system.physmem_1.averagePower 695.442012 # Core power per rank (mW)
270system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states
271system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states
272system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
273system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states
274system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

17system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory
19system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
23system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory

--- 243 unchanged lines hidden (view full) ---

268system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ)
269system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ)
270system.physmem_1.averagePower 695.442012 # Core power per rank (mW)
271system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states
272system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states
273system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
274system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states
275system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

276system.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

275system.cpu.branchPred.lookups 144591747 # Number of BP lookups
276system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted
277system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect
278system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups
279system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits
280system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
281system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage
282system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target.
283system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions.
284system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups.
285system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits.
286system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses.
287system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches.
288system.cpu_clk_domain.clock 500 # Clock period in ticks

277system.cpu.branchPred.lookups 144591747 # Number of BP lookups
278system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted
279system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect
280system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups
281system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits
282system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
283system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage
284system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target.
285system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions.
286system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups.
287system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits.
288system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses.
289system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches.
290system.cpu_clk_domain.clock 500 # Clock period in ticks

291system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

289system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

310system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
311system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
312system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
313system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
314system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
315system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
316system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
317system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

292system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

313system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
314system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
315system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
316system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
317system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
318system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
319system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
320system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

321system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

318system.cpu.dtb.walker.walks 0 # Table walker walks requested
319system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
320system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
321system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
322system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
323system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
324system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
325system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

339system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
340system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
341system.cpu.dtb.read_accesses 0 # DTB read accesses
342system.cpu.dtb.write_accesses 0 # DTB write accesses
343system.cpu.dtb.inst_accesses 0 # ITB inst accesses
344system.cpu.dtb.hits 0 # DTB hits
345system.cpu.dtb.misses 0 # DTB misses
346system.cpu.dtb.accesses 0 # DTB accesses

322system.cpu.dtb.walker.walks 0 # Table walker walks requested
323system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
324system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
325system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
326system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
327system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
328system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
329system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

343system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
344system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
345system.cpu.dtb.read_accesses 0 # DTB read accesses
346system.cpu.dtb.write_accesses 0 # DTB write accesses
347system.cpu.dtb.inst_accesses 0 # ITB inst accesses
348system.cpu.dtb.hits 0 # DTB hits
349system.cpu.dtb.misses 0 # DTB misses
350system.cpu.dtb.accesses 0 # DTB accesses

351system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

347system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

368system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
369system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
370system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
371system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
372system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
373system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
374system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
375system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

352system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

373system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
374system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
375system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
376system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
377system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
378system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
379system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
380system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

381system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

376system.cpu.itb.walker.walks 0 # Table walker walks requested
377system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
378system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
379system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
380system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
381system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
382system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
383system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

398system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
399system.cpu.itb.read_accesses 0 # DTB read accesses
400system.cpu.itb.write_accesses 0 # DTB write accesses
401system.cpu.itb.inst_accesses 0 # ITB inst accesses
402system.cpu.itb.hits 0 # DTB hits
403system.cpu.itb.misses 0 # DTB misses
404system.cpu.itb.accesses 0 # DTB accesses
405system.cpu.workload.num_syscalls 673 # Number of system calls

382system.cpu.itb.walker.walks 0 # Table walker walks requested
383system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
384system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
385system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
386system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
387system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
388system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
389system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

404system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
405system.cpu.itb.read_accesses 0 # DTB read accesses
406system.cpu.itb.write_accesses 0 # DTB write accesses
407system.cpu.itb.inst_accesses 0 # ITB inst accesses
408system.cpu.itb.hits 0 # DTB hits
409system.cpu.itb.misses 0 # DTB misses
410system.cpu.itb.accesses 0 # DTB accesses
411system.cpu.workload.num_syscalls 673 # Number of system calls

412system.cpu.pwrStateResidencyTicks::ON 489945697500 # Cumulative time (in ticks) in various power states

406system.cpu.numCycles 979891395 # number of cpu cycles simulated
407system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
408system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
409system.cpu.committedInsts 640655085 # Number of instructions committed
410system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed
411system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit
412system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
413system.cpu.cpi 1.529515 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

444system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
445system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction
446system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction
447system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
448system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
449system.cpu.op_class_0::total 788730744 # Class of committed instruction
450system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked
451system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped

413system.cpu.numCycles 979891395 # number of cpu cycles simulated
414system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
415system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
416system.cpu.committedInsts 640655085 # Number of instructions committed
417system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed
418system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit
419system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
420system.cpu.cpi 1.529515 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

451system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
452system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction
453system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction
454system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
455system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
456system.cpu.op_class_0::total 788730744 # Class of committed instruction
457system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked
458system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped

459system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

452system.cpu.dcache.tags.replacements 778302 # number of replacements
453system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use
454system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks.
455system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks.
456system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks.
457system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit.
458system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor
459system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy
460system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy
461system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
462system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
463system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
464system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id
465system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id
466system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id
467system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
468system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses
469system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses

460system.cpu.dcache.tags.replacements 778302 # number of replacements
461system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use
462system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks.
463system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks.
464system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks.
465system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit.
466system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor
467system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy
468system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy
469system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
470system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
471system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
472system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id
473system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id
474system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id
475system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
476system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses
477system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses

478system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

470system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits
471system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits
472system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits
473system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits
474system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits
475system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits
476system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
477system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

582system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency
583system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency
584system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency
585system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency
586system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency
587system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency
588system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency
589system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency

479system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits
480system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits
481system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits
482system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits
483system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits
484system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits
485system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
486system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits

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591system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency
592system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency
593system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency
594system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency
595system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency
596system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency
597system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency
598system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency

599system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

590system.cpu.icache.tags.replacements 24859 # number of replacements
591system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use
592system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks.
593system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks.
594system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks.
595system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
596system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor
597system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy
598system.cpu.icache.tags.occ_percent::total 0.836373 # Average percentage of cache occupancy
599system.cpu.icache.tags.occ_task_id_blocks::1024 1753 # Occupied blocks per task id
600system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
601system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
602system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 # Occupied blocks per task id
603system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id
604system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses
605system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses

600system.cpu.icache.tags.replacements 24859 # number of replacements
601system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use
602system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks.
603system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks.
604system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks.
605system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
606system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor
607system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy
608system.cpu.icache.tags.occ_percent::total 0.836373 # Average percentage of cache occupancy
609system.cpu.icache.tags.occ_task_id_blocks::1024 1753 # Occupied blocks per task id
610system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
611system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
612system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 # Occupied blocks per task id
613system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id
614system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses
615system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses

616system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

606system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits
607system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits
608system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits
609system.cpu.icache.demand_hits::total 252585994 # number of demand (read+write) hits
610system.cpu.icache.overall_hits::cpu.inst 252585994 # number of overall hits
611system.cpu.icache.overall_hits::total 252585994 # number of overall hits
612system.cpu.icache.ReadReq_misses::cpu.inst 26613 # number of ReadReq misses
613system.cpu.icache.ReadReq_misses::total 26613 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

666system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses
667system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses
668system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency
669system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency
670system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
671system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
672system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
673system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency

617system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits
618system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits
619system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits
620system.cpu.icache.demand_hits::total 252585994 # number of demand (read+write) hits
621system.cpu.icache.overall_hits::cpu.inst 252585994 # number of overall hits
622system.cpu.icache.overall_hits::total 252585994 # number of overall hits
623system.cpu.icache.ReadReq_misses::cpu.inst 26613 # number of ReadReq misses
624system.cpu.icache.ReadReq_misses::total 26613 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

677system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses
678system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses
679system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency
680system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency
681system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
682system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
683system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
684system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency

685system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

674system.cpu.l2cache.tags.replacements 258808 # number of replacements
675system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use
676system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks.
677system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks.
678system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks.
679system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
680system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor
681system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor

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688system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
689system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
690system.cpu.l2cache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id
691system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3136 # Occupied blocks per task id
692system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 # Occupied blocks per task id
693system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
694system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses
695system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses

686system.cpu.l2cache.tags.replacements 258808 # number of replacements
687system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use
688system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks.
689system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks.
690system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks.
691system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
692system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor
693system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

700system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
701system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
702system.cpu.l2cache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id
703system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3136 # Occupied blocks per task id
704system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 # Occupied blocks per task id
705system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
706system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses
707system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses

708system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

696system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits
697system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits
698system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits
699system.cpu.l2cache.WritebackClean_hits::total 23528 # number of WritebackClean hits
700system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits
701system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
702system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24049 # number of ReadCleanReq hits
703system.cpu.l2cache.ReadCleanReq_hits::total 24049 # number of ReadCleanReq hits

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840system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency
841system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency
842system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter.
843system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
844system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
845system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter.
846system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
847system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

709system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits
710system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits
711system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits
712system.cpu.l2cache.WritebackClean_hits::total 23528 # number of WritebackClean hits
713system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits
714system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
715system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24049 # number of ReadCleanReq hits
716system.cpu.l2cache.ReadCleanReq_hits::total 24049 # number of ReadCleanReq hits

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853system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency
854system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency
855system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter.
856system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
857system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
858system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter.
859system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
860system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

861system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states

848system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution
849system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution
850system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution
851system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution
852system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution
853system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution
854system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution
855system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution

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872system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
873system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram
874system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks)
875system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
876system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks)
877system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
878system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks)
879system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)

862system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution
863system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution
864system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution
865system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution
866system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution
867system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution
868system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution
869system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution

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886system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
887system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram
888system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks)
889system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
890system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks)
891system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
892system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks)
893system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)

894system.membus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states