| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.489946 # Number of seconds simulated 4sim_ticks 489945697500 # Number of ticks simulated 5final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.489946 # Number of seconds simulated 4sim_ticks 489945697500 # Number of ticks simulated 5final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 199747 # Simulator instruction rate (inst/s) 8host_op_rate 245915 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 152758149 # Simulator tick rate (ticks/s) 10host_mem_usage 280032 # Number of bytes of host memory used 11host_seconds 3207.33 # Real time elapsed on the host | 7host_inst_rate 235921 # Simulator instruction rate (inst/s) 8host_op_rate 290449 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 180421993 # Simulator tick rate (ticks/s) 10host_mem_usage 280028 # Number of bytes of host memory used 11host_seconds 2715.55 # Real time elapsed on the host |
| 12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory --- 512 unchanged lines hidden (view full) --- 532system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627 # average overall miss latency 533system.cpu.dcache.overall_avg_miss_latency::total 41444.605627 # average overall miss latency 534system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory --- 512 unchanged lines hidden (view full) --- 532system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627 # average overall miss latency 533system.cpu.dcache.overall_avg_miss_latency::total 41444.605627 # average overall miss latency 534system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 540system.cpu.dcache.fast_writes 0 # number of fast writes performed 541system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 542system.cpu.dcache.writebacks::writebacks 88712 # number of writebacks 543system.cpu.dcache.writebacks::total 88712 # number of writebacks 544system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904 # number of ReadReq MSHR hits 545system.cpu.dcache.ReadReq_mshr_hits::total 904 # number of ReadReq MSHR hits 546system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits 547system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits 548system.cpu.dcache.demand_mshr_hits::cpu.data 69293 # number of demand (read+write) MSHR hits 549system.cpu.dcache.demand_mshr_hits::total 69293 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 584system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency 585system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency 586system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency 587system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency 588system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency 589system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency 590system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency 591system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency | 540system.cpu.dcache.writebacks::writebacks 88712 # number of writebacks 541system.cpu.dcache.writebacks::total 88712 # number of writebacks 542system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904 # number of ReadReq MSHR hits 543system.cpu.dcache.ReadReq_mshr_hits::total 904 # number of ReadReq MSHR hits 544system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits 545system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits 546system.cpu.dcache.demand_mshr_hits::cpu.data 69293 # number of demand (read+write) MSHR hits 547system.cpu.dcache.demand_mshr_hits::total 69293 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 582system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency 583system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency 584system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency 585system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency 586system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency 587system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency 588system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency 589system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency |
| 592system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 593system.cpu.icache.tags.replacements 24859 # number of replacements 594system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use 595system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks. 596system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks. 597system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks. 598system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 599system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor 600system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 643system.cpu.icache.overall_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency 644system.cpu.icache.overall_avg_miss_latency::total 19416.431819 # average overall miss latency 645system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 646system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 647system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 648system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 649system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 650system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 590system.cpu.icache.tags.replacements 24859 # number of replacements 591system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use 592system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks. 593system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks. 594system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks. 595system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 596system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor 597system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 640system.cpu.icache.overall_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency 641system.cpu.icache.overall_avg_miss_latency::total 19416.431819 # average overall miss latency 642system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 643system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 645system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 646system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 647system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 651system.cpu.icache.fast_writes 0 # number of fast writes performed 652system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 653system.cpu.icache.writebacks::writebacks 24859 # number of writebacks 654system.cpu.icache.writebacks::total 24859 # number of writebacks 655system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26613 # number of ReadReq MSHR misses 656system.cpu.icache.ReadReq_mshr_misses::total 26613 # number of ReadReq MSHR misses 657system.cpu.icache.demand_mshr_misses::cpu.inst 26613 # number of demand (read+write) MSHR misses 658system.cpu.icache.demand_mshr_misses::total 26613 # number of demand (read+write) MSHR misses 659system.cpu.icache.overall_mshr_misses::cpu.inst 26613 # number of overall MSHR misses 660system.cpu.icache.overall_mshr_misses::total 26613 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 671system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses 672system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses 673system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency 675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency 677system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency | 648system.cpu.icache.writebacks::writebacks 24859 # number of writebacks 649system.cpu.icache.writebacks::total 24859 # number of writebacks 650system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26613 # number of ReadReq MSHR misses 651system.cpu.icache.ReadReq_mshr_misses::total 26613 # number of ReadReq MSHR misses 652system.cpu.icache.demand_mshr_misses::cpu.inst 26613 # number of demand (read+write) MSHR misses 653system.cpu.icache.demand_mshr_misses::total 26613 # number of demand (read+write) MSHR misses 654system.cpu.icache.overall_mshr_misses::cpu.inst 26613 # number of overall MSHR misses 655system.cpu.icache.overall_mshr_misses::total 26613 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 666system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses 667system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency 669system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency 670system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency 671system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency 672system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency 673system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency |
| 679system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 680system.cpu.l2cache.tags.replacements 258808 # number of replacements 681system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use 682system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks. 683system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks. 684system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks. 685system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 686system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor 687system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 780system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency 781system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132 # average overall miss latency 782system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 785system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 786system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 787system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 674system.cpu.l2cache.tags.replacements 258808 # number of replacements 675system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use 676system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks. 677system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks. 678system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks. 679system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 680system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor 681system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 774system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency 775system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132 # average overall miss latency 776system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 777system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 778system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 779system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 780system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 781system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 788system.cpu.l2cache.fast_writes 0 # number of fast writes performed 789system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 790system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 791system.cpu.l2cache.writebacks::total 66098 # number of writebacks 792system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits 793system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 794system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits 795system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits 796system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 797system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits --- 44 unchanged lines hidden (view full) --- 842system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797 # average ReadSharedReq mshr miss latency 843system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797 # average ReadSharedReq mshr miss latency 844system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency 845system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency 846system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency 847system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency 848system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency 849system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency | 782system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 783system.cpu.l2cache.writebacks::total 66098 # number of writebacks 784system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits 785system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 786system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits 787system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits 788system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 789system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits --- 44 unchanged lines hidden (view full) --- 834system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797 # average ReadSharedReq mshr miss latency 835system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797 # average ReadSharedReq mshr miss latency 836system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency 837system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency 838system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency 839system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency 840system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency 841system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency |
| 850system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 851system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter. 852system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 853system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 854system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. 855system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 856system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 857system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution 858system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution --- 57 unchanged lines hidden --- | 842system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter. 843system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 844system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 845system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. 846system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 847system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 848system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution 849system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution --- 57 unchanged lines hidden --- |