| stats.txt (10636:9ac724889705) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.541786 # Number of seconds simulated 4sim_ticks 541786101000 # Number of ticks simulated 5final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.545057 # Number of seconds simulated 4sim_ticks 545056655500 # Number of ticks simulated 5final_tick 545056655500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 115987 # Simulator instruction rate (inst/s) 8host_op_rate 142796 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 98087491 # Simulator tick rate (ticks/s) 10host_mem_usage 309428 # Number of bytes of host memory used 11host_seconds 5523.50 # Real time elapsed on the host | 7host_inst_rate 182072 # Simulator instruction rate (inst/s) 8host_op_rate 224154 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 154902851 # Simulator tick rate (ticks/s) 10host_mem_usage 321108 # Number of bytes of host memory used 11host_seconds 3518.70 # Real time elapsed on the host |
| 12sim_insts 640655084 # Number of instructions simulated 13sim_ops 788730743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 640655084 # Number of instructions simulated 13sim_ops 788730743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18429184 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 164864 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18429248 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18594112 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 164864 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 164864 # Number of instructions bytes read from this memory |
| 21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory | 21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory |
| 23system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 287956 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory | 23system.physmem.num_reads::cpu.inst 2576 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 287957 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 290533 # Number of read requests responded to by this memory |
| 26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory | 26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory |
| 28system.physmem.bw_read::cpu.inst 303943 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 34015609 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 303943 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 34015609 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 290529 # Number of read requests accepted | 28system.physmem.bw_read::cpu.inst 302471 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 33811619 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 34114090 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 302471 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 302471 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 7761160 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 7761160 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 7761160 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 302471 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 33811619 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 41875251 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 290533 # Number of read requests accepted |
| 40system.physmem.writeReqs 66098 # Number of write requests accepted | 40system.physmem.writeReqs 66098 # Number of write requests accepted |
| 41system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue | 41system.physmem.readBursts 290533 # Number of DRAM read bursts, including those serviced by the write queue |
| 42system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue | 42system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue |
| 43system.physmem.bytesReadDRAM 18572736 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue 45system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side | 43system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue 45system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 18594112 # Total read bytes from the system interface side |
| 47system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side | 47system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side |
| 48system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue | 48system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 51system.physmem.perBankRdBursts::0 18289 # Per bank write bursts 52system.physmem.perBankRdBursts::1 18137 # Per bank write bursts 53system.physmem.perBankRdBursts::2 18222 # Per bank write bursts | 51system.physmem.perBankRdBursts::0 18287 # Per bank write bursts 52system.physmem.perBankRdBursts::1 18141 # Per bank write bursts 53system.physmem.perBankRdBursts::2 18224 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::3 18184 # Per bank write bursts | 54system.physmem.perBankRdBursts::3 18184 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::4 18266 # Per bank write bursts 56system.physmem.perBankRdBursts::5 18308 # Per bank write bursts 57system.physmem.perBankRdBursts::6 18094 # Per bank write bursts 58system.physmem.perBankRdBursts::7 17914 # Per bank write bursts 59system.physmem.perBankRdBursts::8 17939 # Per bank write bursts 60system.physmem.perBankRdBursts::9 17962 # Per bank write bursts 61system.physmem.perBankRdBursts::10 18018 # Per bank write bursts 62system.physmem.perBankRdBursts::11 18110 # Per bank write bursts | 55system.physmem.perBankRdBursts::4 18267 # Per bank write bursts 56system.physmem.perBankRdBursts::5 18318 # Per bank write bursts 57system.physmem.perBankRdBursts::6 18100 # Per bank write bursts 58system.physmem.perBankRdBursts::7 17916 # Per bank write bursts 59system.physmem.perBankRdBursts::8 17940 # Per bank write bursts 60system.physmem.perBankRdBursts::9 17966 # Per bank write bursts 61system.physmem.perBankRdBursts::10 18025 # Per bank write bursts 62system.physmem.perBankRdBursts::11 18111 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::12 18143 # Per bank write bursts | 63system.physmem.perBankRdBursts::12 18143 # Per bank write bursts |
| 64system.physmem.perBankRdBursts::13 18270 # Per bank write bursts 65system.physmem.perBankRdBursts::14 18077 # Per bank write bursts 66system.physmem.perBankRdBursts::15 18266 # Per bank write bursts 67system.physmem.perBankWrBursts::0 4174 # Per bank write bursts 68system.physmem.perBankWrBursts::1 4101 # Per bank write bursts 69system.physmem.perBankWrBursts::2 4137 # Per bank write bursts 70system.physmem.perBankWrBursts::3 4147 # Per bank write bursts | 64system.physmem.perBankRdBursts::13 18269 # Per bank write bursts 65system.physmem.perBankRdBursts::14 18078 # Per bank write bursts 66system.physmem.perBankRdBursts::15 18262 # Per bank write bursts 67system.physmem.perBankWrBursts::0 4173 # Per bank write bursts 68system.physmem.perBankWrBursts::1 4099 # Per bank write bursts 69system.physmem.perBankWrBursts::2 4136 # Per bank write bursts 70system.physmem.perBankWrBursts::3 4146 # Per bank write bursts |
| 71system.physmem.perBankWrBursts::4 4225 # Per bank write bursts | 71system.physmem.perBankWrBursts::4 4225 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::5 4225 # Per bank write bursts | 72system.physmem.perBankWrBursts::5 4223 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::6 4171 # Per bank write bursts | 73system.physmem.perBankWrBursts::6 4171 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 75system.physmem.perBankWrBursts::8 4093 # Per bank write bursts | 74system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 75system.physmem.perBankWrBursts::8 4094 # Per bank write bursts |
| 76system.physmem.perBankWrBursts::9 4093 # Per bank write bursts | 76system.physmem.perBankWrBursts::9 4093 # Per bank write bursts |
| 77system.physmem.perBankWrBursts::10 4090 # Per bank write bursts 78system.physmem.perBankWrBursts::11 4094 # Per bank write bursts 79system.physmem.perBankWrBursts::12 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::13 4094 # Per bank write bursts | 77system.physmem.perBankWrBursts::10 4093 # Per bank write bursts 78system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 79system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 80system.physmem.perBankWrBursts::13 4096 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::14 4096 # Per bank write bursts | 81system.physmem.perBankWrBursts::14 4096 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::15 4138 # Per bank write bursts | 82system.physmem.perBankWrBursts::15 4140 # Per bank write bursts |
| 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 541786012500 # Total gap between requests | 85system.physmem.totGap 545056561000 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 290529 # Read request sizes (log2) | 92system.physmem.readPktSize::6 290533 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 66098 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 66098 # Write request sizes (log2) |
| 100system.physmem.rdQLenPdf::0 289803 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::0 289840 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 375 # What read queue length does an incoming req see |
| 102system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 102system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 989 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4006 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4007 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 4007 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 4007 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 4006 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 4006 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 4006 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 4006 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 4006 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 966 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 966 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 4011 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 4009 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 4009 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 4009 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 4009 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see |
| 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 111554 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 204.382452 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 132.554579 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 255.928936 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 47007 42.14% 42.14% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 43571 39.06% 81.20% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 8721 7.82% 89.01% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 769 0.69% 89.70% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 1361 1.22% 90.92% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1221 1.09% 92.02% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 537 0.48% 92.50% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 497 0.45% 92.95% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 111554 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 4006 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 48.553919 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 36.073633 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 507.732262 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 4003 99.93% 99.93% # Reads before turning the bus around for writes | 196system.physmem.bytesPerActivate::samples 112305 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 203.035662 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 132.214062 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 254.437736 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 47268 42.09% 42.09% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 43750 38.96% 81.05% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 8988 8.00% 89.05% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 1909 1.70% 90.75% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 489 0.44% 91.18% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 737 0.66% 91.84% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 726 0.65% 92.49% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 505 0.45% 92.94% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 7933 7.06% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 112305 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 48.526066 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 36.050433 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 507.549530 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes |
| 215system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes | 215system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::total 4006 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 4006 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.492761 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.471115 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.861913 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 3018 75.34% 75.34% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 3 0.07% 75.41% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 984 24.56% 99.98% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::total 4006 # Writes before turning the bus around for reads 228system.physmem.totQLat 2707676000 # Total ticks spent queuing 229system.physmem.totMemAccLat 8148907250 # Total ticks spent from burst creation until serviced by the DRAM 230system.physmem.totBusLat 1450995000 # Total ticks spent in databus transfers 231system.physmem.avgQLat 9330.41 # Average queueing delay per DRAM burst | 218system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.481417 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.460113 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.855134 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 3044 75.93% 75.93% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 965 24.07% 100.00% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads 226system.physmem.totQLat 2737356250 # Total ticks spent queuing 227system.physmem.totMemAccLat 8179187500 # Total ticks spent from burst creation until serviced by the DRAM 228system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers 229system.physmem.avgQLat 9431.65 # Average queueing delay per DRAM burst |
| 232system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 230system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 233system.physmem.avgMemAccLat 28080.41 # Average memory access latency per DRAM burst 234system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s 235system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s 236system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s 237system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s | 231system.physmem.avgMemAccLat 28181.65 # Average memory access latency per DRAM burst 232system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s 233system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s 234system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s 235system.physmem.avgWrBWSys 7.76 # Average system write bandwidth in MiByte/s |
| 238system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 239system.physmem.busUtil 0.33 # Data bus utilization in percentage 240system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads 241system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 242system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 236system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 237system.physmem.busUtil 0.33 # Data bus utilization in percentage 238system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads 239system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 240system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 243system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing 244system.physmem.readRowHits 194608 # Number of row buffer hits during reads 245system.physmem.writeRowHits 50098 # Number of row buffer hits during writes 246system.physmem.readRowHitRate 67.06 # Row buffer hit rate for reads | 241system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing 242system.physmem.readRowHits 193898 # Number of row buffer hits during reads 243system.physmem.writeRowHits 50093 # Number of row buffer hits during writes 244system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads |
| 247system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes | 245system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes |
| 248system.physmem.avgGap 1519195.16 # Average gap between requests 249system.physmem.pageHitRate 68.68 # Row buffer hit rate, read and write combined 250system.physmem_0.actEnergy 421810200 # Energy for activate commands per rank (pJ) 251system.physmem_0.preEnergy 230154375 # Energy for precharge commands per rank (pJ) 252system.physmem_0.readEnergy 1134190200 # Energy for read commands per rank (pJ) 253system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) 254system.physmem_0.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) 255system.physmem_0.actBackEnergy 106352983170 # Energy for active background per rank (pJ) 256system.physmem_0.preBackEnergy 231777774000 # Energy for precharge background per rank (pJ) 257system.physmem_0.totalEnergy 375519162345 # Total energy per rank (pJ) 258system.physmem_0.averagePower 693.117148 # Core power per rank (mW) 259system.physmem_0.memoryStateTime::IDLE 384873582500 # Time in different power states 260system.physmem_0.memoryStateTime::REF 18091320000 # Time in different power states | 246system.physmem.avgGap 1528348.80 # Average gap between requests 247system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined 248system.physmem_0.actEnergy 424002600 # Energy for activate commands per rank (pJ) 249system.physmem_0.preEnergy 231350625 # Energy for precharge commands per rank (pJ) 250system.physmem_0.readEnergy 1134369600 # Energy for read commands per rank (pJ) 251system.physmem_0.writeEnergy 215570160 # Energy for write commands per rank (pJ) 252system.physmem_0.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) 253system.physmem_0.actBackEnergy 106884947925 # Energy for active background per rank (pJ) 254system.physmem_0.preBackEnergy 233273273250 # Energy for precharge background per rank (pJ) 255system.physmem_0.totalEnergy 377763731280 # Total energy per rank (pJ) 256system.physmem_0.averagePower 693.076638 # Core power per rank (mW) 257system.physmem_0.memoryStateTime::IDLE 387358600750 # Time in different power states 258system.physmem_0.memoryStateTime::REF 18200520000 # Time in different power states |
| 261system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 259system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 262system.physmem_0.memoryStateTime::ACT 138818819500 # Time in different power states | 260system.physmem_0.memoryStateTime::ACT 139494961250 # Time in different power states |
| 263system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 261system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 264system.physmem_1.actEnergy 421477560 # Energy for activate commands per rank (pJ) 265system.physmem_1.preEnergy 229972875 # Energy for precharge commands per rank (pJ) 266system.physmem_1.readEnergy 1129034400 # Energy for read commands per rank (pJ) 267system.physmem_1.writeEnergy 212505120 # Energy for write commands per rank (pJ) 268system.physmem_1.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) 269system.physmem_1.actBackEnergy 105425199585 # Energy for active background per rank (pJ) 270system.physmem_1.preBackEnergy 232591619250 # Energy for precharge background per rank (pJ) 271system.physmem_1.totalEnergy 375396430710 # Total energy per rank (pJ) 272system.physmem_1.averagePower 692.890615 # Core power per rank (mW) 273system.physmem_1.memoryStateTime::IDLE 386233048000 # Time in different power states 274system.physmem_1.memoryStateTime::REF 18091320000 # Time in different power states | 262system.physmem_1.actEnergy 424962720 # Energy for activate commands per rank (pJ) 263system.physmem_1.preEnergy 231874500 # Energy for precharge commands per rank (pJ) 264system.physmem_1.readEnergy 1129096800 # Energy for read commands per rank (pJ) 265system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) 266system.physmem_1.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) 267system.physmem_1.actBackEnergy 105917359815 # Energy for active background per rank (pJ) 268system.physmem_1.preBackEnergy 234122034750 # Energy for precharge background per rank (pJ) 269system.physmem_1.totalEnergy 377638135065 # Total energy per rank (pJ) 270system.physmem_1.averagePower 692.846209 # Core power per rank (mW) 271system.physmem_1.memoryStateTime::IDLE 388771820250 # Time in different power states 272system.physmem_1.memoryStateTime::REF 18200520000 # Time in different power states |
| 275system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 273system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 276system.physmem_1.memoryStateTime::ACT 137458753250 # Time in different power states | 274system.physmem_1.memoryStateTime::ACT 138081006000 # Time in different power states |
| 277system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 275system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 278system.cpu.branchPred.lookups 156937341 # Number of BP lookups 279system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted 280system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect 281system.cpu.branchPred.BTBLookups 97536058 # Number of BTB lookups 282system.cpu.branchPred.BTBHits 81874318 # Number of BTB hits | 276system.cpu.branchPred.lookups 155213668 # Number of BP lookups 277system.cpu.branchPred.condPredicted 105449696 # Number of conditional branches predicted 278system.cpu.branchPred.condIncorrect 12879317 # Number of conditional branches incorrect 279system.cpu.branchPred.BTBLookups 90304208 # Number of BTB lookups 280system.cpu.branchPred.BTBHits 82854286 # Number of BTB hits |
| 283system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 281system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 284system.cpu.branchPred.BTBHitPct 83.942615 # BTB Hit Percentage 285system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. 286system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. | 282system.cpu.branchPred.BTBHitPct 91.750194 # BTB Hit Percentage 283system.cpu.branchPred.usedRAS 19341274 # Number of times the RAS was used to get a target. 284system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. |
| 287system.cpu_clk_domain.clock 500 # Clock period in ticks 288system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 397system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 398system.cpu.itb.read_accesses 0 # DTB read accesses 399system.cpu.itb.write_accesses 0 # DTB write accesses 400system.cpu.itb.inst_accesses 0 # ITB inst accesses 401system.cpu.itb.hits 0 # DTB hits 402system.cpu.itb.misses 0 # DTB misses 403system.cpu.itb.accesses 0 # DTB accesses 404system.cpu.workload.num_syscalls 673 # Number of system calls | 285system.cpu_clk_domain.clock 500 # Clock period in ticks 286system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 288system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 395system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu.itb.read_accesses 0 # DTB read accesses 397system.cpu.itb.write_accesses 0 # DTB write accesses 398system.cpu.itb.inst_accesses 0 # ITB inst accesses 399system.cpu.itb.hits 0 # DTB hits 400system.cpu.itb.misses 0 # DTB misses 401system.cpu.itb.accesses 0 # DTB accesses 402system.cpu.workload.num_syscalls 673 # Number of system calls |
| 405system.cpu.numCycles 1083572202 # number of cpu cycles simulated | 403system.cpu.numCycles 1090113311 # number of cpu cycles simulated |
| 406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 408system.cpu.committedInsts 640655084 # Number of instructions committed 409system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed | 404system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 405system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 406system.cpu.committedInsts 640655084 # Number of instructions committed 407system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed |
| 410system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit | 408system.cpu.discardedOps 22623250 # Number of ops (including micro ops) which were discarded before commit |
| 411system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 409system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 412system.cpu.cpi 1.691350 # CPI: cycles per instruction 413system.cpu.ipc 0.591244 # IPC: instructions per cycle 414system.cpu.tickCycles 1029141566 # Number of cycles that the object actually ticked 415system.cpu.idleCycles 54430636 # Total number of cycles that the object has spent stopped 416system.cpu.dcache.tags.replacements 778221 # number of replacements 417system.cpu.dcache.tags.tagsinuse 4092.645412 # Cycle average of tags in use 418system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. 419system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. 420system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. 421system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. 422system.cpu.dcache.tags.occ_blocks::cpu.data 4092.645412 # Average occupied blocks per requestor 423system.cpu.dcache.tags.occ_percent::cpu.data 0.999181 # Average percentage of cache occupancy 424system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy | 410system.cpu.cpi 1.701560 # CPI: cycles per instruction 411system.cpu.ipc 0.587696 # IPC: instructions per cycle 412system.cpu.tickCycles 1030411592 # Number of cycles that the object actually ticked 413system.cpu.idleCycles 59701719 # Total number of cycles that the object has spent stopped 414system.cpu.dcache.tags.replacements 778141 # number of replacements 415system.cpu.dcache.tags.tagsinuse 4092.460106 # Cycle average of tags in use 416system.cpu.dcache.tags.total_refs 378456482 # Total number of references to valid blocks. 417system.cpu.dcache.tags.sampled_refs 782237 # Sample count of references to valid blocks. 418system.cpu.dcache.tags.avg_refs 483.813067 # Average number of references to valid blocks. 419system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit. 420system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460106 # Average occupied blocks per requestor 421system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy 422system.cpu.dcache.tags.occ_percent::total 0.999136 # Average percentage of cache occupancy |
| 425system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 426system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id | 423system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 424system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id |
| 427system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id 428system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id 429system.cpu.dcache.tags.age_task_id_blocks_1024::3 1341 # Occupied blocks per task id 430system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id | 425system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 426system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id 427system.cpu.dcache.tags.age_task_id_blocks_1024::3 1339 # Occupied blocks per task id 428system.cpu.dcache.tags.age_task_id_blocks_1024::4 1594 # Occupied blocks per task id |
| 431system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 429system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 432system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses 433system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses 434system.cpu.dcache.ReadReq_hits::cpu.data 249632505 # number of ReadReq hits 435system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits 436system.cpu.dcache.WriteReq_hits::cpu.data 128813764 # number of WriteReq hits 437system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits | 430system.cpu.dcache.tags.tag_accesses 759397955 # Number of tag accesses 431system.cpu.dcache.tags.data_accesses 759397955 # Number of data accesses 432system.cpu.dcache.ReadReq_hits::cpu.data 249631239 # number of ReadReq hits 433system.cpu.dcache.ReadReq_hits::total 249631239 # number of ReadReq hits 434system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits 435system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits |
| 438system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 439system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 440system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 441system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits | 436system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 437system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 438system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 439system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits |
| 442system.cpu.dcache.demand_hits::cpu.data 378446269 # number of demand (read+write) hits 443system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits 444system.cpu.dcache.overall_hits::cpu.data 378446269 # number of overall hits 445system.cpu.dcache.overall_hits::total 378446269 # number of overall hits 446system.cpu.dcache.ReadReq_misses::cpu.data 713747 # number of ReadReq misses 447system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses 448system.cpu.dcache.WriteReq_misses::cpu.data 137713 # number of WriteReq misses 449system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses 450system.cpu.dcache.demand_misses::cpu.data 851460 # number of demand (read+write) misses 451system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses 452system.cpu.dcache.overall_misses::cpu.data 851460 # number of overall misses 453system.cpu.dcache.overall_misses::total 851460 # number of overall misses 454system.cpu.dcache.ReadReq_miss_latency::cpu.data 23055853217 # number of ReadReq miss cycles 455system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles 456system.cpu.dcache.WriteReq_miss_latency::cpu.data 9199211000 # number of WriteReq miss cycles 457system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles 458system.cpu.dcache.demand_miss_latency::cpu.data 32255064217 # number of demand (read+write) miss cycles 459system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles 460system.cpu.dcache.overall_miss_latency::cpu.data 32255064217 # number of overall miss cycles 461system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles 462system.cpu.dcache.ReadReq_accesses::cpu.data 250346252 # number of ReadReq accesses(hits+misses) 463system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) | 440system.cpu.dcache.demand_hits::cpu.data 378445004 # number of demand (read+write) hits 441system.cpu.dcache.demand_hits::total 378445004 # number of demand (read+write) hits 442system.cpu.dcache.overall_hits::cpu.data 378445004 # number of overall hits 443system.cpu.dcache.overall_hits::total 378445004 # number of overall hits 444system.cpu.dcache.ReadReq_misses::cpu.data 713665 # number of ReadReq misses 445system.cpu.dcache.ReadReq_misses::total 713665 # number of ReadReq misses 446system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses 447system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses 448system.cpu.dcache.demand_misses::cpu.data 851377 # number of demand (read+write) misses 449system.cpu.dcache.demand_misses::total 851377 # number of demand (read+write) misses 450system.cpu.dcache.overall_misses::cpu.data 851377 # number of overall misses 451system.cpu.dcache.overall_misses::total 851377 # number of overall misses 452system.cpu.dcache.ReadReq_miss_latency::cpu.data 24698082718 # number of ReadReq miss cycles 453system.cpu.dcache.ReadReq_miss_latency::total 24698082718 # number of ReadReq miss cycles 454system.cpu.dcache.WriteReq_miss_latency::cpu.data 10190251750 # number of WriteReq miss cycles 455system.cpu.dcache.WriteReq_miss_latency::total 10190251750 # number of WriteReq miss cycles 456system.cpu.dcache.demand_miss_latency::cpu.data 34888334468 # number of demand (read+write) miss cycles 457system.cpu.dcache.demand_miss_latency::total 34888334468 # number of demand (read+write) miss cycles 458system.cpu.dcache.overall_miss_latency::cpu.data 34888334468 # number of overall miss cycles 459system.cpu.dcache.overall_miss_latency::total 34888334468 # number of overall miss cycles 460system.cpu.dcache.ReadReq_accesses::cpu.data 250344904 # number of ReadReq accesses(hits+misses) 461system.cpu.dcache.ReadReq_accesses::total 250344904 # number of ReadReq accesses(hits+misses) |
| 464system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 465system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 466system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 467system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 468system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 469system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) | 462system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 463system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 464system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 465system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 466system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 467system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) |
| 470system.cpu.dcache.demand_accesses::cpu.data 379297729 # number of demand (read+write) accesses 471system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses 472system.cpu.dcache.overall_accesses::cpu.data 379297729 # number of overall (read+write) accesses 473system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses | 468system.cpu.dcache.demand_accesses::cpu.data 379296381 # number of demand (read+write) accesses 469system.cpu.dcache.demand_accesses::total 379296381 # number of demand (read+write) accesses 470system.cpu.dcache.overall_accesses::cpu.data 379296381 # number of overall (read+write) accesses 471system.cpu.dcache.overall_accesses::total 379296381 # number of overall (read+write) accesses |
| 474system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses 475system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses 476system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 477system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 478system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses 479system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses 480system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses 481system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses | 472system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses 473system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses 474system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 475system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 476system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses 477system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses 478system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses 479system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses |
| 482system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32302.557092 # average ReadReq miss latency 483system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency 484system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66799.873650 # average WriteReq miss latency 485system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency 486system.cpu.dcache.demand_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency 487system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency 488system.cpu.dcache.overall_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency 489system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency | 480system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.389627 # average ReadReq miss latency 481system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.389627 # average ReadReq miss latency 482system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73996.832157 # average WriteReq miss latency 483system.cpu.dcache.WriteReq_avg_miss_latency::total 73996.832157 # average WriteReq miss latency 484system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency 485system.cpu.dcache.demand_avg_miss_latency::total 40978.713858 # average overall miss latency 486system.cpu.dcache.overall_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency 487system.cpu.dcache.overall_avg_miss_latency::total 40978.713858 # average overall miss latency |
| 490system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 491system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 492system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 493system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 494system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 495system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 496system.cpu.dcache.fast_writes 0 # number of fast writes performed 497system.cpu.dcache.cache_copies 0 # number of cache copies performed 498system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks 499system.cpu.dcache.writebacks::total 91420 # number of writebacks | 488system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 489system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 490system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 491system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 492system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 493system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 494system.cpu.dcache.fast_writes 0 # number of fast writes performed 495system.cpu.dcache.cache_copies 0 # number of cache copies performed 496system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks 497system.cpu.dcache.writebacks::total 91420 # number of writebacks |
| 500system.cpu.dcache.ReadReq_mshr_hits::cpu.data 752 # number of ReadReq MSHR hits 501system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits 502system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68391 # number of WriteReq MSHR hits 503system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits 504system.cpu.dcache.demand_mshr_hits::cpu.data 69143 # number of demand (read+write) MSHR hits 505system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits 506system.cpu.dcache.overall_mshr_hits::cpu.data 69143 # number of overall MSHR hits 507system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits 508system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712995 # number of ReadReq MSHR misses 509system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses | 498system.cpu.dcache.ReadReq_mshr_hits::cpu.data 750 # number of ReadReq MSHR hits 499system.cpu.dcache.ReadReq_mshr_hits::total 750 # number of ReadReq MSHR hits 500system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits 501system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits 502system.cpu.dcache.demand_mshr_hits::cpu.data 69140 # number of demand (read+write) MSHR hits 503system.cpu.dcache.demand_mshr_hits::total 69140 # number of demand (read+write) MSHR hits 504system.cpu.dcache.overall_mshr_hits::cpu.data 69140 # number of overall MSHR hits 505system.cpu.dcache.overall_mshr_hits::total 69140 # number of overall MSHR hits 506system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712915 # number of ReadReq MSHR misses 507system.cpu.dcache.ReadReq_mshr_misses::total 712915 # number of ReadReq MSHR misses |
| 510system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 511system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses | 508system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 509system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses |
| 512system.cpu.dcache.demand_mshr_misses::cpu.data 782317 # number of demand (read+write) MSHR misses 513system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses 514system.cpu.dcache.overall_mshr_misses::cpu.data 782317 # number of overall MSHR misses 515system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses 516system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21545578028 # number of ReadReq MSHR miss cycles 517system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles 518system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4531082000 # number of WriteReq MSHR miss cycles 519system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles 520system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26076660028 # number of demand (read+write) MSHR miss cycles 521system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles 522system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26076660028 # number of overall MSHR miss cycles 523system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles | 510system.cpu.dcache.demand_mshr_misses::cpu.data 782237 # number of demand (read+write) MSHR misses 511system.cpu.dcache.demand_mshr_misses::total 782237 # number of demand (read+write) MSHR misses 512system.cpu.dcache.overall_mshr_misses::cpu.data 782237 # number of overall MSHR misses 513system.cpu.dcache.overall_mshr_misses::total 782237 # number of overall MSHR misses 514system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23543649027 # number of ReadReq MSHR miss cycles 515system.cpu.dcache.ReadReq_mshr_miss_latency::total 23543649027 # number of ReadReq MSHR miss cycles 516system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5045531250 # number of WriteReq MSHR miss cycles 517system.cpu.dcache.WriteReq_mshr_miss_latency::total 5045531250 # number of WriteReq MSHR miss cycles 518system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28589180277 # number of demand (read+write) MSHR miss cycles 519system.cpu.dcache.demand_mshr_miss_latency::total 28589180277 # number of demand (read+write) MSHR miss cycles 520system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589180277 # number of overall MSHR miss cycles 521system.cpu.dcache.overall_mshr_miss_latency::total 28589180277 # number of overall MSHR miss cycles |
| 524system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses 525system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses 526system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 527system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses | 522system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses 523system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses 524system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 525system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses |
| 528system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses 529system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses 530system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses 531system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses 532system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30218.413913 # average ReadReq mshr miss latency 533system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency 534system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65362.828539 # average WriteReq mshr miss latency 535system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency 536system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency 537system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency 538system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency 539system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency | 526system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 527system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 528system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 529system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 530system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33024.482620 # average ReadReq mshr miss latency 531system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33024.482620 # average ReadReq mshr miss latency 532system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72783.982718 # average WriteReq mshr miss latency 533system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72783.982718 # average WriteReq mshr miss latency 534system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency 535system.cpu.dcache.demand_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency 536system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency 537system.cpu.dcache.overall_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency |
| 540system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 538system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 541system.cpu.icache.tags.replacements 23590 # number of replacements 542system.cpu.icache.tags.tagsinuse 1712.180561 # Cycle average of tags in use 543system.cpu.icache.tags.total_refs 289921723 # Total number of references to valid blocks. 544system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. 545system.cpu.icache.tags.avg_refs 11440.816187 # Average number of references to valid blocks. | 539system.cpu.icache.tags.replacements 23596 # number of replacements 540system.cpu.icache.tags.tagsinuse 1712.064969 # Cycle average of tags in use 541system.cpu.icache.tags.total_refs 291953853 # Total number of references to valid blocks. 542system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. 543system.cpu.icache.tags.avg_refs 11518.280388 # Average number of references to valid blocks. |
| 546system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 544system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 547system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180561 # Average occupied blocks per requestor 548system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy 549system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy | 545system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064969 # Average occupied blocks per requestor 546system.cpu.icache.tags.occ_percent::cpu.inst 0.835969 # Average percentage of cache occupancy 547system.cpu.icache.tags.occ_percent::total 0.835969 # Average percentage of cache occupancy |
| 550system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id | 548system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id |
| 551system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id | 549system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id |
| 552system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id | 550system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id |
| 553system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id | 551system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id |
| 554system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id | 552system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id |
| 555system.cpu.icache.tags.tag_accesses 579919471 # Number of tag accesses 556system.cpu.icache.tags.data_accesses 579919471 # Number of data accesses 557system.cpu.icache.ReadReq_hits::cpu.inst 289921723 # number of ReadReq hits 558system.cpu.icache.ReadReq_hits::total 289921723 # number of ReadReq hits 559system.cpu.icache.demand_hits::cpu.inst 289921723 # number of demand (read+write) hits 560system.cpu.icache.demand_hits::total 289921723 # number of demand (read+write) hits 561system.cpu.icache.overall_hits::cpu.inst 289921723 # number of overall hits 562system.cpu.icache.overall_hits::total 289921723 # number of overall hits 563system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses 564system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses 565system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses 566system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses 567system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses 568system.cpu.icache.overall_misses::total 25342 # number of overall misses 569system.cpu.icache.ReadReq_miss_latency::cpu.inst 480693746 # number of ReadReq miss cycles 570system.cpu.icache.ReadReq_miss_latency::total 480693746 # number of ReadReq miss cycles 571system.cpu.icache.demand_miss_latency::cpu.inst 480693746 # number of demand (read+write) miss cycles 572system.cpu.icache.demand_miss_latency::total 480693746 # number of demand (read+write) miss cycles 573system.cpu.icache.overall_miss_latency::cpu.inst 480693746 # number of overall miss cycles 574system.cpu.icache.overall_miss_latency::total 480693746 # number of overall miss cycles 575system.cpu.icache.ReadReq_accesses::cpu.inst 289947065 # number of ReadReq accesses(hits+misses) 576system.cpu.icache.ReadReq_accesses::total 289947065 # number of ReadReq accesses(hits+misses) 577system.cpu.icache.demand_accesses::cpu.inst 289947065 # number of demand (read+write) accesses 578system.cpu.icache.demand_accesses::total 289947065 # number of demand (read+write) accesses 579system.cpu.icache.overall_accesses::cpu.inst 289947065 # number of overall (read+write) accesses 580system.cpu.icache.overall_accesses::total 289947065 # number of overall (read+write) accesses | 553system.cpu.icache.tags.tag_accesses 583983749 # Number of tag accesses 554system.cpu.icache.tags.data_accesses 583983749 # Number of data accesses 555system.cpu.icache.ReadReq_hits::cpu.inst 291953853 # number of ReadReq hits 556system.cpu.icache.ReadReq_hits::total 291953853 # number of ReadReq hits 557system.cpu.icache.demand_hits::cpu.inst 291953853 # number of demand (read+write) hits 558system.cpu.icache.demand_hits::total 291953853 # number of demand (read+write) hits 559system.cpu.icache.overall_hits::cpu.inst 291953853 # number of overall hits 560system.cpu.icache.overall_hits::total 291953853 # number of overall hits 561system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses 562system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses 563system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses 564system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses 565system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses 566system.cpu.icache.overall_misses::total 25348 # number of overall misses 567system.cpu.icache.ReadReq_miss_latency::cpu.inst 499968245 # number of ReadReq miss cycles 568system.cpu.icache.ReadReq_miss_latency::total 499968245 # number of ReadReq miss cycles 569system.cpu.icache.demand_miss_latency::cpu.inst 499968245 # number of demand (read+write) miss cycles 570system.cpu.icache.demand_miss_latency::total 499968245 # number of demand (read+write) miss cycles 571system.cpu.icache.overall_miss_latency::cpu.inst 499968245 # number of overall miss cycles 572system.cpu.icache.overall_miss_latency::total 499968245 # number of overall miss cycles 573system.cpu.icache.ReadReq_accesses::cpu.inst 291979201 # number of ReadReq accesses(hits+misses) 574system.cpu.icache.ReadReq_accesses::total 291979201 # number of ReadReq accesses(hits+misses) 575system.cpu.icache.demand_accesses::cpu.inst 291979201 # number of demand (read+write) accesses 576system.cpu.icache.demand_accesses::total 291979201 # number of demand (read+write) accesses 577system.cpu.icache.overall_accesses::cpu.inst 291979201 # number of overall (read+write) accesses 578system.cpu.icache.overall_accesses::total 291979201 # number of overall (read+write) accesses |
| 581system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses 582system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses 583system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses 584system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses 585system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses 586system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses | 579system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses 580system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses 581system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses 582system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses 583system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses 584system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses |
| 587system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.263989 # average ReadReq miss latency 588system.cpu.icache.ReadReq_avg_miss_latency::total 18968.263989 # average ReadReq miss latency 589system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency 590system.cpu.icache.demand_avg_miss_latency::total 18968.263989 # average overall miss latency 591system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency 592system.cpu.icache.overall_avg_miss_latency::total 18968.263989 # average overall miss latency | 585system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19724.169362 # average ReadReq miss latency 586system.cpu.icache.ReadReq_avg_miss_latency::total 19724.169362 # average ReadReq miss latency 587system.cpu.icache.demand_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency 588system.cpu.icache.demand_avg_miss_latency::total 19724.169362 # average overall miss latency 589system.cpu.icache.overall_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency 590system.cpu.icache.overall_avg_miss_latency::total 19724.169362 # average overall miss latency |
| 593system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 594system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 595system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 596system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 597system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 598system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 599system.cpu.icache.fast_writes 0 # number of fast writes performed 600system.cpu.icache.cache_copies 0 # number of cache copies performed | 591system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 592system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 593system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 594system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 595system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 596system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 597system.cpu.icache.fast_writes 0 # number of fast writes performed 598system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 601system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25342 # number of ReadReq MSHR misses 602system.cpu.icache.ReadReq_mshr_misses::total 25342 # number of ReadReq MSHR misses 603system.cpu.icache.demand_mshr_misses::cpu.inst 25342 # number of demand (read+write) MSHR misses 604system.cpu.icache.demand_mshr_misses::total 25342 # number of demand (read+write) MSHR misses 605system.cpu.icache.overall_mshr_misses::cpu.inst 25342 # number of overall MSHR misses 606system.cpu.icache.overall_mshr_misses::total 25342 # number of overall MSHR misses 607system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428909254 # number of ReadReq MSHR miss cycles 608system.cpu.icache.ReadReq_mshr_miss_latency::total 428909254 # number of ReadReq MSHR miss cycles 609system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428909254 # number of demand (read+write) MSHR miss cycles 610system.cpu.icache.demand_mshr_miss_latency::total 428909254 # number of demand (read+write) MSHR miss cycles 611system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428909254 # number of overall MSHR miss cycles 612system.cpu.icache.overall_mshr_miss_latency::total 428909254 # number of overall MSHR miss cycles | 599system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses 600system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses 601system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses 602system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses 603system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses 604system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses 605system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460840255 # number of ReadReq MSHR miss cycles 606system.cpu.icache.ReadReq_mshr_miss_latency::total 460840255 # number of ReadReq MSHR miss cycles 607system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460840255 # number of demand (read+write) MSHR miss cycles 608system.cpu.icache.demand_mshr_miss_latency::total 460840255 # number of demand (read+write) MSHR miss cycles 609system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460840255 # number of overall MSHR miss cycles 610system.cpu.icache.overall_mshr_miss_latency::total 460840255 # number of overall MSHR miss cycles |
| 613system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses 614system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses 615system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses 616system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses 617system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses 618system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses | 611system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses 612system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses 613system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses 614system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses 615system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses 616system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses |
| 619system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.838371 # average ReadReq mshr miss latency 620system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.838371 # average ReadReq mshr miss latency 621system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency 622system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency 623system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency 624system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency | 617system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18180.537123 # average ReadReq mshr miss latency 618system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18180.537123 # average ReadReq mshr miss latency 619system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency 620system.cpu.icache.demand_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency 621system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency 622system.cpu.icache.overall_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency |
| 625system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 623system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 626system.cpu.l2cache.tags.replacements 257749 # number of replacements 627system.cpu.l2cache.tags.tagsinuse 32583.111771 # Cycle average of tags in use 628system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks. 629system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. 630system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. | 624system.cpu.l2cache.tags.replacements 257753 # number of replacements 625system.cpu.l2cache.tags.tagsinuse 32573.758002 # Cycle average of tags in use 626system.cpu.l2cache.tags.total_refs 538992 # Total number of references to valid blocks. 627system.cpu.l2cache.tags.sampled_refs 290497 # Sample count of references to valid blocks. 628system.cpu.l2cache.tags.avg_refs 1.855413 # Average number of references to valid blocks. |
| 631system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 629system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 632system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor 633system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.519731 # Average occupied blocks per requestor 634system.cpu.l2cache.tags.occ_blocks::cpu.data 29632.926805 # Average occupied blocks per requestor 635system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy 636system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002732 # Average percentage of cache occupancy 637system.cpu.l2cache.tags.occ_percent::cpu.data 0.904325 # Average percentage of cache occupancy 638system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy | 630system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231587 # Average occupied blocks per requestor 631system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601373 # Average occupied blocks per requestor 632system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925042 # Average occupied blocks per requestor 633system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy 634system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002734 # Average percentage of cache occupancy 635system.cpu.l2cache.tags.occ_percent::cpu.data 0.903379 # Average percentage of cache occupancy 636system.cpu.l2cache.tags.occ_percent::total 0.994072 # Average percentage of cache occupancy |
| 639system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id | 637system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id |
| 640system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 641system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 642system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 643system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2800 # Occupied blocks per task id 644system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 # Occupied blocks per task id | 638system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 639system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id 640system.cpu.l2cache.tags.age_task_id_blocks_1024::2 287 # Occupied blocks per task id 641system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2793 # Occupied blocks per task id 642system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29433 # Occupied blocks per task id |
| 645system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id | 643system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id |
| 646system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses 647system.cpu.l2cache.tags.data_accesses 7552447 # Number of data accesses 648system.cpu.l2cache.ReadReq_hits::cpu.inst 22764 # number of ReadReq hits 649system.cpu.l2cache.ReadReq_hits::cpu.data 491102 # number of ReadReq hits 650system.cpu.l2cache.ReadReq_hits::total 513866 # number of ReadReq hits | 644system.cpu.l2cache.tags.tag_accesses 7551859 # Number of tag accesses 645system.cpu.l2cache.tags.data_accesses 7551859 # Number of data accesses 646system.cpu.l2cache.ReadReq_hits::cpu.inst 22766 # number of ReadReq hits 647system.cpu.l2cache.ReadReq_hits::cpu.data 491022 # number of ReadReq hits 648system.cpu.l2cache.ReadReq_hits::total 513788 # number of ReadReq hits |
| 651system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits 652system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits 653system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 654system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits | 649system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits 650system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits 651system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 652system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits |
| 655system.cpu.l2cache.demand_hits::cpu.inst 22764 # number of demand (read+write) hits 656system.cpu.l2cache.demand_hits::cpu.data 494333 # number of demand (read+write) hits 657system.cpu.l2cache.demand_hits::total 517097 # number of demand (read+write) hits 658system.cpu.l2cache.overall_hits::cpu.inst 22764 # number of overall hits 659system.cpu.l2cache.overall_hits::cpu.data 494333 # number of overall hits 660system.cpu.l2cache.overall_hits::total 517097 # number of overall hits 661system.cpu.l2cache.ReadReq_misses::cpu.inst 2578 # number of ReadReq misses | 653system.cpu.l2cache.demand_hits::cpu.inst 22766 # number of demand (read+write) hits 654system.cpu.l2cache.demand_hits::cpu.data 494253 # number of demand (read+write) hits 655system.cpu.l2cache.demand_hits::total 517019 # number of demand (read+write) hits 656system.cpu.l2cache.overall_hits::cpu.inst 22766 # number of overall hits 657system.cpu.l2cache.overall_hits::cpu.data 494253 # number of overall hits 658system.cpu.l2cache.overall_hits::total 517019 # number of overall hits 659system.cpu.l2cache.ReadReq_misses::cpu.inst 2582 # number of ReadReq misses |
| 662system.cpu.l2cache.ReadReq_misses::cpu.data 221893 # number of ReadReq misses | 660system.cpu.l2cache.ReadReq_misses::cpu.data 221893 # number of ReadReq misses |
| 663system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses | 661system.cpu.l2cache.ReadReq_misses::total 224475 # number of ReadReq misses |
| 664system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses 665system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses | 662system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses 663system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses |
| 666system.cpu.l2cache.demand_misses::cpu.inst 2578 # number of demand (read+write) misses | 664system.cpu.l2cache.demand_misses::cpu.inst 2582 # number of demand (read+write) misses |
| 667system.cpu.l2cache.demand_misses::cpu.data 287984 # number of demand (read+write) misses | 665system.cpu.l2cache.demand_misses::cpu.data 287984 # number of demand (read+write) misses |
| 668system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses 669system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses | 666system.cpu.l2cache.demand_misses::total 290566 # number of demand (read+write) misses 667system.cpu.l2cache.overall_misses::cpu.inst 2582 # number of overall misses |
| 670system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses | 668system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses |
| 671system.cpu.l2cache.overall_misses::total 290562 # number of overall misses 672system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175909750 # number of ReadReq miss cycles 673system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15921496500 # number of ReadReq miss cycles 674system.cpu.l2cache.ReadReq_miss_latency::total 16097406250 # number of ReadReq miss cycles 675system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4429448000 # number of ReadExReq miss cycles 676system.cpu.l2cache.ReadExReq_miss_latency::total 4429448000 # number of ReadExReq miss cycles 677system.cpu.l2cache.demand_miss_latency::cpu.inst 175909750 # number of demand (read+write) miss cycles 678system.cpu.l2cache.demand_miss_latency::cpu.data 20350944500 # number of demand (read+write) miss cycles 679system.cpu.l2cache.demand_miss_latency::total 20526854250 # number of demand (read+write) miss cycles 680system.cpu.l2cache.overall_miss_latency::cpu.inst 175909750 # number of overall miss cycles 681system.cpu.l2cache.overall_miss_latency::cpu.data 20350944500 # number of overall miss cycles 682system.cpu.l2cache.overall_miss_latency::total 20526854250 # number of overall miss cycles 683system.cpu.l2cache.ReadReq_accesses::cpu.inst 25342 # number of ReadReq accesses(hits+misses) 684system.cpu.l2cache.ReadReq_accesses::cpu.data 712995 # number of ReadReq accesses(hits+misses) 685system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) | 669system.cpu.l2cache.overall_misses::total 290566 # number of overall misses 670system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196449750 # number of ReadReq miss cycles 671system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17674937000 # number of ReadReq miss cycles 672system.cpu.l2cache.ReadReq_miss_latency::total 17871386750 # number of ReadReq miss cycles 673system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942281750 # number of ReadExReq miss cycles 674system.cpu.l2cache.ReadExReq_miss_latency::total 4942281750 # number of ReadExReq miss cycles 675system.cpu.l2cache.demand_miss_latency::cpu.inst 196449750 # number of demand (read+write) miss cycles 676system.cpu.l2cache.demand_miss_latency::cpu.data 22617218750 # number of demand (read+write) miss cycles 677system.cpu.l2cache.demand_miss_latency::total 22813668500 # number of demand (read+write) miss cycles 678system.cpu.l2cache.overall_miss_latency::cpu.inst 196449750 # number of overall miss cycles 679system.cpu.l2cache.overall_miss_latency::cpu.data 22617218750 # number of overall miss cycles 680system.cpu.l2cache.overall_miss_latency::total 22813668500 # number of overall miss cycles 681system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses) 682system.cpu.l2cache.ReadReq_accesses::cpu.data 712915 # number of ReadReq accesses(hits+misses) 683system.cpu.l2cache.ReadReq_accesses::total 738263 # number of ReadReq accesses(hits+misses) |
| 686system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) 687system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) 688system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 689system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) | 684system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) 685system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) 686system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 687system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) |
| 690system.cpu.l2cache.demand_accesses::cpu.inst 25342 # number of demand (read+write) accesses 691system.cpu.l2cache.demand_accesses::cpu.data 782317 # number of demand (read+write) accesses 692system.cpu.l2cache.demand_accesses::total 807659 # number of demand (read+write) accesses 693system.cpu.l2cache.overall_accesses::cpu.inst 25342 # number of overall (read+write) accesses 694system.cpu.l2cache.overall_accesses::cpu.data 782317 # number of overall (read+write) accesses 695system.cpu.l2cache.overall_accesses::total 807659 # number of overall (read+write) accesses 696system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101728 # miss rate for ReadReq accesses 697system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311213 # miss rate for ReadReq accesses 698system.cpu.l2cache.ReadReq_miss_rate::total 0.304022 # miss rate for ReadReq accesses | 688system.cpu.l2cache.demand_accesses::cpu.inst 25348 # number of demand (read+write) accesses 689system.cpu.l2cache.demand_accesses::cpu.data 782237 # number of demand (read+write) accesses 690system.cpu.l2cache.demand_accesses::total 807585 # number of demand (read+write) accesses 691system.cpu.l2cache.overall_accesses::cpu.inst 25348 # number of overall (read+write) accesses 692system.cpu.l2cache.overall_accesses::cpu.data 782237 # number of overall (read+write) accesses 693system.cpu.l2cache.overall_accesses::total 807585 # number of overall (read+write) accesses 694system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101862 # miss rate for ReadReq accesses 695system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311247 # miss rate for ReadReq accesses 696system.cpu.l2cache.ReadReq_miss_rate::total 0.304058 # miss rate for ReadReq accesses |
| 699system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses 700system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses | 697system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses 698system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses |
| 701system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101728 # miss rate for demand accesses 702system.cpu.l2cache.demand_miss_rate::cpu.data 0.368117 # miss rate for demand accesses 703system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses 704system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101728 # miss rate for overall accesses 705system.cpu.l2cache.overall_miss_rate::cpu.data 0.368117 # miss rate for overall accesses 706system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses 707system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68234.968968 # average ReadReq miss latency 708system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71753.036373 # average ReadReq miss latency 709system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144 # average ReadReq miss latency 710system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67020.441512 # average ReadExReq miss latency 711system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512 # average ReadExReq miss latency 712system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency 713system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency 714system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218 # average overall miss latency 715system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency 716system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency 717system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency | 699system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101862 # miss rate for demand accesses 700system.cpu.l2cache.demand_miss_rate::cpu.data 0.368154 # miss rate for demand accesses 701system.cpu.l2cache.demand_miss_rate::total 0.359796 # miss rate for demand accesses 702system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101862 # miss rate for overall accesses 703system.cpu.l2cache.overall_miss_rate::cpu.data 0.368154 # miss rate for overall accesses 704system.cpu.l2cache.overall_miss_rate::total 0.359796 # miss rate for overall accesses 705system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76084.333850 # average ReadReq miss latency 706system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79655.225717 # average ReadReq miss latency 707system.cpu.l2cache.ReadReq_avg_miss_latency::total 79614.151910 # average ReadReq miss latency 708system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74779.951128 # average ReadExReq miss latency 709system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74779.951128 # average ReadExReq miss latency 710system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency 711system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency 712system.cpu.l2cache.demand_avg_miss_latency::total 78514.583606 # average overall miss latency 713system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency 714system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency 715system.cpu.l2cache.overall_avg_miss_latency::total 78514.583606 # average overall miss latency |
| 718system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 719system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 721system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 723system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu.l2cache.fast_writes 0 # number of fast writes performed 725system.cpu.l2cache.cache_copies 0 # number of cache copies performed 726system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 727system.cpu.l2cache.writebacks::total 66098 # number of writebacks | 716system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 717system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 718system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 719system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 720system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 721system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 722system.cpu.l2cache.fast_writes 0 # number of fast writes performed 723system.cpu.l2cache.cache_copies 0 # number of cache copies performed 724system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 725system.cpu.l2cache.writebacks::total 66098 # number of writebacks |
| 728system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 729system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 28 # number of ReadReq MSHR hits | 726system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 727system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits |
| 730system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits | 728system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits |
| 731system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 732system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits | 729system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 730system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits |
| 733system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits | 731system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits |
| 734system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 735system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits | 732system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 733system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits |
| 736system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits | 734system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits |
| 737system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2574 # number of ReadReq MSHR misses 738system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221865 # number of ReadReq MSHR misses 739system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses | 735system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2577 # number of ReadReq MSHR misses 736system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221866 # number of ReadReq MSHR misses 737system.cpu.l2cache.ReadReq_mshr_misses::total 224443 # number of ReadReq MSHR misses |
| 740system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses 741system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses | 738system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses 739system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses |
| 742system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses 743system.cpu.l2cache.demand_mshr_misses::cpu.data 287956 # number of demand (read+write) MSHR misses 744system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses 745system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses 746system.cpu.l2cache.overall_mshr_misses::cpu.data 287956 # number of overall MSHR misses 747system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses 748system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143321250 # number of ReadReq MSHR miss cycles 749system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13141995500 # number of ReadReq MSHR miss cycles 750system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles 751system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577310000 # number of ReadExReq MSHR miss cycles 752system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles 753system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143321250 # number of demand (read+write) MSHR miss cycles 754system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16719305500 # number of demand (read+write) MSHR miss cycles 755system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles 756system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143321250 # number of overall MSHR miss cycles 757system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16719305500 # number of overall MSHR miss cycles 758system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles 759system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for ReadReq accesses 760system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311173 # mshr miss rate for ReadReq accesses 761system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses | 740system.cpu.l2cache.demand_mshr_misses::cpu.inst 2577 # number of demand (read+write) MSHR misses 741system.cpu.l2cache.demand_mshr_misses::cpu.data 287957 # number of demand (read+write) MSHR misses 742system.cpu.l2cache.demand_mshr_misses::total 290534 # number of demand (read+write) MSHR misses 743system.cpu.l2cache.overall_mshr_misses::cpu.inst 2577 # number of overall MSHR misses 744system.cpu.l2cache.overall_mshr_misses::cpu.data 287957 # number of overall MSHR misses 745system.cpu.l2cache.overall_mshr_misses::total 290534 # number of overall MSHR misses 746system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163845000 # number of ReadReq MSHR miss cycles 747system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14897681250 # number of ReadReq MSHR miss cycles 748system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15061526250 # number of ReadReq MSHR miss cycles 749system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113937750 # number of ReadExReq MSHR miss cycles 750system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113937750 # number of ReadExReq MSHR miss cycles 751system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163845000 # number of demand (read+write) MSHR miss cycles 752system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19011619000 # number of demand (read+write) MSHR miss cycles 753system.cpu.l2cache.demand_mshr_miss_latency::total 19175464000 # number of demand (read+write) MSHR miss cycles 754system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163845000 # number of overall MSHR miss cycles 755system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19011619000 # number of overall MSHR miss cycles 756system.cpu.l2cache.overall_mshr_miss_latency::total 19175464000 # number of overall MSHR miss cycles 757system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for ReadReq accesses 758system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311210 # mshr miss rate for ReadReq accesses 759system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304015 # mshr miss rate for ReadReq accesses |
| 762system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 763system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses | 760system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 761system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses |
| 764system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for demand accesses 765system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for demand accesses 766system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses 767system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for overall accesses 768system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for overall accesses 769system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses 770system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55680.361305 # average ReadReq mshr miss latency 771system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59234.198724 # average ReadReq mshr miss latency 772system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency 773system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54127.036964 # average ReadExReq mshr miss latency 774system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency 775system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency 776system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency 778system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency 779system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency | 762system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for demand accesses 763system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for demand accesses 764system.cpu.l2cache.demand_mshr_miss_rate::total 0.359757 # mshr miss rate for demand accesses 765system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for overall accesses 766system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for overall accesses 767system.cpu.l2cache.overall_mshr_miss_rate::total 0.359757 # mshr miss rate for overall accesses 768system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63579.743888 # average ReadReq mshr miss latency 769system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67147.202591 # average ReadReq mshr miss latency 770system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67106.241897 # average ReadReq mshr miss latency 771system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62246.565342 # average ReadExReq mshr miss latency 772system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62246.565342 # average ReadExReq mshr miss latency 773system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency 774system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency 775system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency 776system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency 777system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency 778system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency |
| 781system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 779system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 782system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution 783system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution | 780system.cpu.toL2Bus.trans_dist::ReadReq 738263 # Transaction distribution 781system.cpu.toL2Bus.trans_dist::ReadResp 738262 # Transaction distribution |
| 784system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution 785system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 786system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution | 782system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution 783system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 784system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution |
| 787system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683 # Packet count per connected master and slave (bytes) 788system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656054 # Packet count per connected master and slave (bytes) 789system.cpu.toL2Bus.pkt_count::total 1706737 # Packet count per connected master and slave (bytes) 790system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621824 # Cumulative packet size per connected master and slave (bytes) 791system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55919168 # Cumulative packet size per connected master and slave (bytes) 792system.cpu.toL2Bus.pkt_size::total 57540992 # Cumulative packet size per connected master and slave (bytes) | 785system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) 786system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655894 # Packet count per connected master and slave (bytes) 787system.cpu.toL2Bus.pkt_count::total 1706589 # Packet count per connected master and slave (bytes) 788system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) 789system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55914048 # Cumulative packet size per connected master and slave (bytes) 790system.cpu.toL2Bus.pkt_size::total 57536256 # Cumulative packet size per connected master and slave (bytes) |
| 793system.cpu.toL2Bus.snoops 0 # Total snoops (count) | 791system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| 794system.cpu.toL2Bus.snoop_fanout::samples 899079 # Request fanout histogram 795system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram | 792system.cpu.toL2Bus.snoop_fanout::samples 899005 # Request fanout histogram 793system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram |
| 796system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 797system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 798system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 799system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 800system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 794system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 795system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 796system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 797system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 798system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 801system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 802system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 803system.cpu.toL2Bus.snoop_fanout::5 899079 100.00% 100.00% # Request fanout histogram 804system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram | 799system.cpu.toL2Bus.snoop_fanout::3 899005 100.00% 100.00% # Request fanout histogram 800system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram |
| 805system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 801system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 806system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 807system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 808system.cpu.toL2Bus.snoop_fanout::total 899079 # Request fanout histogram 809system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # Layer occupancy (ticks) | 802system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 803system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 804system.cpu.toL2Bus.snoop_fanout::total 899005 # Request fanout histogram 805system.cpu.toL2Bus.reqLayer0.occupancy 540922500 # Layer occupancy (ticks) |
| 810system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 806system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 811system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) | 807system.cpu.toL2Bus.respLayer0.occupancy 38574245 # Layer occupancy (ticks) |
| 812system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 808system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 813system.cpu.toL2Bus.respLayer1.occupancy 1224351972 # Layer occupancy (ticks) | 809system.cpu.toL2Bus.respLayer1.occupancy 1224003723 # Layer occupancy (ticks) |
| 814system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) | 810system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 815system.membus.trans_dist::ReadReq 224438 # Transaction distribution 816system.membus.trans_dist::ReadResp 224438 # Transaction distribution | 811system.membus.trans_dist::ReadReq 224442 # Transaction distribution 812system.membus.trans_dist::ReadResp 224442 # Transaction distribution |
| 817system.membus.trans_dist::Writeback 66098 # Transaction distribution 818system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 819system.membus.trans_dist::ReadExResp 66091 # Transaction distribution | 813system.membus.trans_dist::Writeback 66098 # Transaction distribution 814system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 815system.membus.trans_dist::ReadExResp 66091 # Transaction distribution |
| 820system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) 821system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) 822system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes) 823system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes) | 816system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647164 # Packet count per connected master and slave (bytes) 817system.membus.pkt_count::total 647164 # Packet count per connected master and slave (bytes) 818system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824384 # Cumulative packet size per connected master and slave (bytes) 819system.membus.pkt_size::total 22824384 # Cumulative packet size per connected master and slave (bytes) |
| 824system.membus.snoops 0 # Total snoops (count) | 820system.membus.snoops 0 # Total snoops (count) |
| 825system.membus.snoop_fanout::samples 356627 # Request fanout histogram | 821system.membus.snoop_fanout::samples 356631 # Request fanout histogram |
| 826system.membus.snoop_fanout::mean 0 # Request fanout histogram 827system.membus.snoop_fanout::stdev 0 # Request fanout histogram 828system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 822system.membus.snoop_fanout::mean 0 # Request fanout histogram 823system.membus.snoop_fanout::stdev 0 # Request fanout histogram 824system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 829system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram | 825system.membus.snoop_fanout::0 356631 100.00% 100.00% # Request fanout histogram |
| 830system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 831system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 832system.membus.snoop_fanout::min_value 0 # Request fanout histogram 833system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 826system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 827system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 828system.membus.snoop_fanout::min_value 0 # Request fanout histogram 829system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 834system.membus.snoop_fanout::total 356627 # Request fanout histogram 835system.membus.reqLayer0.occupancy 983550500 # Layer occupancy (ticks) 836system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 837system.membus.respLayer1.occupancy 2739032750 # Layer occupancy (ticks) 838system.membus.respLayer1.utilization 0.5 # Layer utilization (%) | 830system.membus.snoop_fanout::total 356631 # Request fanout histogram 831system.membus.reqLayer0.occupancy 731515500 # Layer occupancy (ticks) 832system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 833system.membus.respLayer1.occupancy 1551221000 # Layer occupancy (ticks) 834system.membus.respLayer1.utilization 0.3 # Layer utilization (%) |
| 839 840---------- End Simulation Statistics ---------- | 835 836---------- End Simulation Statistics ---------- |