| stats.txt (10585:1c9d5d9417b3) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.541781 # Number of seconds simulated 4sim_ticks 541781076000 # Number of ticks simulated 5final_tick 541781076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.541786 # Number of seconds simulated 4sim_ticks 541786101000 # Number of ticks simulated 5final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 140173 # Simulator instruction rate (inst/s) 8host_op_rate 172571 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 118539448 # Simulator tick rate (ticks/s) 10host_mem_usage 261676 # Number of bytes of host memory used 11host_seconds 4570.47 # Real time elapsed on the host | 7host_inst_rate 183531 # Simulator instruction rate (inst/s) 8host_op_rate 225950 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 155207340 # Simulator tick rate (ticks/s) 10host_mem_usage 320704 # Number of bytes of host memory used 11host_seconds 3490.72 # Real time elapsed on the host |
| 12sim_insts 640655084 # Number of instructions simulated 13sim_ops 788730743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18593856 # Number of bytes read from this memory 17system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 21system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 290529 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory | 12sim_insts 640655084 # Number of instructions simulated 13sim_ops 788730743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18593856 # Number of bytes read from this memory 17system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 21system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 290529 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory |
| 26system.physmem.bw_read::cpu.inst 34319870 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 34319870 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 303946 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 303946 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 7808084 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 7808084 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 7808084 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 34319870 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 42127954 # Total bandwidth to/from this memory (bytes/s) | 26system.physmem.bw_read::cpu.inst 34319552 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 34319552 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) |
| 35system.physmem.readReqs 290529 # Number of read requests accepted 36system.physmem.writeReqs 66098 # Number of write requests accepted 37system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.readReqs 290529 # Number of read requests accepted 36system.physmem.writeReqs 66098 # Number of write requests accepted 37system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue |
| 39system.physmem.bytesReadDRAM 18573248 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue | 39system.physmem.bytesReadDRAM 18572736 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue |
| 41system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side | 41system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side |
| 44system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue | 44system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue |
| 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 47system.physmem.perBankRdBursts::0 18288 # Per bank write bursts 48system.physmem.perBankRdBursts::1 18139 # Per bank write bursts 49system.physmem.perBankRdBursts::2 18224 # Per bank write bursts 50system.physmem.perBankRdBursts::3 18182 # Per bank write bursts 51system.physmem.perBankRdBursts::4 18264 # Per bank write bursts 52system.physmem.perBankRdBursts::5 18315 # Per bank write bursts 53system.physmem.perBankRdBursts::6 18098 # Per bank write bursts | 47system.physmem.perBankRdBursts::0 18289 # Per bank write bursts 48system.physmem.perBankRdBursts::1 18137 # Per bank write bursts 49system.physmem.perBankRdBursts::2 18222 # Per bank write bursts 50system.physmem.perBankRdBursts::3 18184 # Per bank write bursts 51system.physmem.perBankRdBursts::4 18266 # Per bank write bursts 52system.physmem.perBankRdBursts::5 18308 # Per bank write bursts 53system.physmem.perBankRdBursts::6 18094 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::7 17914 # Per bank write bursts | 54system.physmem.perBankRdBursts::7 17914 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::8 17936 # Per bank write bursts 56system.physmem.perBankRdBursts::9 17963 # Per bank write bursts 57system.physmem.perBankRdBursts::10 18015 # Per bank write bursts | 55system.physmem.perBankRdBursts::8 17939 # Per bank write bursts 56system.physmem.perBankRdBursts::9 17962 # Per bank write bursts 57system.physmem.perBankRdBursts::10 18018 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::11 18110 # Per bank write bursts | 58system.physmem.perBankRdBursts::11 18110 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::12 18146 # Per bank write bursts 60system.physmem.perBankRdBursts::13 18271 # Per bank write bursts 61system.physmem.perBankRdBursts::14 18075 # Per bank write bursts 62system.physmem.perBankRdBursts::15 18267 # Per bank write bursts | 59system.physmem.perBankRdBursts::12 18143 # Per bank write bursts 60system.physmem.perBankRdBursts::13 18270 # Per bank write bursts 61system.physmem.perBankRdBursts::14 18077 # Per bank write bursts 62system.physmem.perBankRdBursts::15 18266 # Per bank write bursts |
| 63system.physmem.perBankWrBursts::0 4174 # Per bank write bursts 64system.physmem.perBankWrBursts::1 4101 # Per bank write bursts 65system.physmem.perBankWrBursts::2 4137 # Per bank write bursts 66system.physmem.perBankWrBursts::3 4147 # Per bank write bursts 67system.physmem.perBankWrBursts::4 4225 # Per bank write bursts 68system.physmem.perBankWrBursts::5 4225 # Per bank write bursts 69system.physmem.perBankWrBursts::6 4171 # Per bank write bursts 70system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 71system.physmem.perBankWrBursts::8 4093 # Per bank write bursts 72system.physmem.perBankWrBursts::9 4093 # Per bank write bursts 73system.physmem.perBankWrBursts::10 4090 # Per bank write bursts 74system.physmem.perBankWrBursts::11 4094 # Per bank write bursts 75system.physmem.perBankWrBursts::12 4096 # Per bank write bursts 76system.physmem.perBankWrBursts::13 4094 # Per bank write bursts 77system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 78system.physmem.perBankWrBursts::15 4138 # Per bank write bursts 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 63system.physmem.perBankWrBursts::0 4174 # Per bank write bursts 64system.physmem.perBankWrBursts::1 4101 # Per bank write bursts 65system.physmem.perBankWrBursts::2 4137 # Per bank write bursts 66system.physmem.perBankWrBursts::3 4147 # Per bank write bursts 67system.physmem.perBankWrBursts::4 4225 # Per bank write bursts 68system.physmem.perBankWrBursts::5 4225 # Per bank write bursts 69system.physmem.perBankWrBursts::6 4171 # Per bank write bursts 70system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 71system.physmem.perBankWrBursts::8 4093 # Per bank write bursts 72system.physmem.perBankWrBursts::9 4093 # Per bank write bursts 73system.physmem.perBankWrBursts::10 4090 # Per bank write bursts 74system.physmem.perBankWrBursts::11 4094 # Per bank write bursts 75system.physmem.perBankWrBursts::12 4096 # Per bank write bursts 76system.physmem.perBankWrBursts::13 4094 # Per bank write bursts 77system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 78system.physmem.perBankWrBursts::15 4138 # Per bank write bursts 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 81system.physmem.totGap 541780987500 # Total gap between requests | 81system.physmem.totGap 541786012500 # Total gap between requests |
| 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) 88system.physmem.readPktSize::6 290529 # Read request sizes (log2) 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) 95system.physmem.writePktSize::6 66098 # Write request sizes (log2) | 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) 88system.physmem.readPktSize::6 290529 # Read request sizes (log2) 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) 95system.physmem.writePktSize::6 66098 # Write request sizes (log2) |
| 96system.physmem.rdQLenPdf::0 289809 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see | 96system.physmem.rdQLenPdf::0 289803 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 143system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 980 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 989 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 4006 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 4007 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::20 4008 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::20 4007 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 4007 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see |
| 155system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see |
| 156system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see | 156system.physmem.wrQLenPdf::28 4006 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 4006 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 4006 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 4006 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 4006 # What write queue length does an incoming req see |
| 161system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 161system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 192system.physmem.bytesPerActivate::samples 111520 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 204.445337 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 132.546078 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 256.289579 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 46919 42.07% 42.07% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 43694 39.18% 81.25% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 8696 7.80% 89.05% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 722 0.65% 89.70% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 1258 1.13% 90.83% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1255 1.13% 91.95% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 576 0.52% 92.47% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 502 0.45% 92.92% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 7898 7.08% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 111520 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 48.543798 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::gmean 36.072613 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::stdev 507.664819 # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes | 192system.physmem.bytesPerActivate::samples 111554 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 204.382452 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 132.554579 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 255.928936 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 47007 42.14% 42.14% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 43571 39.06% 81.20% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 8721 7.82% 89.01% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 769 0.69% 89.70% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 1361 1.22% 90.92% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1221 1.09% 92.02% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 537 0.48% 92.50% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 497 0.45% 92.95% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 111554 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 4006 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 48.553919 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::gmean 36.073633 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::stdev 507.732262 # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::0-1023 4003 99.93% 99.93% # Reads before turning the bus around for writes |
| 211system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes | 211system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 214system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes 215system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::mean 16.488645 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::gmean 16.467122 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::stdev 0.859477 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::16 3028 75.57% 75.57% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads 222system.physmem.totQLat 2702187250 # Total ticks spent queuing 223system.physmem.totMemAccLat 8143568500 # Total ticks spent from burst creation until serviced by the DRAM 224system.physmem.totBusLat 1451035000 # Total ticks spent in databus transfers 225system.physmem.avgQLat 9311.24 # Average queueing delay per DRAM burst | 214system.physmem.rdPerTurnAround::total 4006 # Reads before turning the bus around for writes 215system.physmem.wrPerTurnAround::samples 4006 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::mean 16.492761 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::gmean 16.471115 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::stdev 0.861913 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::16 3018 75.34% 75.34% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::17 3 0.07% 75.41% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::18 984 24.56% 99.98% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::total 4006 # Writes before turning the bus around for reads 224system.physmem.totQLat 2707676000 # Total ticks spent queuing 225system.physmem.totMemAccLat 8148907250 # Total ticks spent from burst creation until serviced by the DRAM 226system.physmem.totBusLat 1450995000 # Total ticks spent in databus transfers 227system.physmem.avgQLat 9330.41 # Average queueing delay per DRAM burst |
| 226system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 228system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 227system.physmem.avgMemAccLat 28061.24 # Average memory access latency per DRAM burst | 229system.physmem.avgMemAccLat 28080.41 # Average memory access latency per DRAM burst |
| 228system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s 229system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s 230system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s 231system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s 232system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 233system.physmem.busUtil 0.33 # Data bus utilization in percentage 234system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads 235system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 236system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 237system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing | 230system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s 231system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s 232system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s 233system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s 234system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 235system.physmem.busUtil 0.33 # Data bus utilization in percentage 236system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads 237system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 238system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 239system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing |
| 238system.physmem.readRowHits 194639 # Number of row buffer hits during reads 239system.physmem.writeRowHits 50105 # Number of row buffer hits during writes 240system.physmem.readRowHitRate 67.07 # Row buffer hit rate for reads 241system.physmem.writeRowHitRate 75.80 # Row buffer hit rate for writes 242system.physmem.avgGap 1519181.07 # Average gap between requests 243system.physmem.pageHitRate 68.69 # Row buffer hit rate, read and write combined 244system.physmem.memoryStateTime::IDLE 263887343000 # Time in different power states 245system.physmem.memoryStateTime::REF 18091060000 # Time in different power states 246system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 247system.physmem.memoryStateTime::ACT 259796939500 # Time in different power states 248system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 249system.physmem.actEnergy::0 421530480 # Energy for activate commands per rank (pJ) 250system.physmem.actEnergy::1 421462440 # Energy for activate commands per rank (pJ) 251system.physmem.preEnergy::0 230001750 # Energy for precharge commands per rank (pJ) 252system.physmem.preEnergy::1 229964625 # Energy for precharge commands per rank (pJ) 253system.physmem.readEnergy::0 1134174600 # Energy for read commands per rank (pJ) 254system.physmem.readEnergy::1 1128987600 # Energy for read commands per rank (pJ) 255system.physmem.writeEnergy::0 215628480 # Energy for write commands per rank (pJ) 256system.physmem.writeEnergy::1 212505120 # Energy for write commands per rank (pJ) 257system.physmem.refreshEnergy::0 35386113360 # Energy for refresh commands per rank (pJ) 258system.physmem.refreshEnergy::1 35386113360 # Energy for refresh commands per rank (pJ) 259system.physmem.actBackEnergy::0 105979651695 # Energy for active background per rank (pJ) 260system.physmem.actBackEnergy::1 105556941405 # Energy for active background per rank (pJ) 261system.physmem.preBackEnergy::0 232100586000 # Energy for precharge background per rank (pJ) 262system.physmem.preBackEnergy::1 232471384500 # Energy for precharge background per rank (pJ) 263system.physmem.totalEnergy::0 375467686365 # Total energy per rank (pJ) 264system.physmem.totalEnergy::1 375407359050 # Total energy per rank (pJ) 265system.physmem.averagePower::0 693.032096 # Core power per rank (mW) 266system.physmem.averagePower::1 692.920745 # Core power per rank (mW) | 240system.physmem.readRowHits 194608 # Number of row buffer hits during reads 241system.physmem.writeRowHits 50098 # Number of row buffer hits during writes 242system.physmem.readRowHitRate 67.06 # Row buffer hit rate for reads 243system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes 244system.physmem.avgGap 1519195.16 # Average gap between requests 245system.physmem.pageHitRate 68.68 # Row buffer hit rate, read and write combined 246system.physmem_0.actEnergy 421810200 # Energy for activate commands per rank (pJ) 247system.physmem_0.preEnergy 230154375 # Energy for precharge commands per rank (pJ) 248system.physmem_0.readEnergy 1134190200 # Energy for read commands per rank (pJ) 249system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) 250system.physmem_0.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) 251system.physmem_0.actBackEnergy 106352983170 # Energy for active background per rank (pJ) 252system.physmem_0.preBackEnergy 231777774000 # Energy for precharge background per rank (pJ) 253system.physmem_0.totalEnergy 375519162345 # Total energy per rank (pJ) 254system.physmem_0.averagePower 693.117148 # Core power per rank (mW) 255system.physmem_0.memoryStateTime::IDLE 384873582500 # Time in different power states 256system.physmem_0.memoryStateTime::REF 18091320000 # Time in different power states 257system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 258system.physmem_0.memoryStateTime::ACT 138818819500 # Time in different power states 259system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 260system.physmem_1.actEnergy 421477560 # Energy for activate commands per rank (pJ) 261system.physmem_1.preEnergy 229972875 # Energy for precharge commands per rank (pJ) 262system.physmem_1.readEnergy 1129034400 # Energy for read commands per rank (pJ) 263system.physmem_1.writeEnergy 212505120 # Energy for write commands per rank (pJ) 264system.physmem_1.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) 265system.physmem_1.actBackEnergy 105425199585 # Energy for active background per rank (pJ) 266system.physmem_1.preBackEnergy 232591619250 # Energy for precharge background per rank (pJ) 267system.physmem_1.totalEnergy 375396430710 # Total energy per rank (pJ) 268system.physmem_1.averagePower 692.890615 # Core power per rank (mW) 269system.physmem_1.memoryStateTime::IDLE 386233048000 # Time in different power states 270system.physmem_1.memoryStateTime::REF 18091320000 # Time in different power states 271system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 272system.physmem_1.memoryStateTime::ACT 137458753250 # Time in different power states 273system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 267system.cpu.branchPred.lookups 156937341 # Number of BP lookups 268system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted 269system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect 270system.cpu.branchPred.BTBLookups 97536058 # Number of BTB lookups 271system.cpu.branchPred.BTBHits 81874318 # Number of BTB hits 272system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 273system.cpu.branchPred.BTBHitPct 83.942615 # BTB Hit Percentage 274system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. 275system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. 276system.cpu_clk_domain.clock 500 # Clock period in ticks | 274system.cpu.branchPred.lookups 156937341 # Number of BP lookups 275system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted 276system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect 277system.cpu.branchPred.BTBLookups 97536058 # Number of BTB lookups 278system.cpu.branchPred.BTBHits 81874318 # Number of BTB hits 279system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 280system.cpu.branchPred.BTBHitPct 83.942615 # BTB Hit Percentage 281system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. 282system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. 283system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 284system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 288system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 277system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 278system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 279system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 280system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 281system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 282system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 290system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 291system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 292system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 293system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 294system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 295system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 296system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 297system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 292system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 293system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 294system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 295system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 296system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 297system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 298system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 299system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 305system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 306system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 307system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 308system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 309system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 310system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 311system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 312system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 313system.cpu.dtb.walker.walks 0 # Table walker walks requested 314system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 318system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 319system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 298system.cpu.dtb.inst_hits 0 # ITB inst hits 299system.cpu.dtb.inst_misses 0 # ITB inst misses 300system.cpu.dtb.read_hits 0 # DTB read hits 301system.cpu.dtb.read_misses 0 # DTB read misses 302system.cpu.dtb.write_hits 0 # DTB write hits 303system.cpu.dtb.write_misses 0 # DTB write misses 304system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 305system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 311system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 312system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 313system.cpu.dtb.read_accesses 0 # DTB read accesses 314system.cpu.dtb.write_accesses 0 # DTB write accesses 315system.cpu.dtb.inst_accesses 0 # ITB inst accesses 316system.cpu.dtb.hits 0 # DTB hits 317system.cpu.dtb.misses 0 # DTB misses 318system.cpu.dtb.accesses 0 # DTB accesses | 321system.cpu.dtb.inst_hits 0 # ITB inst hits 322system.cpu.dtb.inst_misses 0 # ITB inst misses 323system.cpu.dtb.read_hits 0 # DTB read hits 324system.cpu.dtb.read_misses 0 # DTB read misses 325system.cpu.dtb.write_hits 0 # DTB write hits 326system.cpu.dtb.write_misses 0 # DTB write misses 327system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 328system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 334system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 335system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 336system.cpu.dtb.read_accesses 0 # DTB read accesses 337system.cpu.dtb.write_accesses 0 # DTB write accesses 338system.cpu.dtb.inst_accesses 0 # ITB inst accesses 339system.cpu.dtb.hits 0 # DTB hits 340system.cpu.dtb.misses 0 # DTB misses 341system.cpu.dtb.accesses 0 # DTB accesses |
| 342system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 343system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 319system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 320system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 321system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 322system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 323system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 324system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 325system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 326system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 332system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 333system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 334system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 335system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 336system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 337system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 338system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 339system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 350system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 351system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 352system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 353system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 354system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 355system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 356system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 357system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 363system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 364system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 365system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 366system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 367system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 368system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 369system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 370system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 371system.cpu.itb.walker.walks 0 # Table walker walks requested 372system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 373system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 374system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 375system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 340system.cpu.itb.inst_hits 0 # ITB inst hits 341system.cpu.itb.inst_misses 0 # ITB inst misses 342system.cpu.itb.read_hits 0 # DTB read hits 343system.cpu.itb.read_misses 0 # DTB read misses 344system.cpu.itb.write_hits 0 # DTB write hits 345system.cpu.itb.write_misses 0 # DTB write misses 346system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 347system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 354system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.itb.read_accesses 0 # DTB read accesses 356system.cpu.itb.write_accesses 0 # DTB write accesses 357system.cpu.itb.inst_accesses 0 # ITB inst accesses 358system.cpu.itb.hits 0 # DTB hits 359system.cpu.itb.misses 0 # DTB misses 360system.cpu.itb.accesses 0 # DTB accesses 361system.cpu.workload.num_syscalls 673 # Number of system calls | 379system.cpu.itb.inst_hits 0 # ITB inst hits 380system.cpu.itb.inst_misses 0 # ITB inst misses 381system.cpu.itb.read_hits 0 # DTB read hits 382system.cpu.itb.read_misses 0 # DTB read misses 383system.cpu.itb.write_hits 0 # DTB write hits 384system.cpu.itb.write_misses 0 # DTB write misses 385system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 386system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 393system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 394system.cpu.itb.read_accesses 0 # DTB read accesses 395system.cpu.itb.write_accesses 0 # DTB write accesses 396system.cpu.itb.inst_accesses 0 # ITB inst accesses 397system.cpu.itb.hits 0 # DTB hits 398system.cpu.itb.misses 0 # DTB misses 399system.cpu.itb.accesses 0 # DTB accesses 400system.cpu.workload.num_syscalls 673 # Number of system calls |
| 362system.cpu.numCycles 1083562152 # number of cpu cycles simulated | 401system.cpu.numCycles 1083572202 # number of cpu cycles simulated |
| 363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 364system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 365system.cpu.committedInsts 640655084 # Number of instructions committed 366system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed 367system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit 368system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 402system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 403system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 404system.cpu.committedInsts 640655084 # Number of instructions committed 405system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed 406system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit 407system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 369system.cpu.cpi 1.691335 # CPI: cycles per instruction 370system.cpu.ipc 0.591249 # IPC: instructions per cycle 371system.cpu.tickCycles 1029140125 # Number of cycles that the object actually ticked 372system.cpu.idleCycles 54422027 # Total number of cycles that the object has spent stopped | 408system.cpu.cpi 1.691350 # CPI: cycles per instruction 409system.cpu.ipc 0.591244 # IPC: instructions per cycle 410system.cpu.tickCycles 1029141566 # Number of cycles that the object actually ticked 411system.cpu.idleCycles 54430636 # Total number of cycles that the object has spent stopped |
| 373system.cpu.dcache.tags.replacements 778221 # number of replacements | 412system.cpu.dcache.tags.replacements 778221 # number of replacements |
| 374system.cpu.dcache.tags.tagsinuse 4092.644165 # Cycle average of tags in use | 413system.cpu.dcache.tags.tagsinuse 4092.645412 # Cycle average of tags in use |
| 375system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. 376system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. 377system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. | 414system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. 415system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. 416system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. |
| 378system.cpu.dcache.tags.warmup_cycle 752182250 # Cycle when the warmup percentage was hit. 379system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.644165 # Average occupied blocks per requestor | 417system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. 418system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.645412 # Average occupied blocks per requestor |
| 380system.cpu.dcache.tags.occ_percent::cpu.inst 0.999181 # Average percentage of cache occupancy 381system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy 382system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 383system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 384system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id 385system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id 386system.cpu.dcache.tags.age_task_id_blocks_1024::3 1341 # Occupied blocks per task id 387system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id --- 15 unchanged lines hidden (view full) --- 403system.cpu.dcache.ReadReq_misses::cpu.inst 713747 # number of ReadReq misses 404system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses 405system.cpu.dcache.WriteReq_misses::cpu.inst 137713 # number of WriteReq misses 406system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses 407system.cpu.dcache.demand_misses::cpu.inst 851460 # number of demand (read+write) misses 408system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses 409system.cpu.dcache.overall_misses::cpu.inst 851460 # number of overall misses 410system.cpu.dcache.overall_misses::total 851460 # number of overall misses | 419system.cpu.dcache.tags.occ_percent::cpu.inst 0.999181 # Average percentage of cache occupancy 420system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy 421system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 422system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 423system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id 424system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id 425system.cpu.dcache.tags.age_task_id_blocks_1024::3 1341 # Occupied blocks per task id 426system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id --- 15 unchanged lines hidden (view full) --- 442system.cpu.dcache.ReadReq_misses::cpu.inst 713747 # number of ReadReq misses 443system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses 444system.cpu.dcache.WriteReq_misses::cpu.inst 137713 # number of WriteReq misses 445system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses 446system.cpu.dcache.demand_misses::cpu.inst 851460 # number of demand (read+write) misses 447system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses 448system.cpu.dcache.overall_misses::cpu.inst 851460 # number of overall misses 449system.cpu.dcache.overall_misses::total 851460 # number of overall misses |
| 411system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23050728217 # number of ReadReq miss cycles 412system.cpu.dcache.ReadReq_miss_latency::total 23050728217 # number of ReadReq miss cycles 413system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9196889000 # number of WriteReq miss cycles 414system.cpu.dcache.WriteReq_miss_latency::total 9196889000 # number of WriteReq miss cycles 415system.cpu.dcache.demand_miss_latency::cpu.inst 32247617217 # number of demand (read+write) miss cycles 416system.cpu.dcache.demand_miss_latency::total 32247617217 # number of demand (read+write) miss cycles 417system.cpu.dcache.overall_miss_latency::cpu.inst 32247617217 # number of overall miss cycles 418system.cpu.dcache.overall_miss_latency::total 32247617217 # number of overall miss cycles | 450system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23055853217 # number of ReadReq miss cycles 451system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles 452system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9199211000 # number of WriteReq miss cycles 453system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles 454system.cpu.dcache.demand_miss_latency::cpu.inst 32255064217 # number of demand (read+write) miss cycles 455system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles 456system.cpu.dcache.overall_miss_latency::cpu.inst 32255064217 # number of overall miss cycles 457system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles |
| 419system.cpu.dcache.ReadReq_accesses::cpu.inst 250346252 # number of ReadReq accesses(hits+misses) 420system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) 421system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) 422system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 423system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) 424system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 425system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) 426system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 431system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses 432system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses 433system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001068 # miss rate for WriteReq accesses 434system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 435system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses 436system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses 437system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses 438system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses | 458system.cpu.dcache.ReadReq_accesses::cpu.inst 250346252 # number of ReadReq accesses(hits+misses) 459system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) 460system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) 461system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 462system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) 463system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 464system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) 465system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 470system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses 471system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses 472system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001068 # miss rate for WriteReq accesses 473system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 474system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses 475system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses 476system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses 477system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses |
| 439system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32295.376677 # average ReadReq miss latency 440system.cpu.dcache.ReadReq_avg_miss_latency::total 32295.376677 # average ReadReq miss latency 441system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66783.012497 # average WriteReq miss latency 442system.cpu.dcache.WriteReq_avg_miss_latency::total 66783.012497 # average WriteReq miss latency 443system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency 444system.cpu.dcache.demand_avg_miss_latency::total 37873.320199 # average overall miss latency 445system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency 446system.cpu.dcache.overall_avg_miss_latency::total 37873.320199 # average overall miss latency | 478system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32302.557092 # average ReadReq miss latency 479system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency 480system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66799.873650 # average WriteReq miss latency 481system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency 482system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency 483system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency 484system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency 485system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency |
| 447system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 448system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 449system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 451system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 453system.cpu.dcache.fast_writes 0 # number of fast writes performed 454system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 465system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712995 # number of ReadReq MSHR misses 466system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses 467system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69322 # number of WriteReq MSHR misses 468system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 469system.cpu.dcache.demand_mshr_misses::cpu.inst 782317 # number of demand (read+write) MSHR misses 470system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses 471system.cpu.dcache.overall_mshr_misses::cpu.inst 782317 # number of overall MSHR misses 472system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses | 486system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 487system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 488system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 489system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 490system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 491system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 492system.cpu.dcache.fast_writes 0 # number of fast writes performed 493system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 504system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712995 # number of ReadReq MSHR misses 505system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses 506system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69322 # number of WriteReq MSHR misses 507system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 508system.cpu.dcache.demand_mshr_misses::cpu.inst 782317 # number of demand (read+write) MSHR misses 509system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses 510system.cpu.dcache.overall_mshr_misses::cpu.inst 782317 # number of overall MSHR misses 511system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses |
| 473system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21540338778 # number of ReadReq MSHR miss cycles 474system.cpu.dcache.ReadReq_mshr_miss_latency::total 21540338778 # number of ReadReq MSHR miss cycles 475system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4529678750 # number of WriteReq MSHR miss cycles 476system.cpu.dcache.WriteReq_mshr_miss_latency::total 4529678750 # number of WriteReq MSHR miss cycles 477system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26070017528 # number of demand (read+write) MSHR miss cycles 478system.cpu.dcache.demand_mshr_miss_latency::total 26070017528 # number of demand (read+write) MSHR miss cycles 479system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26070017528 # number of overall MSHR miss cycles 480system.cpu.dcache.overall_mshr_miss_latency::total 26070017528 # number of overall MSHR miss cycles | 512system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21545578028 # number of ReadReq MSHR miss cycles 513system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles 514system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4531082000 # number of WriteReq MSHR miss cycles 515system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles 516system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26076660028 # number of demand (read+write) MSHR miss cycles 517system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles 518system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26076660028 # number of overall MSHR miss cycles 519system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles |
| 481system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses 482system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses 483system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses 484system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 485system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses 486system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses 487system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses 488system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses | 520system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses 521system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses 522system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses 523system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 524system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses 525system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses 526system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses 527system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses |
| 489system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30211.065685 # average ReadReq mshr miss latency 490system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30211.065685 # average ReadReq mshr miss latency 491system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65342.586048 # average WriteReq mshr miss latency 492system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65342.586048 # average WriteReq mshr miss latency 493system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency 494system.cpu.dcache.demand_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency 495system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency 496system.cpu.dcache.overall_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency | 528system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30218.413913 # average ReadReq mshr miss latency 529system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency 530system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65362.828539 # average WriteReq mshr miss latency 531system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency 532system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency 533system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency 534system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency 535system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency |
| 497system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 498system.cpu.icache.tags.replacements 23590 # number of replacements | 536system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 537system.cpu.icache.tags.replacements 23590 # number of replacements |
| 499system.cpu.icache.tags.tagsinuse 1712.180354 # Cycle average of tags in use 500system.cpu.icache.tags.total_refs 289921724 # Total number of references to valid blocks. | 538system.cpu.icache.tags.tagsinuse 1712.180561 # Cycle average of tags in use 539system.cpu.icache.tags.total_refs 289921723 # Total number of references to valid blocks. |
| 501system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. | 540system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. |
| 502system.cpu.icache.tags.avg_refs 11440.816227 # Average number of references to valid blocks. | 541system.cpu.icache.tags.avg_refs 11440.816187 # Average number of references to valid blocks. |
| 503system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 542system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 504system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180354 # Average occupied blocks per requestor | 543system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180561 # Average occupied blocks per requestor |
| 505system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy 506system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy 507system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id 508system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 509system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 510system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id 511system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id | 544system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy 545system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy 546system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id 547system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 548system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 549system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id 550system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id |
| 512system.cpu.icache.tags.tag_accesses 579919473 # Number of tag accesses 513system.cpu.icache.tags.data_accesses 579919473 # Number of data accesses 514system.cpu.icache.ReadReq_hits::cpu.inst 289921724 # number of ReadReq hits 515system.cpu.icache.ReadReq_hits::total 289921724 # number of ReadReq hits 516system.cpu.icache.demand_hits::cpu.inst 289921724 # number of demand (read+write) hits 517system.cpu.icache.demand_hits::total 289921724 # number of demand (read+write) hits 518system.cpu.icache.overall_hits::cpu.inst 289921724 # number of overall hits 519system.cpu.icache.overall_hits::total 289921724 # number of overall hits | 551system.cpu.icache.tags.tag_accesses 579919471 # Number of tag accesses 552system.cpu.icache.tags.data_accesses 579919471 # Number of data accesses 553system.cpu.icache.ReadReq_hits::cpu.inst 289921723 # number of ReadReq hits 554system.cpu.icache.ReadReq_hits::total 289921723 # number of ReadReq hits 555system.cpu.icache.demand_hits::cpu.inst 289921723 # number of demand (read+write) hits 556system.cpu.icache.demand_hits::total 289921723 # number of demand (read+write) hits 557system.cpu.icache.overall_hits::cpu.inst 289921723 # number of overall hits 558system.cpu.icache.overall_hits::total 289921723 # number of overall hits |
| 520system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses 521system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses 522system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses 523system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses 524system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses 525system.cpu.icache.overall_misses::total 25342 # number of overall misses | 559system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses 560system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses 561system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses 562system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses 563system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses 564system.cpu.icache.overall_misses::total 25342 # number of overall misses |
| 526system.cpu.icache.ReadReq_miss_latency::cpu.inst 481750746 # number of ReadReq miss cycles 527system.cpu.icache.ReadReq_miss_latency::total 481750746 # number of ReadReq miss cycles 528system.cpu.icache.demand_miss_latency::cpu.inst 481750746 # number of demand (read+write) miss cycles 529system.cpu.icache.demand_miss_latency::total 481750746 # number of demand (read+write) miss cycles 530system.cpu.icache.overall_miss_latency::cpu.inst 481750746 # number of overall miss cycles 531system.cpu.icache.overall_miss_latency::total 481750746 # number of overall miss cycles 532system.cpu.icache.ReadReq_accesses::cpu.inst 289947066 # number of ReadReq accesses(hits+misses) 533system.cpu.icache.ReadReq_accesses::total 289947066 # number of ReadReq accesses(hits+misses) 534system.cpu.icache.demand_accesses::cpu.inst 289947066 # number of demand (read+write) accesses 535system.cpu.icache.demand_accesses::total 289947066 # number of demand (read+write) accesses 536system.cpu.icache.overall_accesses::cpu.inst 289947066 # number of overall (read+write) accesses 537system.cpu.icache.overall_accesses::total 289947066 # number of overall (read+write) accesses | 565system.cpu.icache.ReadReq_miss_latency::cpu.inst 480693746 # number of ReadReq miss cycles 566system.cpu.icache.ReadReq_miss_latency::total 480693746 # number of ReadReq miss cycles 567system.cpu.icache.demand_miss_latency::cpu.inst 480693746 # number of demand (read+write) miss cycles 568system.cpu.icache.demand_miss_latency::total 480693746 # number of demand (read+write) miss cycles 569system.cpu.icache.overall_miss_latency::cpu.inst 480693746 # number of overall miss cycles 570system.cpu.icache.overall_miss_latency::total 480693746 # number of overall miss cycles 571system.cpu.icache.ReadReq_accesses::cpu.inst 289947065 # number of ReadReq accesses(hits+misses) 572system.cpu.icache.ReadReq_accesses::total 289947065 # number of ReadReq accesses(hits+misses) 573system.cpu.icache.demand_accesses::cpu.inst 289947065 # number of demand (read+write) accesses 574system.cpu.icache.demand_accesses::total 289947065 # number of demand (read+write) accesses 575system.cpu.icache.overall_accesses::cpu.inst 289947065 # number of overall (read+write) accesses 576system.cpu.icache.overall_accesses::total 289947065 # number of overall (read+write) accesses |
| 538system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses 539system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses 540system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses 541system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses 542system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses 543system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses | 577system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses 578system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses 579system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses 580system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses 581system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses 582system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses |
| 544system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19009.973404 # average ReadReq miss latency 545system.cpu.icache.ReadReq_avg_miss_latency::total 19009.973404 # average ReadReq miss latency 546system.cpu.icache.demand_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency 547system.cpu.icache.demand_avg_miss_latency::total 19009.973404 # average overall miss latency 548system.cpu.icache.overall_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency 549system.cpu.icache.overall_avg_miss_latency::total 19009.973404 # average overall miss latency | 583system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.263989 # average ReadReq miss latency 584system.cpu.icache.ReadReq_avg_miss_latency::total 18968.263989 # average ReadReq miss latency 585system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency 586system.cpu.icache.demand_avg_miss_latency::total 18968.263989 # average overall miss latency 587system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency 588system.cpu.icache.overall_avg_miss_latency::total 18968.263989 # average overall miss latency |
| 550system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 551system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 552system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 553system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 554system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 555system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 556system.cpu.icache.fast_writes 0 # number of fast writes performed 557system.cpu.icache.cache_copies 0 # number of cache copies performed 558system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25342 # number of ReadReq MSHR misses 559system.cpu.icache.ReadReq_mshr_misses::total 25342 # number of ReadReq MSHR misses 560system.cpu.icache.demand_mshr_misses::cpu.inst 25342 # number of demand (read+write) MSHR misses 561system.cpu.icache.demand_mshr_misses::total 25342 # number of demand (read+write) MSHR misses 562system.cpu.icache.overall_mshr_misses::cpu.inst 25342 # number of overall MSHR misses 563system.cpu.icache.overall_mshr_misses::total 25342 # number of overall MSHR misses | 589system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 590system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 591system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 592system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 593system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 594system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 595system.cpu.icache.fast_writes 0 # number of fast writes performed 596system.cpu.icache.cache_copies 0 # number of cache copies performed 597system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25342 # number of ReadReq MSHR misses 598system.cpu.icache.ReadReq_mshr_misses::total 25342 # number of ReadReq MSHR misses 599system.cpu.icache.demand_mshr_misses::cpu.inst 25342 # number of demand (read+write) MSHR misses 600system.cpu.icache.demand_mshr_misses::total 25342 # number of demand (read+write) MSHR misses 601system.cpu.icache.overall_mshr_misses::cpu.inst 25342 # number of overall MSHR misses 602system.cpu.icache.overall_mshr_misses::total 25342 # number of overall MSHR misses |
| 564system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429966254 # number of ReadReq MSHR miss cycles 565system.cpu.icache.ReadReq_mshr_miss_latency::total 429966254 # number of ReadReq MSHR miss cycles 566system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429966254 # number of demand (read+write) MSHR miss cycles 567system.cpu.icache.demand_mshr_miss_latency::total 429966254 # number of demand (read+write) MSHR miss cycles 568system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429966254 # number of overall MSHR miss cycles 569system.cpu.icache.overall_mshr_miss_latency::total 429966254 # number of overall MSHR miss cycles | 603system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428909254 # number of ReadReq MSHR miss cycles 604system.cpu.icache.ReadReq_mshr_miss_latency::total 428909254 # number of ReadReq MSHR miss cycles 605system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428909254 # number of demand (read+write) MSHR miss cycles 606system.cpu.icache.demand_mshr_miss_latency::total 428909254 # number of demand (read+write) MSHR miss cycles 607system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428909254 # number of overall MSHR miss cycles 608system.cpu.icache.overall_mshr_miss_latency::total 428909254 # number of overall MSHR miss cycles |
| 570system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses 571system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses 572system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses 573system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses 574system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses 575system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses | 609system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses 610system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses 611system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses 612system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses 613system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses 614system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses |
| 576system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16966.547786 # average ReadReq mshr miss latency 577system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16966.547786 # average ReadReq mshr miss latency 578system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency 579system.cpu.icache.demand_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency 580system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency 581system.cpu.icache.overall_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency | 615system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.838371 # average ReadReq mshr miss latency 616system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.838371 # average ReadReq mshr miss latency 617system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency 618system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency 619system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency 620system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency |
| 582system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 583system.cpu.l2cache.tags.replacements 257749 # number of replacements | 621system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 622system.cpu.l2cache.tags.replacements 257749 # number of replacements |
| 584system.cpu.l2cache.tags.tagsinuse 32583.074549 # Cycle average of tags in use | 623system.cpu.l2cache.tags.tagsinuse 32583.111771 # Cycle average of tags in use |
| 585system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks. 586system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. 587system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. 588system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 624system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks. 625system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. 626system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. 627system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 589system.cpu.l2cache.tags.occ_blocks::writebacks 2860.585859 # Average occupied blocks per requestor 590system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.488690 # Average occupied blocks per requestor 591system.cpu.l2cache.tags.occ_percent::writebacks 0.087298 # Average percentage of cache occupancy 592system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907058 # Average percentage of cache occupancy 593system.cpu.l2cache.tags.occ_percent::total 0.994357 # Average percentage of cache occupancy | 628system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor 629system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.446536 # Average occupied blocks per requestor 630system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy 631system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907057 # Average percentage of cache occupancy 632system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy |
| 594system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id 595system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 596system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 597system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 598system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2800 # Occupied blocks per task id 599system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 # Occupied blocks per task id 600system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id 601system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses --- 11 unchanged lines hidden (view full) --- 613system.cpu.l2cache.ReadReq_misses::cpu.inst 224471 # number of ReadReq misses 614system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses 615system.cpu.l2cache.ReadExReq_misses::cpu.inst 66091 # number of ReadExReq misses 616system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses 617system.cpu.l2cache.demand_misses::cpu.inst 290562 # number of demand (read+write) misses 618system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses 619system.cpu.l2cache.overall_misses::cpu.inst 290562 # number of overall misses 620system.cpu.l2cache.overall_misses::total 290562 # number of overall misses | 633system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id 634system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 635system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 636system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 637system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2800 # Occupied blocks per task id 638system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 # Occupied blocks per task id 639system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id 640system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses --- 11 unchanged lines hidden (view full) --- 652system.cpu.l2cache.ReadReq_misses::cpu.inst 224471 # number of ReadReq misses 653system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses 654system.cpu.l2cache.ReadExReq_misses::cpu.inst 66091 # number of ReadExReq misses 655system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses 656system.cpu.l2cache.demand_misses::cpu.inst 290562 # number of demand (read+write) misses 657system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses 658system.cpu.l2cache.overall_misses::cpu.inst 290562 # number of overall misses 659system.cpu.l2cache.overall_misses::total 290562 # number of overall misses |
| 621system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16093224000 # number of ReadReq miss cycles 622system.cpu.l2cache.ReadReq_miss_latency::total 16093224000 # number of ReadReq miss cycles 623system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4428044750 # number of ReadExReq miss cycles 624system.cpu.l2cache.ReadExReq_miss_latency::total 4428044750 # number of ReadExReq miss cycles 625system.cpu.l2cache.demand_miss_latency::cpu.inst 20521268750 # number of demand (read+write) miss cycles 626system.cpu.l2cache.demand_miss_latency::total 20521268750 # number of demand (read+write) miss cycles 627system.cpu.l2cache.overall_miss_latency::cpu.inst 20521268750 # number of overall miss cycles 628system.cpu.l2cache.overall_miss_latency::total 20521268750 # number of overall miss cycles | 660system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16097406250 # number of ReadReq miss cycles 661system.cpu.l2cache.ReadReq_miss_latency::total 16097406250 # number of ReadReq miss cycles 662system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4429448000 # number of ReadExReq miss cycles 663system.cpu.l2cache.ReadExReq_miss_latency::total 4429448000 # number of ReadExReq miss cycles 664system.cpu.l2cache.demand_miss_latency::cpu.inst 20526854250 # number of demand (read+write) miss cycles 665system.cpu.l2cache.demand_miss_latency::total 20526854250 # number of demand (read+write) miss cycles 666system.cpu.l2cache.overall_miss_latency::cpu.inst 20526854250 # number of overall miss cycles 667system.cpu.l2cache.overall_miss_latency::total 20526854250 # number of overall miss cycles |
| 629system.cpu.l2cache.ReadReq_accesses::cpu.inst 738337 # number of ReadReq accesses(hits+misses) 630system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) 631system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) 632system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) 633system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69322 # number of ReadExReq accesses(hits+misses) 634system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 635system.cpu.l2cache.demand_accesses::cpu.inst 807659 # number of demand (read+write) accesses 636system.cpu.l2cache.demand_accesses::total 807659 # number of demand (read+write) accesses 637system.cpu.l2cache.overall_accesses::cpu.inst 807659 # number of overall (read+write) accesses 638system.cpu.l2cache.overall_accesses::total 807659 # number of overall (read+write) accesses 639system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.304022 # miss rate for ReadReq accesses 640system.cpu.l2cache.ReadReq_miss_rate::total 0.304022 # miss rate for ReadReq accesses 641system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953391 # miss rate for ReadExReq accesses 642system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses 643system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359758 # miss rate for demand accesses 644system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses 645system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359758 # miss rate for overall accesses 646system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses | 668system.cpu.l2cache.ReadReq_accesses::cpu.inst 738337 # number of ReadReq accesses(hits+misses) 669system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) 670system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) 671system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) 672system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69322 # number of ReadExReq accesses(hits+misses) 673system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 674system.cpu.l2cache.demand_accesses::cpu.inst 807659 # number of demand (read+write) accesses 675system.cpu.l2cache.demand_accesses::total 807659 # number of demand (read+write) accesses 676system.cpu.l2cache.overall_accesses::cpu.inst 807659 # number of overall (read+write) accesses 677system.cpu.l2cache.overall_accesses::total 807659 # number of overall (read+write) accesses 678system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.304022 # miss rate for ReadReq accesses 679system.cpu.l2cache.ReadReq_miss_rate::total 0.304022 # miss rate for ReadReq accesses 680system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953391 # miss rate for ReadExReq accesses 681system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses 682system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359758 # miss rate for demand accesses 683system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses 684system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359758 # miss rate for overall accesses 685system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses |
| 647system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71694.000561 # average ReadReq miss latency 648system.cpu.l2cache.ReadReq_avg_miss_latency::total 71694.000561 # average ReadReq miss latency 649system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66999.209423 # average ReadExReq miss latency 650system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66999.209423 # average ReadExReq miss latency 651system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency 652system.cpu.l2cache.demand_avg_miss_latency::total 70626.127126 # average overall miss latency 653system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency 654system.cpu.l2cache.overall_avg_miss_latency::total 70626.127126 # average overall miss latency | 686system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71712.632144 # average ReadReq miss latency 687system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144 # average ReadReq miss latency 688system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67020.441512 # average ReadExReq miss latency 689system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512 # average ReadExReq miss latency 690system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency 691system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218 # average overall miss latency 692system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency 693system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency |
| 655system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 656system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 657system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 658system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 659system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 660system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 661system.cpu.l2cache.fast_writes 0 # number of fast writes performed 662system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 671system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224439 # number of ReadReq MSHR misses 672system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses 673system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66091 # number of ReadExReq MSHR misses 674system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses 675system.cpu.l2cache.demand_mshr_misses::cpu.inst 290530 # number of demand (read+write) MSHR misses 676system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.overall_mshr_misses::cpu.inst 290530 # number of overall MSHR misses 678system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses | 694system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 695system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 696system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 697system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 698system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 699system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 700system.cpu.l2cache.fast_writes 0 # number of fast writes performed 701system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 710system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224439 # number of ReadReq MSHR misses 711system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses 712system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66091 # number of ReadExReq MSHR misses 713system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses 714system.cpu.l2cache.demand_mshr_misses::cpu.inst 290530 # number of demand (read+write) MSHR misses 715system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses 716system.cpu.l2cache.overall_mshr_misses::cpu.inst 290530 # number of overall MSHR misses 717system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses |
| 679system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13281416250 # number of ReadReq MSHR miss cycles 680system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13281416250 # number of ReadReq MSHR miss cycles 681system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3575940250 # number of ReadExReq MSHR miss cycles 682system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3575940250 # number of ReadExReq MSHR miss cycles 683system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16857356500 # number of demand (read+write) MSHR miss cycles 684system.cpu.l2cache.demand_mshr_miss_latency::total 16857356500 # number of demand (read+write) MSHR miss cycles 685system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16857356500 # number of overall MSHR miss cycles 686system.cpu.l2cache.overall_mshr_miss_latency::total 16857356500 # number of overall MSHR miss cycles | 718system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13285316750 # number of ReadReq MSHR miss cycles 719system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles 720system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3577310000 # number of ReadExReq MSHR miss cycles 721system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles 722system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16862626750 # number of demand (read+write) MSHR miss cycles 723system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles 724system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16862626750 # number of overall MSHR miss cycles 725system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles |
| 687system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303979 # mshr miss rate for ReadReq accesses 688system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses 689system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953391 # mshr miss rate for ReadExReq accesses 690system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 691system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for demand accesses 692system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses 693system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for overall accesses 694system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses | 726system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303979 # mshr miss rate for ReadReq accesses 727system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses 728system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953391 # mshr miss rate for ReadExReq accesses 729system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 730system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for demand accesses 731system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses 732system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for overall accesses 733system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses |
| 695system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59176.062315 # average ReadReq mshr miss latency 696system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59176.062315 # average ReadReq mshr miss latency 697system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54106.311752 # average ReadExReq mshr miss latency 698system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54106.311752 # average ReadExReq mshr miss latency 699system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58022.773896 # average overall mshr miss latency 700system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58022.773896 # average overall mshr miss latency 701system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58022.773896 # average overall mshr miss latency 702system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58022.773896 # average overall mshr miss latency | 734system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59193.441202 # average ReadReq mshr miss latency 735system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency 736system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54127.036964 # average ReadExReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency 740system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency |
| 703system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 704system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution 705system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution 706system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution 707system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 708system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 709system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683 # Packet count per connected master and slave (bytes) 710system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656054 # Packet count per connected master and slave (bytes) --- 16 unchanged lines hidden (view full) --- 727system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 728system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 729system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 730system.cpu.toL2Bus.snoop_fanout::total 899079 # Request fanout histogram 731system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # Layer occupancy (ticks) 732system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 733system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) 734system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 742system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 743system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution 744system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution 745system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution 746system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 747system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 748system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683 # Packet count per connected master and slave (bytes) 749system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656054 # Packet count per connected master and slave (bytes) --- 16 unchanged lines hidden (view full) --- 766system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 767system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 768system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 769system.cpu.toL2Bus.snoop_fanout::total 899079 # Request fanout histogram 770system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # Layer occupancy (ticks) 771system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 772system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) 773system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 735system.cpu.toL2Bus.respLayer1.occupancy 1224341972 # Layer occupancy (ticks) | 774system.cpu.toL2Bus.respLayer1.occupancy 1224351972 # Layer occupancy (ticks) |
| 736system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 737system.membus.trans_dist::ReadReq 224438 # Transaction distribution 738system.membus.trans_dist::ReadResp 224438 # Transaction distribution 739system.membus.trans_dist::Writeback 66098 # Transaction distribution 740system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 741system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 742system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) 743system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 749system.membus.snoop_fanout::stdev 0 # Request fanout histogram 750system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 751system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram 752system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 753system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 754system.membus.snoop_fanout::min_value 0 # Request fanout histogram 755system.membus.snoop_fanout::max_value 0 # Request fanout histogram 756system.membus.snoop_fanout::total 356627 # Request fanout histogram | 775system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 776system.membus.trans_dist::ReadReq 224438 # Transaction distribution 777system.membus.trans_dist::ReadResp 224438 # Transaction distribution 778system.membus.trans_dist::Writeback 66098 # Transaction distribution 779system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 780system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 781system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) 782system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 788system.membus.snoop_fanout::stdev 0 # Request fanout histogram 789system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 790system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram 791system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 792system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 793system.membus.snoop_fanout::min_value 0 # Request fanout histogram 794system.membus.snoop_fanout::max_value 0 # Request fanout histogram 795system.membus.snoop_fanout::total 356627 # Request fanout histogram |
| 757system.membus.reqLayer0.occupancy 983533000 # Layer occupancy (ticks) | 796system.membus.reqLayer0.occupancy 983550500 # Layer occupancy (ticks) |
| 758system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) | 797system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 759system.membus.respLayer1.occupancy 2738969000 # Layer occupancy (ticks) | 798system.membus.respLayer1.occupancy 2739032750 # Layer occupancy (ticks) |
| 760system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 761 762---------- End Simulation Statistics ---------- | 799system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 800 801---------- End Simulation Statistics ---------- |