Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt

Deleted Added

sdiff udiff text old ( 11687:b3d5f0e9e258 ) new ( 11860:67dee11badea )

full compact

3,5c3,5
< sim_seconds 0.525654 # Number of seconds simulated
< sim_ticks 525654485500 # Number of ticks simulated
< final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.525648 # Number of seconds simulated
> sim_ticks 525647850500 # Number of ticks simulated
> final_tick 525647850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 282925 # Simulator instruction rate (inst/s)
< host_op_rate 348318 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 232138645 # Simulator tick rate (ticks/s)
< host_mem_usage 279272 # Number of bytes of host memory used
< host_seconds 2264.40 # Real time elapsed on the host
---
> host_inst_rate 304424 # Simulator instruction rate (inst/s)
> host_op_rate 374786 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 249775392 # Simulator tick rate (ticks/s)
> host_mem_usage 281156 # Number of bytes of host memory used
> host_seconds 2104.48 # Real time elapsed on the host
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory
19,21c19,21
< system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::total 18639040 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory
24c24
< system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory
26c26
< system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::total 291235 # Number of read requests responded to by this memory
29,40c29,40
< system.physmem.bw_read::cpu.inst 312296 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 35145702 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 35457999 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 312296 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 312296 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 8047628 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8047628 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8047628 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 312296 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 35145702 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 43505627 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 291229 # Number of read requests accepted
---
> system.physmem.bw_read::cpu.inst 313031 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 35146146 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 35459177 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 313031 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 313031 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 8047730 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8047730 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8047730 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 313031 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 35146146 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 43506907 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 291235 # Number of read requests accepted
42c42
< system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 291235 # Number of DRAM read bursts, including those serviced by the write queue
44,47c44,47
< system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4229248 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side
---
> system.physmem.bytesReadDRAM 18619136 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 18639040 # Total read bytes from the system interface side
49c49
< system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue
52,58c52,58
< system.physmem.perBankRdBursts::0 18281 # Per bank write bursts
< system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
< system.physmem.perBankRdBursts::2 18221 # Per bank write bursts
< system.physmem.perBankRdBursts::3 18176 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18285 # Per bank write bursts
< system.physmem.perBankRdBursts::5 18412 # Per bank write bursts
< system.physmem.perBankRdBursts::6 18178 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 18288 # Per bank write bursts
> system.physmem.perBankRdBursts::1 18134 # Per bank write bursts
> system.physmem.perBankRdBursts::2 18217 # Per bank write bursts
> system.physmem.perBankRdBursts::3 18185 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18292 # Per bank write bursts
> system.physmem.perBankRdBursts::5 18424 # Per bank write bursts
> system.physmem.perBankRdBursts::6 18179 # Per bank write bursts
60,67c60,67
< system.physmem.perBankRdBursts::8 18034 # Per bank write bursts
< system.physmem.perBankRdBursts::9 18056 # Per bank write bursts
< system.physmem.perBankRdBursts::10 18101 # Per bank write bursts
< system.physmem.perBankRdBursts::11 18200 # Per bank write bursts
< system.physmem.perBankRdBursts::12 18218 # Per bank write bursts
< system.physmem.perBankRdBursts::13 18271 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18258 # Per bank write bursts
---
> system.physmem.perBankRdBursts::8 18031 # Per bank write bursts
> system.physmem.perBankRdBursts::9 18051 # Per bank write bursts
> system.physmem.perBankRdBursts::10 18108 # Per bank write bursts
> system.physmem.perBankRdBursts::11 18204 # Per bank write bursts
> system.physmem.perBankRdBursts::12 18211 # Per bank write bursts
> system.physmem.perBankRdBursts::13 18269 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18079 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
70c70
< system.physmem.perBankWrBursts::2 4135 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 4134 # Per bank write bursts
72c72
< system.physmem.perBankWrBursts::4 4224 # Per bank write bursts
---
> system.physmem.perBankWrBursts::4 4223 # Per bank write bursts
74c74
< system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
---
> system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
76,77c76,77
< system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
< system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
---
> system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
> system.physmem.perBankWrBursts::9 4093 # Per bank write bursts
80,83c80,83
< system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
< system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
< system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
< system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 4095 # Per bank write bursts
> system.physmem.perBankWrBursts::13 4095 # Per bank write bursts
> system.physmem.perBankWrBursts::14 4095 # Per bank write bursts
> system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
86c86
< system.physmem.totGap 525654384500 # Total gap between requests
---
> system.physmem.totGap 525647749500 # Total gap between requests
93c93
< system.physmem.readPktSize::6 291229 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 291235 # Read request sizes (log2)
101,103c101,103
< system.physmem.rdQLenPdf::0 290516 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 290544 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
149,151c149,151
< system.physmem.wrQLenPdf::16 889 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::16 890 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see
158c158
< system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::25 4020 # What write queue length does an incoming req see
160,161c160,161
< system.physmem.wrQLenPdf::27 4019 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 4020 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::27 4021 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 4021 # What write queue length does an incoming req see
163,165c163,165
< system.physmem.wrQLenPdf::30 4022 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4021 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4019 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::30 4023 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see
197,215c197,215
< system.physmem.bytesPerActivate::samples 102767 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 222.307005 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 147.372317 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 261.848294 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 36138 35.16% 35.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 41898 40.77% 75.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 13163 12.81% 88.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1012 0.98% 89.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 489 0.48% 90.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1030 1.00% 91.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 399 0.39% 91.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 484 0.47% 92.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8154 7.93% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 102767 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 48.497387 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 34.151985 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 506.429034 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 4017 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 102644 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 222.570282 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 147.559533 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 262.016403 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 36015 35.09% 35.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 41909 40.83% 75.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13148 12.81% 88.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 1006 0.98% 89.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 491 0.48% 90.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1034 1.01% 91.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 399 0.39% 91.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 481 0.47% 92.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8161 7.95% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 102644 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 48.515182 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 34.167653 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 506.604541 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes
218,229c218,229
< system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.442399 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.422334 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.830212 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3130 77.88% 77.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 889 22.12% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads
< system.physmem.totQLat 15538679500 # Total ticks spent queuing
< system.physmem.totMemAccLat 20992885750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 53417.53 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.442509 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.422441 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.830286 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3129 77.87% 77.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 889 22.13% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads
> system.physmem.totQLat 15528676000 # Total ticks spent queuing
> system.physmem.totMemAccLat 20983501000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1454620000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 53377.09 # Average queueing delay per DRAM burst
231c231
< system.physmem.avgMemAccLat 72167.53 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 72127.09 # Average memory access latency per DRAM burst
233c233
< system.physmem.avgWrBW 8.05 # Average achieved write bandwidth in MiByte/s
---
> system.physmem.avgWrBW 8.04 # Average achieved write bandwidth in MiByte/s
241,268c241,268
< system.physmem.avgWrQLen 19.65 # Average write queue length when enqueuing
< system.physmem.readRowHits 202495 # Number of row buffer hits during reads
< system.physmem.writeRowHits 51707 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 69.61 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes
< system.physmem.avgGap 1471073.79 # Average gap between requests
< system.physmem.pageHitRate 71.21 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 367124520 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 195116130 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1040126640 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 173653740 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 28870255440.000008 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 8266537290 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1634065440 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 57360982710 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 51276223200 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 64953258915 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 214157919585 # Total energy per rank (pJ)
< system.physmem_0.averagePower 407.411950 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 503225172750 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 3206676000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 12282762000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 243901523000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 133531907000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 6939814000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 125791803500 # Time in different power states
< system.physmem_1.actEnergy 366660420 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 194884635 # Energy for precharge commands per rank (pJ)
---
> system.physmem.avgWrQLen 28.92 # Average write queue length when enqueuing
> system.physmem.readRowHits 202546 # Number of row buffer hits during reads
> system.physmem.writeRowHits 51789 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 69.62 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 78.35 # Row buffer hit rate for writes
> system.physmem.avgGap 1471030.52 # Average gap between requests
> system.physmem.pageHitRate 71.24 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 366410520 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 194736630 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1040362260 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 173638080 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 28886236080.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 8300918550 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1634993280 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 57345491820 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 51305938080 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 64928910000 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 214198815120 # Total energy per rank (pJ)
> system.physmem_0.averagePower 407.494892 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 503139346250 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 3209706000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 12289528000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 243772297750 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 133609273250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 7009209500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 125757836000 # Time in different power states
> system.physmem_1.actEnergy 366546180 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 194797350 # Energy for precharge commands per rank (pJ)
270,291c270,291
< system.physmem_1.writeEnergy 171294300 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 28737493200.000008 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 8178131430 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1630074720 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 56926536120 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 51134645280 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 65306601210 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 213703234155 # Total energy per rank (pJ)
< system.physmem_1.averagePower 406.546781 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 503430400500 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 3200172000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 12226116000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 245428473250 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 133163073250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 6797797000 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 124838854000 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 147261657 # Number of BP lookups
< system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 89949365 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 63294627 # Number of BTB hits
---
> system.physmem_1.writeEnergy 171226440 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 28725815040.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 8187694890 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1628706720 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 56919000150 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 51113801760 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 65311053315 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 213675530385 # Total energy per rank (pJ)
> system.physmem_1.averagePower 406.499389 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 503405920500 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 3197022000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 12221338000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 245475081750 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 133108808000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 6823284750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 124822316000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 147257105 # Number of BP lookups
> system.cpu.branchPred.condPredicted 98226689 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1384794 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 89640439 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 63297158 # Number of BTB hits
293,298c293,298
< system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1312 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 15995155 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 15988941 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses.
---
> system.cpu.branchPred.BTBHitPct 70.612280 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 19276056 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1321 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 15995188 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 15989428 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 5760 # Number of indirect misses.
301c301
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
331c331
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
361c361
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
391c391
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
422,423c422,423
< system.cpu.pwrStateResidencyTicks::ON 525654485500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1051308971 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 525647850500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1051295701 # number of cpu cycles simulated
428c428
< system.cpu.discardedOps 8621767 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 8620171 # Number of ops (including micro ops) which were discarded before commit
430,431c430,431
< system.cpu.cpi 1.640991 # CPI: cycles per instruction
< system.cpu.ipc 0.609388 # IPC: instructions per cycle
---
> system.cpu.cpi 1.640970 # CPI: cycles per instruction
> system.cpu.ipc 0.609396 # IPC: instructions per cycle
471,473c471,473
< system.cpu.tickCycles 955911046 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 95397925 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 955914808 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 95380893 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
475,476c475,476
< system.cpu.dcache.tags.tagsinuse 4092.108689 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4092.107040 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 378447440 # Total number of references to valid blocks.
478,480c478,480
< system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 850386500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4092.108689 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.avg_refs 483.826867 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 850680500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4092.107040 # Average occupied blocks per requestor
485,486c485,486
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 970 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id
490,494c490,494
< system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 759379166 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 759379166 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 249618713 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 249618713 # number of ReadReq hits
503,506c503,506
< system.cpu.dcache.demand_hits::cpu.data 378434445 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 378434445 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 378437929 # number of overall hits
< system.cpu.dcache.overall_hits::total 378437929 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 378432478 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 378432478 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 378435962 # number of overall hits
> system.cpu.dcache.overall_hits::total 378435962 # number of overall hits
517,526c517,526
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 37269485500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 37269485500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10946218000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10946218000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 48215703500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 48215703500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 48215703500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 48215703500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 37264745000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 37264745000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10940214000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10940214000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 48204959000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 48204959000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 48204959000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 48204959000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 250331905 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 250331905 # number of ReadReq accesses(hits+misses)
535,538c535,538
< system.cpu.dcache.demand_accesses::cpu.data 379285349 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 379285349 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 379288974 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 379288974 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 379283382 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 379283382 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 379287007 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 379287007 # number of overall (read+write) accesses
549,556c549,556
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 56664.093129 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 56654.705098 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52250.649194 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 52250.649194 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79442.706518 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 79442.706518 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 56651.465970 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 56651.465970 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 56642.080031 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 56642.080031 # average overall miss latency
563,564c563,564
< system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks
< system.cpu.dcache.writebacks::total 88688 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 88684 # number of writebacks
> system.cpu.dcache.writebacks::total 88684 # number of writebacks
583,586c583,586
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36547770500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 36547770500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5489520000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5489520000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36543095500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 36543095500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5486426000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5486426000 # number of WriteReq MSHR miss cycles
589,592c589,592
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42037290500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 42037290500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42039092500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 42039092500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42029521500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 42029521500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42031323500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 42031323500 # number of overall MSHR miss cycles
603,606c603,606
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51271.644440 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51271.644440 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79144.081244 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79144.081244 # average WriteReq mshr miss latency
609,618c609,618
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 24885 # number of replacements
< system.cpu.icache.tags.tagsinuse 1711.889727 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 257789639 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 9678.241440 # Average number of references to valid blocks.
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53742.273901 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53742.273901 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53735.027410 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53735.027410 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 24889 # number of replacements
> system.cpu.icache.tags.tagsinuse 1710.890314 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 257795451 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 26639 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 9677.369684 # Average number of references to valid blocks.
620,654c620,654
< system.cpu.icache.tags.occ_blocks::cpu.inst 1711.889727 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.835884 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.835884 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 515659188 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 515659188 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 257789639 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 257789639 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 257789639 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 257789639 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 257789639 # number of overall hits
< system.cpu.icache.overall_hits::total 257789639 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses
< system.cpu.icache.overall_misses::total 26637 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 539890500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 539890500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 539890500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 539890500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 539890500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 539890500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 257816276 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 257816276 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 257816276 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 257816276 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 257816276 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 257816276 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1710.890314 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.835396 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.835396 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 515670821 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 515670821 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 257795451 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 257795451 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 257795451 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 257795451 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 257795451 # number of overall hits
> system.cpu.icache.overall_hits::total 257795451 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 26640 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 26640 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 26640 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 26640 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 26640 # number of overall misses
> system.cpu.icache.overall_misses::total 26640 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 538801500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 538801500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 538801500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 538801500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 538801500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 538801500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 257822091 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 257822091 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 257822091 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 257822091 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 257822091 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 257822091 # number of overall (read+write) accesses
661,666c661,666
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20268.442392 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20268.442392 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20225.281532 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20225.281532 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20225.281532 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20225.281532 # average overall miss latency
673,686c673,686
< system.cpu.icache.writebacks::writebacks 24885 # number of writebacks
< system.cpu.icache.writebacks::total 24885 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26637 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 26637 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 26637 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 513254500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 513254500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 513254500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 513254500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 513254500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 513254500 # number of overall MSHR miss cycles
---
> system.cpu.icache.writebacks::writebacks 24889 # number of writebacks
> system.cpu.icache.writebacks::total 24889 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26640 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 26640 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 26640 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 26640 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 26640 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 26640 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 512162500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 512162500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 512162500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 512162500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 512162500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 512162500 # number of overall MSHR miss cycles
693,712c693,712
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 258837 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 32651.524409 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 3958369000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 41.514151 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.268254 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.001267 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002724 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.992454 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996445 # Average percentage of cache occupancy
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19225.319069 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19225.319069 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 258839 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 32651.545544 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1316953 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 291607 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.516191 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 3958663000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 40.523746 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.271478 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.750321 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.001237 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002755 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.992455 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996446 # Average percentage of cache occupancy
714,715c714,715
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
718c718
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29221 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29227 # Occupied blocks per task id
720,726c720,726
< system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits
---
> system.cpu.l2cache.tags.tag_accesses 13160335 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 13160335 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 88684 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 88684 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 23557 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 23557 # number of WritebackClean hits
729,730c729,730
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits
---
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24064 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 24064 # number of ReadCleanReq hits
733c733
< system.cpu.l2cache.demand_hits::cpu.inst 24067 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 24064 # number of demand (read+write) hits
735,736c735,736
< system.cpu.l2cache.demand_hits::total 517573 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 24067 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 517570 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 24064 # number of overall hits
738c738
< system.cpu.l2cache.overall_hits::total 517573 # number of overall hits
---
> system.cpu.l2cache.overall_hits::total 517570 # number of overall hits
741,742c741,742
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2570 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 2570 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2576 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 2576 # number of ReadCleanReq misses
745c745
< system.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 2576 # number of demand (read+write) misses
747,748c747,748
< system.cpu.l2cache.demand_misses::total 291260 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 291266 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2576 # number of overall misses
750,766c750,766
< system.cpu.l2cache.overall_misses::total 291260 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5351609000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5351609000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 219318000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 219318000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30330402000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 30330402000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 219318000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 35682011000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 35901329000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 219318000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 35682011000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 35901329000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 291266 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5348515000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5348515000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 218253000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 218253000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30325726000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 30325726000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 218253000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 35674241000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 35892494000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 218253000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 35674241000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 35892494000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 88684 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 88684 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 23557 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 23557 # number of WritebackClean accesses(hits+misses)
769,770c769,770
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26637 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 26637 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26640 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 26640 # number of ReadCleanReq accesses(hits+misses)
773c773
< system.cpu.l2cache.demand_accesses::cpu.inst 26637 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 26640 # number of demand (read+write) accesses
775,776c775,776
< system.cpu.l2cache.demand_accesses::total 808833 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 26637 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 808836 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 26640 # number of overall (read+write) accesses
778c778
< system.cpu.l2cache.overall_accesses::total 808833 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 808836 # number of overall (read+write) accesses
781,782c781,782
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096482 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096482 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096697 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096697 # miss rate for ReadCleanReq accesses
785c785
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096697 # miss rate for demand accesses
787,788c787,788
< system.cpu.l2cache.demand_miss_rate::total 0.360099 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.360105 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096697 # miss rate for overall accesses
790,802c790,802
< system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.360105 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80926.525548 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80926.525548 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.543478 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.543478 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136234.780929 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136234.780929 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 123229.261225 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 123229.261225 # average overall miss latency
823,824c823,824
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2572 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2572 # number of ReadCleanReq MSHR misses
827c827
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses
829,830c829,830
< system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 291236 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses
832,844c832,844
< system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4690699000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4690699000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193386000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193386000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28102659500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28102659500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193386000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32793358500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 32986744500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193386000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32793358500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 32986744500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::total 291236 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4687605000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4687605000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 192261000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 192261000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28098015500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28098015500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192261000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32785620500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 32977881500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192261000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32785620500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 32977881500 # number of overall MSHR miss cycles
847,848c847,848
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096547 # mshr miss rate for ReadCleanReq accesses
851c851
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for demand accesses
853,854c853,854
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.360068 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for overall accesses
856,870c856,870
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.360068 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70926.525548 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70926.525548 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74751.555210 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74751.555210 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126241.797073 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126241.797073 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 1611825 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 803048 # Number of requests hitting in the snoop filter with a single holder of the requested data.
872,873c872,873
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2033 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2018 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
875,879c875,879
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 739513 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 154782 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 24889 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 882157 # Transaction distribution
882c882
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 26640 # Transaction distribution
884c884
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78158 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78168 # Packet count per connected master and slave (bytes)
886,890c886,890
< system.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736576 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 59033920 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 258837 # Total snoops (count)
---
> system.cpu.toL2Bus.pkt_count::total 2420660 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297792 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736320 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 59034112 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 258839 # Total snoops (count)
892,894c892,894
< system.cpu.toL2Bus.snoop_fanout::samples 1067670 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.005005 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.070770 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 1067675 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.005002 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.070750 # Request fanout histogram
896,897c896,897
< system.cpu.toL2Bus.snoop_fanout::0 1062341 99.50% 99.50% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 5314 0.50% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1062349 99.50% 99.50% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 5311 0.50% 100.00% # Request fanout histogram
902,903c902,903
< system.cpu.toL2Bus.snoop_fanout::total 1067670 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 919482000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1067675 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 919485500 # Layer occupancy (ticks)
905c905
< system.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 39960496 # Layer occupancy (ticks)
909,910c909,910
< system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.membus.snoop_filter.tot_requests 548040 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 256844 # Number of requests hitting in the snoop filter with a single holder of the requested data.
915,916c915,916
< system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 225138 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 225144 # Transaction distribution
918c918
< system.membus.trans_dist::CleanEvict 190702 # Transaction distribution
---
> system.membus.trans_dist::CleanEvict 190707 # Transaction distribution
921,925c921,925
< system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868928 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 22868928 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 225144 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839275 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 839275 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22869312 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22869312 # Cumulative packet size per connected master and slave (bytes)
928c928
< system.membus.snoop_fanout::samples 291229 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 291235 # Request fanout histogram
932c932
< system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 291235 100.00% 100.00% # Request fanout histogram
937,938c937,938
< system.membus.snoop_fanout::total 291229 # Request fanout histogram
< system.membus.reqLayer0.occupancy 917205000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 291235 # Request fanout histogram
> system.membus.reqLayer0.occupancy 917214500 # Layer occupancy (ticks)
940c940
< system.membus.respLayer1.occupancy 1553500250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1553534250 # Layer occupancy (ticks)