3,5c3,5
< sim_seconds 0.512877 # Number of seconds simulated
< sim_ticks 512876814500 # Number of ticks simulated
< final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.525654 # Number of seconds simulated
> sim_ticks 525654485500 # Number of ticks simulated
> final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 169706 # Simulator instruction rate (inst/s)
< host_op_rate 208931 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 135858559 # Simulator tick rate (ticks/s)
< host_mem_usage 281524 # Number of bytes of host memory used
< host_seconds 3775.08 # Real time elapsed on the host
---
> host_inst_rate 213828 # Simulator instruction rate (inst/s)
> host_op_rate 263250 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 175444467 # Simulator tick rate (ticks/s)
> host_mem_usage 278324 # Number of bytes of host memory used
> host_seconds 2996.13 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
29,39c29,39
< system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 312296 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 35145702 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 35457999 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 312296 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 312296 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 8047628 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8047628 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8047628 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 312296 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 35145702 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 43505627 # Total bandwidth to/from this memory (bytes/s)
44,46c44,46
< system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM
---
> system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4229248 # Total number of bytes written to DRAM
49c49
< system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue
52,55c52,55
< system.physmem.perBankRdBursts::0 18285 # Per bank write bursts
< system.physmem.perBankRdBursts::1 18130 # Per bank write bursts
< system.physmem.perBankRdBursts::2 18219 # Per bank write bursts
< system.physmem.perBankRdBursts::3 18177 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 18281 # Per bank write bursts
> system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
> system.physmem.perBankRdBursts::2 18221 # Per bank write bursts
> system.physmem.perBankRdBursts::3 18176 # Per bank write bursts
57,67c57,67
< system.physmem.perBankRdBursts::5 18413 # Per bank write bursts
< system.physmem.perBankRdBursts::6 18173 # Per bank write bursts
< system.physmem.perBankRdBursts::7 17985 # Per bank write bursts
< system.physmem.perBankRdBursts::8 18026 # Per bank write bursts
< system.physmem.perBankRdBursts::9 18055 # Per bank write bursts
< system.physmem.perBankRdBursts::10 18102 # Per bank write bursts
< system.physmem.perBankRdBursts::11 18206 # Per bank write bursts
< system.physmem.perBankRdBursts::12 18220 # Per bank write bursts
< system.physmem.perBankRdBursts::13 18274 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18073 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 18412 # Per bank write bursts
> system.physmem.perBankRdBursts::6 18178 # Per bank write bursts
> system.physmem.perBankRdBursts::7 17990 # Per bank write bursts
> system.physmem.perBankRdBursts::8 18034 # Per bank write bursts
> system.physmem.perBankRdBursts::9 18056 # Per bank write bursts
> system.physmem.perBankRdBursts::10 18101 # Per bank write bursts
> system.physmem.perBankRdBursts::11 18200 # Per bank write bursts
> system.physmem.perBankRdBursts::12 18218 # Per bank write bursts
> system.physmem.perBankRdBursts::13 18271 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18258 # Per bank write bursts
69,70c69,70
< system.physmem.perBankWrBursts::1 4098 # Per bank write bursts
< system.physmem.perBankWrBursts::2 4134 # Per bank write bursts
---
> system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
> system.physmem.perBankWrBursts::2 4135 # Per bank write bursts
72c72
< system.physmem.perBankWrBursts::4 4223 # Per bank write bursts
---
> system.physmem.perBankWrBursts::4 4224 # Per bank write bursts
74,76c74,76
< system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
< system.physmem.perBankWrBursts::7 4092 # Per bank write bursts
< system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
---
> system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
> system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
> system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
80c80
< system.physmem.perBankWrBursts::12 4095 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
83c83
< system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
86c86
< system.physmem.totGap 512876719500 # Total gap between requests
---
> system.physmem.totGap 525654384500 # Total gap between requests
101,103c101,103
< system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 290516 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see
148,149c148,149
< system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 889 # What write queue length does an incoming req see
151,165c151,165
< system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 4020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4022 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4021 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4019 # What write queue length does an incoming req see
197,215c197,215
< system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 102767 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 222.307005 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 147.372317 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 261.848294 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 36138 35.16% 35.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 41898 40.77% 75.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13163 12.81% 88.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 1012 0.98% 89.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 489 0.48% 90.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1030 1.00% 91.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 399 0.39% 91.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 484 0.47% 92.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8154 7.93% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 102767 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 48.497387 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 34.151985 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 506.429034 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 4017 99.95% 99.95% # Reads before turning the bus around for writes
218,229c218,229
< system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads
< system.physmem.totQLat 2756382250 # Total ticks spent queuing
< system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.442399 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.422334 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.830212 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3130 77.88% 77.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 889 22.12% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads
> system.physmem.totQLat 15538679500 # Total ticks spent queuing
> system.physmem.totMemAccLat 20992885750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 53417.53 # Average queueing delay per DRAM burst
231,235c231,235
< system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 72167.53 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 8.05 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s
237c237
< system.physmem.busUtil 0.35 # Data bus utilization in percentage
---
> system.physmem.busUtil 0.34 # Data bus utilization in percentage
241,277c241,287
< system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing
< system.physmem.readRowHits 194946 # Number of row buffer hits during reads
< system.physmem.writeRowHits 51576 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes
< system.physmem.avgGap 1435314.77 # Average gap between requests
< system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ)
< system.physmem_0.averagePower 694.111511 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ)
< system.physmem_1.averagePower 694.035798 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 147261658 # Number of BP lookups
---
> system.physmem.avgWrQLen 19.65 # Average write queue length when enqueuing
> system.physmem.readRowHits 202495 # Number of row buffer hits during reads
> system.physmem.writeRowHits 51707 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 69.61 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes
> system.physmem.avgGap 1471073.79 # Average gap between requests
> system.physmem.pageHitRate 71.21 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 367124520 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 195116130 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1040126640 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 173653740 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 28870255440.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 8266537290 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1634065440 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 57360982710 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 51276223200 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 64953258915 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 214157919585 # Total energy per rank (pJ)
> system.physmem_0.averagePower 407.411950 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 503225172750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 3206676000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 12282762000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 243901523000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 133531907000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 6939814000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 125791803500 # Time in different power states
> system.physmem_1.actEnergy 366660420 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 194884635 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 171294300 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 28737493200.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 8178131430 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1630074720 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 56926536120 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 51134645280 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 65306601210 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 213703234155 # Total energy per rank (pJ)
> system.physmem_1.averagePower 406.546781 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 503430400500 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 3200172000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 12226116000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 245428473250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 133163073250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 6797797000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 124838854000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 147261657 # Number of BP lookups
280,281c290,291
< system.cpu.branchPred.BTBLookups 89949366 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 63294628 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 89949365 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 63294627 # Number of BTB hits
291c301
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
321c331
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
351c361
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
381c391
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
412,413c422,423
< system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1025753629 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 525654485500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1051308971 # number of cpu cycles simulated
418c428
< system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 8621767 # Number of ops (including micro ops) which were discarded before commit
420,421c430,431
< system.cpu.cpi 1.601101 # CPI: cycles per instruction
< system.cpu.ipc 0.624570 # IPC: instructions per cycle
---
> system.cpu.cpi 1.640991 # CPI: cycles per instruction
> system.cpu.ipc 0.609388 # IPC: instructions per cycle
457,459c467,469
< system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 955911046 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 95397925 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
461c471
< system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4092.108689 # Cycle average of tags in use
465,468c475,478
< system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 850386500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4092.108689 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy
471,474c481,484
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 970 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id
478c488
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
503,510c513,520
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 37269485500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 37269485500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10946218000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10946218000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 48215703500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 48215703500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 48215703500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 48215703500 # number of overall miss cycles
535,542c545,552
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 56664.093129 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 56654.705098 # average overall miss latency
569,578c579,588
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36547770500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 36547770500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5489520000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5489520000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42037290500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 42037290500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42039092500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 42039092500 # number of overall MSHR miss cycles
589,599c599,609
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
601,602c611,612
< system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1711.889727 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 257789639 # Total number of references to valid blocks.
604c614
< system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 9678.241440 # Average number of references to valid blocks.
606,608c616,618
< system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1711.889727 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.835884 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.835884 # Average percentage of cache occupancy
614,622c624,632
< system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits
< system.cpu.icache.overall_hits::total 257789646 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 515659188 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 515659188 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 257789639 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 257789639 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 257789639 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 257789639 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 257789639 # number of overall hits
> system.cpu.icache.overall_hits::total 257789639 # number of overall hits
629,640c639,650
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 518689000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 518689000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 518689000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 518689000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 518689000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 518689000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 257816283 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 539890500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 539890500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 539890500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 539890500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 539890500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 539890500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 257816276 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 257816276 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 257816276 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 257816276 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 257816276 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 257816276 # number of overall (read+write) accesses
647,652c657,662
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20268.442392 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20268.442392 # average overall miss latency
667,672c677,682
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 513254500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 513254500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 513254500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 513254500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 513254500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 513254500 # number of overall MSHR miss cycles
679,685c689,695
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
687c697
< system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 32651.524409 # Cycle average of tags in use
691,698c701,708
< system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.warmup_cycle 3958369000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 41.514151 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.268254 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.001267 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002724 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.992454 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996445 # Average percentage of cache occupancy
702,704c712,714
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29221 # Occupied blocks per task id
708c718
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
737,748c747,758
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5351609000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5351609000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 219318000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 219318000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30330402000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 30330402000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 219318000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 35682011000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 35901329000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 219318000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 35682011000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 35901329000 # number of overall miss cycles
777,788c787,798
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489 # average overall miss latency
819,830c829,840
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4690699000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4690699000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193386000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193386000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28102659500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28102659500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193386000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32793358500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 32986744500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193386000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32793358500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 32986744500 # number of overall MSHR miss cycles
843,854c853,864
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency
861c871
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
901c911
< system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
924c934
< system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 917205000 # Layer occupancy (ticks)
926c936
< system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1553500250 # Layer occupancy (ticks)
< sim_seconds 0.512877 # Number of seconds simulated
< sim_ticks 512876814500 # Number of ticks simulated
< final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.525654 # Number of seconds simulated
> sim_ticks 525654485500 # Number of ticks simulated
> final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 169706 # Simulator instruction rate (inst/s)
< host_op_rate 208931 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 135858559 # Simulator tick rate (ticks/s)
< host_mem_usage 281524 # Number of bytes of host memory used
< host_seconds 3775.08 # Real time elapsed on the host
---
> host_inst_rate 213828 # Simulator instruction rate (inst/s)
> host_op_rate 263250 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 175444467 # Simulator tick rate (ticks/s)
> host_mem_usage 278324 # Number of bytes of host memory used
> host_seconds 2996.13 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
29,39c29,39
< system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 312296 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 35145702 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 35457999 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 312296 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 312296 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 8047628 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8047628 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8047628 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 312296 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 35145702 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 43505627 # Total bandwidth to/from this memory (bytes/s)
44,46c44,46
< system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM
---
> system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4229248 # Total number of bytes written to DRAM
49c49
< system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue
52,55c52,55
< system.physmem.perBankRdBursts::0 18285 # Per bank write bursts
< system.physmem.perBankRdBursts::1 18130 # Per bank write bursts
< system.physmem.perBankRdBursts::2 18219 # Per bank write bursts
< system.physmem.perBankRdBursts::3 18177 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 18281 # Per bank write bursts
> system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
> system.physmem.perBankRdBursts::2 18221 # Per bank write bursts
> system.physmem.perBankRdBursts::3 18176 # Per bank write bursts
57,67c57,67
< system.physmem.perBankRdBursts::5 18413 # Per bank write bursts
< system.physmem.perBankRdBursts::6 18173 # Per bank write bursts
< system.physmem.perBankRdBursts::7 17985 # Per bank write bursts
< system.physmem.perBankRdBursts::8 18026 # Per bank write bursts
< system.physmem.perBankRdBursts::9 18055 # Per bank write bursts
< system.physmem.perBankRdBursts::10 18102 # Per bank write bursts
< system.physmem.perBankRdBursts::11 18206 # Per bank write bursts
< system.physmem.perBankRdBursts::12 18220 # Per bank write bursts
< system.physmem.perBankRdBursts::13 18274 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18073 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 18412 # Per bank write bursts
> system.physmem.perBankRdBursts::6 18178 # Per bank write bursts
> system.physmem.perBankRdBursts::7 17990 # Per bank write bursts
> system.physmem.perBankRdBursts::8 18034 # Per bank write bursts
> system.physmem.perBankRdBursts::9 18056 # Per bank write bursts
> system.physmem.perBankRdBursts::10 18101 # Per bank write bursts
> system.physmem.perBankRdBursts::11 18200 # Per bank write bursts
> system.physmem.perBankRdBursts::12 18218 # Per bank write bursts
> system.physmem.perBankRdBursts::13 18271 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18258 # Per bank write bursts
69,70c69,70
< system.physmem.perBankWrBursts::1 4098 # Per bank write bursts
< system.physmem.perBankWrBursts::2 4134 # Per bank write bursts
---
> system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
> system.physmem.perBankWrBursts::2 4135 # Per bank write bursts
72c72
< system.physmem.perBankWrBursts::4 4223 # Per bank write bursts
---
> system.physmem.perBankWrBursts::4 4224 # Per bank write bursts
74,76c74,76
< system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
< system.physmem.perBankWrBursts::7 4092 # Per bank write bursts
< system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
---
> system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
> system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
> system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
80c80
< system.physmem.perBankWrBursts::12 4095 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
83c83
< system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
86c86
< system.physmem.totGap 512876719500 # Total gap between requests
---
> system.physmem.totGap 525654384500 # Total gap between requests
101,103c101,103
< system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 290516 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see
148,149c148,149
< system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 889 # What write queue length does an incoming req see
151,165c151,165
< system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 4019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 4020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4022 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4021 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4019 # What write queue length does an incoming req see
197,215c197,215
< system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 102767 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 222.307005 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 147.372317 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 261.848294 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 36138 35.16% 35.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 41898 40.77% 75.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13163 12.81% 88.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 1012 0.98% 89.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 489 0.48% 90.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1030 1.00% 91.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 399 0.39% 91.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 484 0.47% 92.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8154 7.93% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 102767 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 48.497387 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 34.151985 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 506.429034 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 4017 99.95% 99.95% # Reads before turning the bus around for writes
218,229c218,229
< system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads
< system.physmem.totQLat 2756382250 # Total ticks spent queuing
< system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.442399 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.422334 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.830212 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3130 77.88% 77.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 889 22.12% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads
> system.physmem.totQLat 15538679500 # Total ticks spent queuing
> system.physmem.totMemAccLat 20992885750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 53417.53 # Average queueing delay per DRAM burst
231,235c231,235
< system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 72167.53 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 8.05 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s
237c237
< system.physmem.busUtil 0.35 # Data bus utilization in percentage
---
> system.physmem.busUtil 0.34 # Data bus utilization in percentage
241,277c241,287
< system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing
< system.physmem.readRowHits 194946 # Number of row buffer hits during reads
< system.physmem.writeRowHits 51576 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes
< system.physmem.avgGap 1435314.77 # Average gap between requests
< system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ)
< system.physmem_0.averagePower 694.111511 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ)
< system.physmem_1.averagePower 694.035798 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 147261658 # Number of BP lookups
---
> system.physmem.avgWrQLen 19.65 # Average write queue length when enqueuing
> system.physmem.readRowHits 202495 # Number of row buffer hits during reads
> system.physmem.writeRowHits 51707 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 69.61 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes
> system.physmem.avgGap 1471073.79 # Average gap between requests
> system.physmem.pageHitRate 71.21 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 367124520 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 195116130 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1040126640 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 173653740 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 28870255440.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 8266537290 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1634065440 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 57360982710 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 51276223200 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 64953258915 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 214157919585 # Total energy per rank (pJ)
> system.physmem_0.averagePower 407.411950 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 503225172750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 3206676000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 12282762000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 243901523000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 133531907000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 6939814000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 125791803500 # Time in different power states
> system.physmem_1.actEnergy 366660420 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 194884635 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 171294300 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 28737493200.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 8178131430 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1630074720 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 56926536120 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 51134645280 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 65306601210 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 213703234155 # Total energy per rank (pJ)
> system.physmem_1.averagePower 406.546781 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 503430400500 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 3200172000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 12226116000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 245428473250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 133163073250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 6797797000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 124838854000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 147261657 # Number of BP lookups
280,281c290,291
< system.cpu.branchPred.BTBLookups 89949366 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 63294628 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 89949365 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 63294627 # Number of BTB hits
291c301
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
321c331
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
351c361
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
381c391
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
412,413c422,423
< system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1025753629 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 525654485500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1051308971 # number of cpu cycles simulated
418c428
< system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 8621767 # Number of ops (including micro ops) which were discarded before commit
420,421c430,431
< system.cpu.cpi 1.601101 # CPI: cycles per instruction
< system.cpu.ipc 0.624570 # IPC: instructions per cycle
---
> system.cpu.cpi 1.640991 # CPI: cycles per instruction
> system.cpu.ipc 0.609388 # IPC: instructions per cycle
457,459c467,469
< system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 955911046 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 95397925 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
461c471
< system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4092.108689 # Cycle average of tags in use
465,468c475,478
< system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 850386500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4092.108689 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy
471,474c481,484
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 970 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id
478c488
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
503,510c513,520
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 37269485500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 37269485500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10946218000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10946218000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 48215703500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 48215703500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 48215703500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 48215703500 # number of overall miss cycles
535,542c545,552
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 56664.093129 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 56654.705098 # average overall miss latency
569,578c579,588
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36547770500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 36547770500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5489520000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5489520000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42037290500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 42037290500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42039092500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 42039092500 # number of overall MSHR miss cycles
589,599c599,609
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
601,602c611,612
< system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1711.889727 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 257789639 # Total number of references to valid blocks.
604c614
< system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 9678.241440 # Average number of references to valid blocks.
606,608c616,618
< system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1711.889727 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.835884 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.835884 # Average percentage of cache occupancy
614,622c624,632
< system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits
< system.cpu.icache.overall_hits::total 257789646 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 515659188 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 515659188 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 257789639 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 257789639 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 257789639 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 257789639 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 257789639 # number of overall hits
> system.cpu.icache.overall_hits::total 257789639 # number of overall hits
629,640c639,650
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 518689000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 518689000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 518689000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 518689000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 518689000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 518689000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 257816283 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 539890500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 539890500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 539890500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 539890500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 539890500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 539890500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 257816276 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 257816276 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 257816276 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 257816276 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 257816276 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 257816276 # number of overall (read+write) accesses
647,652c657,662
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20268.442392 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20268.442392 # average overall miss latency
667,672c677,682
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 513254500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 513254500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 513254500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 513254500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 513254500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 513254500 # number of overall MSHR miss cycles
679,685c689,695
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
687c697
< system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 32651.524409 # Cycle average of tags in use
691,698c701,708
< system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.warmup_cycle 3958369000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 41.514151 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.268254 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.001267 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002724 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.992454 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996445 # Average percentage of cache occupancy
702,704c712,714
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29221 # Occupied blocks per task id
708c718
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
737,748c747,758
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5351609000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5351609000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 219318000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 219318000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30330402000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 30330402000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 219318000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 35682011000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 35901329000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 219318000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 35682011000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 35901329000 # number of overall miss cycles
777,788c787,798
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489 # average overall miss latency
819,830c829,840
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4690699000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4690699000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193386000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193386000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28102659500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28102659500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193386000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32793358500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 32986744500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193386000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32793358500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 32986744500 # number of overall MSHR miss cycles
843,854c853,864
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency
861c871
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
901c911
< system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
924c934
< system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 917205000 # Layer occupancy (ticks)
926c936
< system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1553500250 # Layer occupancy (ticks)