3,5c3,5
< sim_seconds 0.512589 # Number of seconds simulated
< sim_ticks 512588680500 # Number of ticks simulated
< final_tick 512588680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.512877 # Number of seconds simulated
> sim_ticks 512876814500 # Number of ticks simulated
> final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 180394 # Simulator instruction rate (inst/s)
< host_op_rate 222088 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 144333179 # Simulator tick rate (ticks/s)
< host_mem_usage 275860 # Number of bytes of host memory used
< host_seconds 3551.43 # Real time elapsed on the host
---
> host_inst_rate 169706 # Simulator instruction rate (inst/s)
> host_op_rate 208931 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 135858559 # Simulator tick rate (ticks/s)
> host_mem_usage 281524 # Number of bytes of host memory used
> host_seconds 3775.08 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 18474048 # Number of bytes read from this memory
< system.physmem.bytes_read::total 18638208 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory
> system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory
25,26c25,26
< system.physmem.num_reads::cpu.data 288657 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 291222 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory
29,40c29,40
< system.physmem.bw_read::cpu.inst 320257 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 36040687 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 36360943 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 320257 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 320257 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 8252761 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8252761 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8252761 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 320257 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 36040687 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 44613705 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 291222 # Number of read requests accepted
---
> system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 291229 # Number of read requests accepted
42c42
< system.physmem.readBursts 291222 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue
44,47c44,47
< system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 18638208 # Total read bytes from the system interface side
---
> system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side
49c49
< system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue
52,67c52,67
< system.physmem.perBankRdBursts::0 18288 # Per bank write bursts
< system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
< system.physmem.perBankRdBursts::2 18220 # Per bank write bursts
< system.physmem.perBankRdBursts::3 18178 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18281 # Per bank write bursts
< system.physmem.perBankRdBursts::5 18410 # Per bank write bursts
< system.physmem.perBankRdBursts::6 18174 # Per bank write bursts
< system.physmem.perBankRdBursts::7 17993 # Per bank write bursts
< system.physmem.perBankRdBursts::8 18029 # Per bank write bursts
< system.physmem.perBankRdBursts::9 18057 # Per bank write bursts
< system.physmem.perBankRdBursts::10 18103 # Per bank write bursts
< system.physmem.perBankRdBursts::11 18205 # Per bank write bursts
< system.physmem.perBankRdBursts::12 18223 # Per bank write bursts
< system.physmem.perBankRdBursts::13 18272 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18257 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 18285 # Per bank write bursts
> system.physmem.perBankRdBursts::1 18130 # Per bank write bursts
> system.physmem.perBankRdBursts::2 18219 # Per bank write bursts
> system.physmem.perBankRdBursts::3 18177 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18285 # Per bank write bursts
> system.physmem.perBankRdBursts::5 18413 # Per bank write bursts
> system.physmem.perBankRdBursts::6 18173 # Per bank write bursts
> system.physmem.perBankRdBursts::7 17985 # Per bank write bursts
> system.physmem.perBankRdBursts::8 18026 # Per bank write bursts
> system.physmem.perBankRdBursts::9 18055 # Per bank write bursts
> system.physmem.perBankRdBursts::10 18102 # Per bank write bursts
> system.physmem.perBankRdBursts::11 18206 # Per bank write bursts
> system.physmem.perBankRdBursts::12 18220 # Per bank write bursts
> system.physmem.perBankRdBursts::13 18274 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18073 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
69,70c69,70
< system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
< system.physmem.perBankWrBursts::2 4135 # Per bank write bursts
---
> system.physmem.perBankWrBursts::1 4098 # Per bank write bursts
> system.physmem.perBankWrBursts::2 4134 # Per bank write bursts
73c73
< system.physmem.perBankWrBursts::5 4222 # Per bank write bursts
---
> system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
75,76c75,76
< system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
< system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 4092 # Per bank write bursts
> system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
80c80
< system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 4095 # Per bank write bursts
86c86
< system.physmem.totGap 512588586500 # Total gap between requests
---
> system.physmem.totGap 512876719500 # Total gap between requests
93c93
< system.physmem.readPktSize::6 291222 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 291229 # Read request sizes (log2)
101c101
< system.physmem.rdQLenPdf::0 290535 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see
148,154c148,154
< system.physmem.wrQLenPdf::15 910 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 910 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4017 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see
157c157
< system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see
159c159
< system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see
161,165c161,165
< system.physmem.wrQLenPdf::28 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see
197,215c197,215
< system.physmem.bytesPerActivate::samples 110334 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 207.049577 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 134.865332 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 256.872236 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 45104 40.88% 40.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 43590 39.51% 80.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 9238 8.37% 88.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1655 1.50% 90.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 896 0.81% 91.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 605 0.55% 91.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 780 0.71% 92.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 416 0.38% 92.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8050 7.30% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 110334 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4016 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 48.533367 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 34.247557 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 506.662918 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 4014 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes
218,230c218,229
< system.physmem.rdPerTurnAround::total 4016 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4016 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.453187 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.432732 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.838251 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3107 77.37% 77.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 907 22.58% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4016 # Writes before turning the bus around for reads
< system.physmem.totQLat 2758807250 # Total ticks spent queuing
< system.physmem.totMemAccLat 8213182250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9483.70 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads
> system.physmem.totQLat 2756382250 # Total ticks spent queuing
> system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst
232,235c231,234
< system.physmem.avgMemAccLat 28233.70 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 36.32 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 8.25 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 36.36 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s
242,259c241,258
< system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing
< system.physmem.readRowHits 195021 # Number of row buffer hits during reads
< system.physmem.writeRowHits 51610 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 67.04 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.08 # Row buffer hit rate for writes
< system.physmem.avgGap 1434536.51 # Average gap between requests
< system.physmem.pageHitRate 69.08 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 417312000 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 227700000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1136202600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 215544240 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 103911193800 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 216400632000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 355788106560 # Total energy per rank (pJ)
< system.physmem_0.averagePower 694.106023 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 359300376000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 17116320000 # Time in different power states
---
> system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing
> system.physmem.readRowHits 194946 # Number of row buffer hits during reads
> system.physmem.writeRowHits 51576 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes
> system.physmem.avgGap 1435314.77 # Average gap between requests
> system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ)
> system.physmem_0.averagePower 694.111511 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states
261c260
< system.physmem_0.memoryStateTime::ACT 136167987750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states
263,273c262,272
< system.physmem_1.actEnergy 416737440 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 227386500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1132435200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 103626578835 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 216650294250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 355745582385 # Total energy per rank (pJ)
< system.physmem_1.averagePower 694.023062 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 359717078250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 17116320000 # Time in different power states
---
> system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ)
> system.physmem_1.averagePower 694.035798 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states
275c274
< system.physmem_1.memoryStateTime::ACT 135751825750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states
277c276
< system.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
292c291
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
322c321
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
352c351
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
382c381
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
413,414c412,413
< system.cpu.pwrStateResidencyTicks::ON 512588680500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1025177361 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1025753629 # number of cpu cycles simulated
421,422c420,421
< system.cpu.cpi 1.600202 # CPI: cycles per instruction
< system.cpu.ipc 0.624921 # IPC: instructions per cycle
---
> system.cpu.cpi 1.601101 # CPI: cycles per instruction
> system.cpu.ipc 0.624570 # IPC: instructions per cycle
458,460c457,459
< system.cpu.tickCycles 955908039 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 69269322 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
462c461
< system.cpu.dcache.tags.tagsinuse 4092.241926 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use
466,469c465,468
< system.cpu.dcache.tags.warmup_cycle 798177500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4092.241926 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999083 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999083 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy
472c471
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
474c473
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 1420 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id
479c478
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
504,511c503,510
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 24628452500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 24628452500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10137526000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10137526000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34765978500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34765978500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34765978500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34765978500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles
536,543c535,542
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34532.709986 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34532.709986 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73613.962472 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73613.962472 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 40857.697813 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 40857.697813 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 40850.928564 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 40850.928564 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency
550,551c549,550
< system.cpu.dcache.writebacks::writebacks 88716 # number of writebacks
< system.cpu.dcache.writebacks::total 88716 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks
> system.cpu.dcache.writebacks::total 88688 # number of writebacks
570,579c569,578
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23907337500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 23907337500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084282000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084282000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28991619500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 28991619500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993407500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 28993407500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles
590,600c589,599
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33543.094558 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33543.094558 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73342.979141 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73342.979141 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37070.980120 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 37070.980120 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37066.678301 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 37066.678301 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
602,603c601,602
< system.cpu.icache.tags.tagsinuse 1711.979735 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 257789647 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks.
605c604
< system.cpu.icache.tags.avg_refs 9678.241741 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks.
607,609c606,608
< system.cpu.icache.tags.occ_blocks::cpu.inst 1711.979735 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.835928 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.835928 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy
615,623c614,622
< system.cpu.icache.tags.tag_accesses 515659204 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 515659204 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 257789647 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 257789647 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 257789647 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 257789647 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 257789647 # number of overall hits
< system.cpu.icache.overall_hits::total 257789647 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits
> system.cpu.icache.overall_hits::total 257789646 # number of overall hits
630,641c629,640
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 515552500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 515552500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 515552500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 515552500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 515552500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 515552500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 257816284 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 257816284 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 257816284 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 257816284 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 257816284 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 257816284 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 518689000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 518689000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 518689000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 518689000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 518689000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 518689000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 257816283 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses
648,653c647,652
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19354.750910 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19354.750910 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19354.750910 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19354.750910 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency
668,673c667,672
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 488916500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 488916500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 488916500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 488916500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 488916500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 488916500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles
680,700c679,699
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18354.788452 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18354.788452 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 258816 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 32567.443571 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1247529 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 291562 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.278778 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 2619.708679 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.014636 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 29858.720256 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.079947 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002717 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.911216 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 32746 # Occupied blocks per task id
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 258837 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
702c701
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id
704,711c703,710
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29128 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999329 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 13229556 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 13229556 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 88716 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 88716 # number of WritebackDirty hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits
718,719c717,718
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490282 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 490282 # number of ReadSharedReq hits
---
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490275 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 490275 # number of ReadSharedReq hits
721,722c720,721
< system.cpu.l2cache.demand_hits::cpu.data 493513 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 517580 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 493506 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 517573 # number of demand (read+write) hits
724,725c723,724
< system.cpu.l2cache.overall_hits::cpu.data 493513 # number of overall hits
< system.cpu.l2cache.overall_hits::total 517580 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 493506 # number of overall hits
> system.cpu.l2cache.overall_hits::total 517573 # number of overall hits
730,731c729,730
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222592 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 222592 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses
733,734c732,733
< system.cpu.l2cache.demand_misses::cpu.data 288683 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 291253 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 291260 # number of demand (read+write) misses
736,751c735,750
< system.cpu.l2cache.overall_misses::cpu.data 288683 # number of overall misses
< system.cpu.l2cache.overall_misses::total 291253 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4946370000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4946370000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194980000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 194980000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17689881000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 17689881000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 194980000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 22636251000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 22831231000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 194980000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 22636251000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 22831231000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 88716 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 88716 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses
> system.cpu.l2cache.overall_misses::total 291260 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses)
770,771c769,770
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312246 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312246 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses
773,774c772,773
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.369067 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.360090 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.360099 # miss rate for demand accesses
776,789c775,788
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.369067 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.360090 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74841.809021 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74841.809021 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.704280 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.704280 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79472.222721 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79472.222721 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78389.685256 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78389.685256 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency
812,813c811,812
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222566 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222566 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses
815,816c814,815
< system.cpu.l2cache.demand_mshr_misses::cpu.data 288657 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 291223 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses
818,831c817,830
< system.cpu.l2cache.overall_mshr_misses::cpu.data 288657 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 291223 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285460000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285460000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169076000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169076000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15462440500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15462440500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169076000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19747900500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 19916976500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169076000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19747900500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 19916976500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles
836,837c835,836
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312209 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312209 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses
839,840c838,839
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.360053 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses
842,855c841,854
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.360053 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64841.809021 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64841.809021 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65890.880748 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65890.880748 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69473.506735 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69473.506735 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency
859,860c858,859
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
862c861
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
864c863
< system.cpu.toL2Bus.trans_dist::WritebackDirty 154814 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution
866c865
< system.cpu.toL2Bus.trans_dist::CleanEvict 882102 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution
875,877c874,876
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55738368 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 59035712 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 258816 # Total snoops (count)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736576 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 59033920 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 258837 # Total snoops (count)
879,881c878,880
< system.cpu.toL2Bus.snoop_fanout::samples 1067649 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.004997 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.070711 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 1067670 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.005005 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.070770 # Request fanout histogram
883,884c882,883
< system.cpu.toL2Bus.snoop_fanout::0 1062329 99.50% 99.50% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 5305 0.50% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1062341 99.50% 99.50% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 5314 0.50% 100.00% # Request fanout histogram
889,890c888,889
< system.cpu.toL2Bus.snoop_fanout::total 1067649 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 919510000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1067670 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 919482000 # Layer occupancy (ticks)
896,897c895,902
< system.membus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 225131 # Transaction distribution
---
> system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 225138 # Transaction distribution
899c904
< system.membus.trans_dist::CleanEvict 190690 # Transaction distribution
---
> system.membus.trans_dist::CleanEvict 190702 # Transaction distribution
902,906c907,911
< system.membus.trans_dist::ReadSharedReq 225131 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839232 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 839232 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868480 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 22868480 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868928 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22868928 # Cumulative packet size per connected master and slave (bytes)
909c914
< system.membus.snoop_fanout::samples 548010 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 291229 # Request fanout histogram
913c918
< system.membus.snoop_fanout::0 548010 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram
918,919c923,924
< system.membus.snoop_fanout::total 548010 # Request fanout histogram
< system.membus.reqLayer0.occupancy 917220500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 291229 # Request fanout histogram
> system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks)
921c926
< system.membus.respLayer1.occupancy 1554785500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks)
< sim_seconds 0.512589 # Number of seconds simulated
< sim_ticks 512588680500 # Number of ticks simulated
< final_tick 512588680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.512877 # Number of seconds simulated
> sim_ticks 512876814500 # Number of ticks simulated
> final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 180394 # Simulator instruction rate (inst/s)
< host_op_rate 222088 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 144333179 # Simulator tick rate (ticks/s)
< host_mem_usage 275860 # Number of bytes of host memory used
< host_seconds 3551.43 # Real time elapsed on the host
---
> host_inst_rate 169706 # Simulator instruction rate (inst/s)
> host_op_rate 208931 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 135858559 # Simulator tick rate (ticks/s)
> host_mem_usage 281524 # Number of bytes of host memory used
> host_seconds 3775.08 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 18474048 # Number of bytes read from this memory
< system.physmem.bytes_read::total 18638208 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory
> system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory
25,26c25,26
< system.physmem.num_reads::cpu.data 288657 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 291222 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory
29,40c29,40
< system.physmem.bw_read::cpu.inst 320257 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 36040687 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 36360943 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 320257 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 320257 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 8252761 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 8252761 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 8252761 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 320257 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 36040687 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 44613705 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 291222 # Number of read requests accepted
---
> system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 291229 # Number of read requests accepted
42c42
< system.physmem.readBursts 291222 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue
44,47c44,47
< system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 18638208 # Total read bytes from the system interface side
---
> system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side
49c49
< system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue
52,67c52,67
< system.physmem.perBankRdBursts::0 18288 # Per bank write bursts
< system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
< system.physmem.perBankRdBursts::2 18220 # Per bank write bursts
< system.physmem.perBankRdBursts::3 18178 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18281 # Per bank write bursts
< system.physmem.perBankRdBursts::5 18410 # Per bank write bursts
< system.physmem.perBankRdBursts::6 18174 # Per bank write bursts
< system.physmem.perBankRdBursts::7 17993 # Per bank write bursts
< system.physmem.perBankRdBursts::8 18029 # Per bank write bursts
< system.physmem.perBankRdBursts::9 18057 # Per bank write bursts
< system.physmem.perBankRdBursts::10 18103 # Per bank write bursts
< system.physmem.perBankRdBursts::11 18205 # Per bank write bursts
< system.physmem.perBankRdBursts::12 18223 # Per bank write bursts
< system.physmem.perBankRdBursts::13 18272 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18257 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 18285 # Per bank write bursts
> system.physmem.perBankRdBursts::1 18130 # Per bank write bursts
> system.physmem.perBankRdBursts::2 18219 # Per bank write bursts
> system.physmem.perBankRdBursts::3 18177 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18285 # Per bank write bursts
> system.physmem.perBankRdBursts::5 18413 # Per bank write bursts
> system.physmem.perBankRdBursts::6 18173 # Per bank write bursts
> system.physmem.perBankRdBursts::7 17985 # Per bank write bursts
> system.physmem.perBankRdBursts::8 18026 # Per bank write bursts
> system.physmem.perBankRdBursts::9 18055 # Per bank write bursts
> system.physmem.perBankRdBursts::10 18102 # Per bank write bursts
> system.physmem.perBankRdBursts::11 18206 # Per bank write bursts
> system.physmem.perBankRdBursts::12 18220 # Per bank write bursts
> system.physmem.perBankRdBursts::13 18274 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18073 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
69,70c69,70
< system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
< system.physmem.perBankWrBursts::2 4135 # Per bank write bursts
---
> system.physmem.perBankWrBursts::1 4098 # Per bank write bursts
> system.physmem.perBankWrBursts::2 4134 # Per bank write bursts
73c73
< system.physmem.perBankWrBursts::5 4222 # Per bank write bursts
---
> system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
75,76c75,76
< system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
< system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 4092 # Per bank write bursts
> system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
80c80
< system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 4095 # Per bank write bursts
86c86
< system.physmem.totGap 512588586500 # Total gap between requests
---
> system.physmem.totGap 512876719500 # Total gap between requests
93c93
< system.physmem.readPktSize::6 291222 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 291229 # Read request sizes (log2)
101c101
< system.physmem.rdQLenPdf::0 290535 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see
148,154c148,154
< system.physmem.wrQLenPdf::15 910 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 910 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4017 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see
157c157
< system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see
159c159
< system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see
161,165c161,165
< system.physmem.wrQLenPdf::28 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see
197,215c197,215
< system.physmem.bytesPerActivate::samples 110334 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 207.049577 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 134.865332 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 256.872236 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 45104 40.88% 40.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 43590 39.51% 80.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 9238 8.37% 88.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1655 1.50% 90.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 896 0.81% 91.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 605 0.55% 91.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 780 0.71% 92.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 416 0.38% 92.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8050 7.30% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 110334 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4016 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 48.533367 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 34.247557 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 506.662918 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 4014 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes
218,230c218,229
< system.physmem.rdPerTurnAround::total 4016 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4016 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.453187 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.432732 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.838251 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3107 77.37% 77.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 907 22.58% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4016 # Writes before turning the bus around for reads
< system.physmem.totQLat 2758807250 # Total ticks spent queuing
< system.physmem.totMemAccLat 8213182250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9483.70 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads
> system.physmem.totQLat 2756382250 # Total ticks spent queuing
> system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst
232,235c231,234
< system.physmem.avgMemAccLat 28233.70 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 36.32 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 8.25 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 36.36 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s
242,259c241,258
< system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing
< system.physmem.readRowHits 195021 # Number of row buffer hits during reads
< system.physmem.writeRowHits 51610 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 67.04 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.08 # Row buffer hit rate for writes
< system.physmem.avgGap 1434536.51 # Average gap between requests
< system.physmem.pageHitRate 69.08 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 417312000 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 227700000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1136202600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 215544240 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 103911193800 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 216400632000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 355788106560 # Total energy per rank (pJ)
< system.physmem_0.averagePower 694.106023 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 359300376000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 17116320000 # Time in different power states
---
> system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing
> system.physmem.readRowHits 194946 # Number of row buffer hits during reads
> system.physmem.writeRowHits 51576 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes
> system.physmem.avgGap 1435314.77 # Average gap between requests
> system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ)
> system.physmem_0.averagePower 694.111511 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states
261c260
< system.physmem_0.memoryStateTime::ACT 136167987750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states
263,273c262,272
< system.physmem_1.actEnergy 416737440 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 227386500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1132435200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 103626578835 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 216650294250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 355745582385 # Total energy per rank (pJ)
< system.physmem_1.averagePower 694.023062 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 359717078250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 17116320000 # Time in different power states
---
> system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ)
> system.physmem_1.averagePower 694.035798 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states
275c274
< system.physmem_1.memoryStateTime::ACT 135751825750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states
277c276
< system.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
292c291
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
322c321
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
352c351
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
382c381
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
413,414c412,413
< system.cpu.pwrStateResidencyTicks::ON 512588680500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1025177361 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1025753629 # number of cpu cycles simulated
421,422c420,421
< system.cpu.cpi 1.600202 # CPI: cycles per instruction
< system.cpu.ipc 0.624921 # IPC: instructions per cycle
---
> system.cpu.cpi 1.601101 # CPI: cycles per instruction
> system.cpu.ipc 0.624570 # IPC: instructions per cycle
458,460c457,459
< system.cpu.tickCycles 955908039 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 69269322 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
462c461
< system.cpu.dcache.tags.tagsinuse 4092.241926 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use
466,469c465,468
< system.cpu.dcache.tags.warmup_cycle 798177500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4092.241926 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999083 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999083 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy
472c471
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
474c473
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 1420 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id
479c478
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
504,511c503,510
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 24628452500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 24628452500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10137526000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10137526000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34765978500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34765978500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34765978500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34765978500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles
536,543c535,542
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34532.709986 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34532.709986 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73613.962472 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73613.962472 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 40857.697813 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 40857.697813 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 40850.928564 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 40850.928564 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency
550,551c549,550
< system.cpu.dcache.writebacks::writebacks 88716 # number of writebacks
< system.cpu.dcache.writebacks::total 88716 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks
> system.cpu.dcache.writebacks::total 88688 # number of writebacks
570,579c569,578
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23907337500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 23907337500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084282000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084282000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28991619500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 28991619500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993407500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 28993407500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles
590,600c589,599
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33543.094558 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33543.094558 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73342.979141 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73342.979141 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37070.980120 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 37070.980120 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37066.678301 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 37066.678301 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
602,603c601,602
< system.cpu.icache.tags.tagsinuse 1711.979735 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 257789647 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks.
605c604
< system.cpu.icache.tags.avg_refs 9678.241741 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks.
607,609c606,608
< system.cpu.icache.tags.occ_blocks::cpu.inst 1711.979735 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.835928 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.835928 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy
615,623c614,622
< system.cpu.icache.tags.tag_accesses 515659204 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 515659204 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 257789647 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 257789647 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 257789647 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 257789647 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 257789647 # number of overall hits
< system.cpu.icache.overall_hits::total 257789647 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits
> system.cpu.icache.overall_hits::total 257789646 # number of overall hits
630,641c629,640
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 515552500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 515552500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 515552500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 515552500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 515552500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 515552500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 257816284 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 257816284 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 257816284 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 257816284 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 257816284 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 257816284 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 518689000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 518689000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 518689000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 518689000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 518689000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 518689000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 257816283 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses
648,653c647,652
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19354.750910 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19354.750910 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19354.750910 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19354.750910 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency
668,673c667,672
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 488916500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 488916500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 488916500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 488916500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 488916500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 488916500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles
680,700c679,699
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18354.788452 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18354.788452 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 258816 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 32567.443571 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1247529 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 291562 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.278778 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 2619.708679 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.014636 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 29858.720256 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.079947 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002717 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.911216 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 32746 # Occupied blocks per task id
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 258837 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
702c701
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id
704,711c703,710
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29128 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999329 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 13229556 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 13229556 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 88716 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 88716 # number of WritebackDirty hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits
718,719c717,718
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490282 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 490282 # number of ReadSharedReq hits
---
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490275 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 490275 # number of ReadSharedReq hits
721,722c720,721
< system.cpu.l2cache.demand_hits::cpu.data 493513 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 517580 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 493506 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 517573 # number of demand (read+write) hits
724,725c723,724
< system.cpu.l2cache.overall_hits::cpu.data 493513 # number of overall hits
< system.cpu.l2cache.overall_hits::total 517580 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 493506 # number of overall hits
> system.cpu.l2cache.overall_hits::total 517573 # number of overall hits
730,731c729,730
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222592 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 222592 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses
733,734c732,733
< system.cpu.l2cache.demand_misses::cpu.data 288683 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 291253 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 291260 # number of demand (read+write) misses
736,751c735,750
< system.cpu.l2cache.overall_misses::cpu.data 288683 # number of overall misses
< system.cpu.l2cache.overall_misses::total 291253 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4946370000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4946370000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194980000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 194980000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17689881000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 17689881000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 194980000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 22636251000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 22831231000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 194980000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 22636251000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 22831231000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 88716 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 88716 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses
> system.cpu.l2cache.overall_misses::total 291260 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses)
770,771c769,770
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312246 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312246 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses
773,774c772,773
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.369067 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.360090 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.360099 # miss rate for demand accesses
776,789c775,788
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.369067 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.360090 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74841.809021 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74841.809021 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.704280 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.704280 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79472.222721 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79472.222721 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78389.685256 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78389.685256 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency
812,813c811,812
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222566 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222566 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses
815,816c814,815
< system.cpu.l2cache.demand_mshr_misses::cpu.data 288657 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 291223 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses
818,831c817,830
< system.cpu.l2cache.overall_mshr_misses::cpu.data 288657 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 291223 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285460000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285460000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169076000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169076000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15462440500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15462440500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169076000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19747900500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 19916976500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169076000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19747900500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 19916976500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles
836,837c835,836
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312209 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312209 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses
839,840c838,839
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.360053 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses
842,855c841,854
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.360053 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64841.809021 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64841.809021 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65890.880748 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65890.880748 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69473.506735 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69473.506735 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency
859,860c858,859
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
862c861
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
864c863
< system.cpu.toL2Bus.trans_dist::WritebackDirty 154814 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution
866c865
< system.cpu.toL2Bus.trans_dist::CleanEvict 882102 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution
875,877c874,876
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55738368 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 59035712 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 258816 # Total snoops (count)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736576 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 59033920 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 258837 # Total snoops (count)
879,881c878,880
< system.cpu.toL2Bus.snoop_fanout::samples 1067649 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.004997 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.070711 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 1067670 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.005005 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.070770 # Request fanout histogram
883,884c882,883
< system.cpu.toL2Bus.snoop_fanout::0 1062329 99.50% 99.50% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 5305 0.50% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1062341 99.50% 99.50% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 5314 0.50% 100.00% # Request fanout histogram
889,890c888,889
< system.cpu.toL2Bus.snoop_fanout::total 1067649 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 919510000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1067670 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 919482000 # Layer occupancy (ticks)
896,897c895,902
< system.membus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 225131 # Transaction distribution
---
> system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 225138 # Transaction distribution
899c904
< system.membus.trans_dist::CleanEvict 190690 # Transaction distribution
---
> system.membus.trans_dist::CleanEvict 190702 # Transaction distribution
902,906c907,911
< system.membus.trans_dist::ReadSharedReq 225131 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839232 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 839232 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868480 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 22868480 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868928 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22868928 # Cumulative packet size per connected master and slave (bytes)
909c914
< system.membus.snoop_fanout::samples 548010 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 291229 # Request fanout histogram
913c918
< system.membus.snoop_fanout::0 548010 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram
918,919c923,924
< system.membus.snoop_fanout::total 548010 # Request fanout histogram
< system.membus.reqLayer0.occupancy 917220500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 291229 # Request fanout histogram
> system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks)
921c926
< system.membus.respLayer1.occupancy 1554785500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks)