4,5c4,5
< sim_ticks 542257602500 # Number of ticks simulated
< final_tick 542257602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 542257676500 # Number of ticks simulated
> final_tick 542257676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 121737 # Simulator instruction rate (inst/s)
< host_op_rate 149875 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 103039759 # Simulator tick rate (ticks/s)
< host_mem_usage 317376 # Number of bytes of host memory used
< host_seconds 5262.61 # Real time elapsed on the host
---
> host_inst_rate 169610 # Simulator instruction rate (inst/s)
> host_op_rate 208813 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 143560034 # Simulator tick rate (ticks/s)
> host_mem_usage 325880 # Number of bytes of host memory used
> host_seconds 3777.22 # Real time elapsed on the host
16,17c16,17
< system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 18470528 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 164608 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 18470592 # Number of bytes read from this memory
19,20c19,20
< system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_inst_read::cpu.inst 164608 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 164608 # Number of instructions bytes read from this memory
23,24c23,24
< system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 288602 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 2572 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 288603 # Number of read requests responded to by this memory
28,38c28,38
< system.physmem.bw_read::cpu.inst 303679 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 34062276 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 34365954 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 303679 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 303679 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 7801222 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 7801222 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 7801222 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 303679 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 34062276 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 42167176 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 303560 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 34062389 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 34365950 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 303560 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 303560 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 7801221 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 7801221 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 7801221 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 303560 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 34062389 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 42167171 # Total bandwidth to/from this memory (bytes/s)
43,44c43,44
< system.physmem.bytesReadDRAM 18614208 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 20992 # Total number of bytes read from write queue
---
> system.physmem.bytesReadDRAM 18614336 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue
48c48
< system.physmem.servicedByWrQ 328 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue
52,56c52,56
< system.physmem.perBankRdBursts::1 18134 # Per bank write bursts
< system.physmem.perBankRdBursts::2 18219 # Per bank write bursts
< system.physmem.perBankRdBursts::3 18172 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18271 # Per bank write bursts
< system.physmem.perBankRdBursts::5 18399 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 18135 # Per bank write bursts
> system.physmem.perBankRdBursts::2 18220 # Per bank write bursts
> system.physmem.perBankRdBursts::3 18173 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18273 # Per bank write bursts
> system.physmem.perBankRdBursts::5 18400 # Per bank write bursts
58,59c58,59
< system.physmem.perBankRdBursts::7 17991 # Per bank write bursts
< system.physmem.perBankRdBursts::8 18028 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 17989 # Per bank write bursts
> system.physmem.perBankRdBursts::8 18030 # Per bank write bursts
63,66c63,66
< system.physmem.perBankRdBursts::12 18215 # Per bank write bursts
< system.physmem.perBankRdBursts::13 18268 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18078 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18258 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 18214 # Per bank write bursts
> system.physmem.perBankRdBursts::13 18267 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18257 # Per bank write bursts
85c85
< system.physmem.totGap 542257509000 # Total gap between requests
---
> system.physmem.totGap 542257582000 # Total gap between requests
100c100
< system.physmem.rdQLenPdf::0 290456 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 290458 # What read queue length does an incoming req see
196,203c196,203
< system.physmem.bytesPerActivate::samples 111041 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 205.695554 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 133.912944 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 256.637901 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 45880 41.32% 41.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 43577 39.24% 80.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 9434 8.50% 89.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1633 1.47% 90.53% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 111013 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 205.748588 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 133.953680 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 256.656452 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 45849 41.30% 41.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 43580 39.26% 80.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 9433 8.50% 89.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 1634 1.47% 90.53% # Bytes accessed per row activation
206c206
< system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::768-895 515 0.46% 92.21% # Bytes accessed per row activation
209c209
< system.physmem.bytesPerActivate::total 111041 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::total 111013 # Bytes accessed per row activation
211,213c211,213
< system.physmem.rdPerTurnAround::mean 48.509833 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 34.246439 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 506.588678 # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::mean 48.510331 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 34.246707 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 506.588684 # Reads before turning the bus around for writes
227,230c227,230
< system.physmem.totQLat 2871354000 # Total ticks spent queuing
< system.physmem.totMemAccLat 8324735250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1454235000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9872.39 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 2868100000 # Total ticks spent queuing
> system.physmem.totMemAccLat 8321518750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1454245000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9861.13 # Average queueing delay per DRAM burst
232c232
< system.physmem.avgMemAccLat 28622.39 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 28611.13 # Average memory access latency per DRAM burst
243,251c243,251
< system.physmem.readRowHits 194229 # Number of row buffer hits during reads
< system.physmem.writeRowHits 51633 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 66.78 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.12 # Row buffer hit rate for writes
< system.physmem.avgGap 1517767.95 # Average gap between requests
< system.physmem.pageHitRate 68.88 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 420124320 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 229234500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1135836000 # Energy for read commands per rank (pJ)
---
> system.physmem.readRowHits 194250 # Number of row buffer hits during reads
> system.physmem.writeRowHits 51642 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 66.79 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes
> system.physmem.avgGap 1517768.15 # Average gap between requests
> system.physmem.pageHitRate 68.89 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 419905080 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 229114875 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1135859400 # Energy for read commands per rank (pJ)
254,258c254,258
< system.physmem_0.actBackEnergy 107502461415 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 231049769250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 375970079325 # Total energy per rank (pJ)
< system.physmem_0.averagePower 693.351550 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 383670371250 # Time in different power states
---
> system.physmem_0.actBackEnergy 107383469355 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 231154143750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 375955146300 # Total energy per rank (pJ)
> system.physmem_0.averagePower 693.324021 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 383844481500 # Time in different power states
261c261
< system.physmem_0.memoryStateTime::ACT 140473012000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 140298894750 # Time in different power states
263,265c263,265
< system.physmem_1.actEnergy 419247360 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 228756000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1132271400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 419254920 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 228760125 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1132255800 # Energy for read commands per rank (pJ)
268,272c268,272
< system.physmem_1.actBackEnergy 108055650690 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 230564511000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 376030187250 # Total energy per rank (pJ)
< system.physmem_1.averagePower 693.462409 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 382864555750 # Time in different power states
---
> system.physmem_1.actBackEnergy 107988829875 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 230623125750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 376021977270 # Total energy per rank (pJ)
> system.physmem_1.averagePower 693.447269 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 382962347750 # Time in different power states
275c275
< system.physmem_1.memoryStateTime::ACT 141281958750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 141184235750 # Time in different power states
277c277
< system.cpu.branchPred.lookups 154805772 # Number of BP lookups
---
> system.cpu.branchPred.lookups 154805770 # Number of BP lookups
280c280
< system.cpu.branchPred.BTBLookups 90693369 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 90693367 # Number of BTB lookups
283c283
< system.cpu.branchPred.BTBHitPct 91.615651 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 91.615653 # BTB Hit Percentage
404c404
< system.cpu.numCycles 1084515205 # number of cpu cycles simulated
---
> system.cpu.numCycles 1084515353 # number of cpu cycles simulated
409c409
< system.cpu.discardedOps 23906785 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 23906784 # Number of ops (including micro ops) which were discarded before commit
411c411
< system.cpu.cpi 1.692822 # CPI: cycles per instruction
---
> system.cpu.cpi 1.692823 # CPI: cycles per instruction
413,414c413,414
< system.cpu.tickCycles 1025899032 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 58616173 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 1025899498 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 58615855 # Total number of cycles that the object has spent stopped
416c416
< system.cpu.dcache.tags.tagsinuse 4092.484062 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4092.484054 # Cycle average of tags in use
421c421
< system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484062 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484054 # Average occupied blocks per requestor
457,464c457,464
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762813000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 24762813000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105718500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10105718500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34868531500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34868531500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34868531500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34868531500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762143500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 24762143500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105570000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10105570000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 34867713500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 34867713500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 34867713500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 34867713500 # number of overall miss cycles
489,496c489,496
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34687.835142 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34687.835142 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73382.991315 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73382.991315 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 40945.306298 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 40945.306298 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 40938.527982 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 40938.527982 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34686.897304 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34686.897304 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73381.912978 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 73381.912978 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 40944.345740 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 40944.345740 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 40937.567583 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 40937.567583 # average overall miss latency
525,528c525,528
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24034165000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 24034165000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067912500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067912500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24033231500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 24033231500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067791500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067791500 # number of WriteReq MSHR miss cycles
531,534c531,534
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29102077500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 29102077500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29103932500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 29103932500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29101023000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 29101023000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29102878000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 29102878000 # number of overall MSHR miss cycles
545,548c545,548
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33709.735558 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33709.735558 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73106.841984 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73106.841984 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33708.426254 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33708.426254 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73105.096506 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73105.096506 # average WriteReq mshr miss latency
551,554c551,554
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37200.851724 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 37200.851724 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37196.613776 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 37196.613776 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37199.503768 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 37199.503768 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37195.266060 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 37195.266060 # average overall mshr miss latency
557,558c557,558
< system.cpu.icache.tags.tagsinuse 1713.095623 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 291576498 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1713.095615 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 291576499 # Total number of references to valid blocks.
560c560
< system.cpu.icache.tags.avg_refs 11505.662458 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 11505.662497 # Average number of references to valid blocks.
562c562
< system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095623 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095615 # Average occupied blocks per requestor
570,577c570,577
< system.cpu.icache.tags.tag_accesses 583229024 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 583229024 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 291576498 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 291576498 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 291576498 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 291576498 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 291576498 # number of overall hits
< system.cpu.icache.overall_hits::total 291576498 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 583229026 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 583229026 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 291576499 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 291576499 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 291576499 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 291576499 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 291576499 # number of overall hits
> system.cpu.icache.overall_hits::total 291576499 # number of overall hits
584,595c584,595
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 498098000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 498098000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 498098000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 498098000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 498098000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 498098000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 291601841 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 291601841 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 291601841 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 291601841 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 291601841 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 291601841 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 499290500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 499290500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 499290500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 499290500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 499290500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 499290500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 291601842 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 291601842 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 291601842 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 291601842 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 291601842 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 291601842 # number of overall (read+write) accesses
602,607c602,607
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19654.263505 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19654.263505 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19654.263505 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19654.263505 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19701.317918 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 19701.317918 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 19701.317918 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 19701.317918 # average overall miss latency
622,627c622,627
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 472756000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 472756000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 472756000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 472756000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 472756000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 472756000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 473948500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 473948500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 473948500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 473948500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 473948500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 473948500 # number of overall MSHR miss cycles
634,639c634,639
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18654.302963 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18654.302963 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18701.357377 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18701.357377 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency
642c642
< system.cpu.l2cache.tags.tagsinuse 32574.709364 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 32574.709394 # Cycle average of tags in use
647,649c647,649
< system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156166 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.700113 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 29894.853085 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156414 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.726448 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 29895.826532 # Average occupied blocks per requestor
651,652c651,652
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002768 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.912319 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002738 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.912348 # Average percentage of cache occupancy
689,700c689,700
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4930001500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4930001500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195708000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 195708000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17815243000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 17815243000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 195708000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 22745244500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 22940952500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 195708000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 22745244500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 22940952500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4929880500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4929880500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195624000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 195624000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17812302500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 17812302500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 195624000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 22742183000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 22937807000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 195624000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 22742183000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 22937807000 # number of overall miss cycles
727,738c727,738
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74594.142924 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74594.142924 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75914.662529 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75914.662529 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80054.475845 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80054.475845 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75914.662529 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78804.159304 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78778.579229 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75914.662529 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78804.159304 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78778.579229 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74592.312115 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74592.312115 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75882.079131 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75882.079131 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80041.262430 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80041.262430 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78767.777671 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78767.777671 # average overall miss latency
749,754c749,754
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 28 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 28 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
756,757c756,757
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits
---
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
763,768c763,768
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2574 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2574 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222511 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222511 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 288602 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2573 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2573 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222512 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222512 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2573 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 288603 # number of demand (read+write) MSHR misses
770,771c770,771
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 288602 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2573 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 288603 # number of overall MSHR misses
773,784c773,784
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4269091500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4269091500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169723000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169723000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15588307500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15588307500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169723000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19857399000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 20027122000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169723000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19857399000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20027122000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268970500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268970500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169583000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169583000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15585424500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15585424500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169583000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19854395000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 20023978000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169583000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19854395000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 20023978000 # number of overall MSHR miss cycles
789,794c789,794
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101567 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312028 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312028 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368851 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101527 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312029 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312029 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for demand accesses
796,797c796,797
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368851 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for overall accesses
799,810c799,810
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64594.142924 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64594.142924 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65937.451437 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65937.451437 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70056.345529 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70056.345529 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64592.312115 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64592.312115 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65908.666926 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65908.666926 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70043.074081 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70043.074081 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency
811a812,817
> system.cpu.toL2Bus.snoop_filter.tot_requests 1609708 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 801990 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3351 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
827,828c833,834
< system.cpu.toL2Bus.snoop_fanout::mean 1.138319 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.345235 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.004713 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.068609 # Request fanout histogram
830,832c836,838
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1609708 86.17% 86.17% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 258395 13.83% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1859313 99.53% 99.53% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 8775 0.47% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram
834c840
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
839c845
< system.cpu.toL2Bus.respLayer0.occupancy 38014996 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 38015495 # Layer occupancy (ticks)
841c847
< system.cpu.toL2Bus.respLayer1.occupancy 1173666472 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1173665973 # Layer occupancy (ticks)
864c870
< system.membus.reqLayer0.occupancy 917948500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 917954000 # Layer occupancy (ticks)
866c872
< system.membus.respLayer1.occupancy 1554418250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1554429500 # Layer occupancy (ticks)
< sim_ticks 542257602500 # Number of ticks simulated
< final_tick 542257602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 542257676500 # Number of ticks simulated
> final_tick 542257676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 121737 # Simulator instruction rate (inst/s)
< host_op_rate 149875 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 103039759 # Simulator tick rate (ticks/s)
< host_mem_usage 317376 # Number of bytes of host memory used
< host_seconds 5262.61 # Real time elapsed on the host
---
> host_inst_rate 169610 # Simulator instruction rate (inst/s)
> host_op_rate 208813 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 143560034 # Simulator tick rate (ticks/s)
> host_mem_usage 325880 # Number of bytes of host memory used
> host_seconds 3777.22 # Real time elapsed on the host
16,17c16,17
< system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 18470528 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 164608 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 18470592 # Number of bytes read from this memory
19,20c19,20
< system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_inst_read::cpu.inst 164608 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 164608 # Number of instructions bytes read from this memory
23,24c23,24
< system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 288602 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 2572 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 288603 # Number of read requests responded to by this memory
28,38c28,38
< system.physmem.bw_read::cpu.inst 303679 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 34062276 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 34365954 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 303679 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 303679 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 7801222 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 7801222 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 7801222 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 303679 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 34062276 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 42167176 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 303560 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 34062389 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 34365950 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 303560 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 303560 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 7801221 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 7801221 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 7801221 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 303560 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 34062389 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 42167171 # Total bandwidth to/from this memory (bytes/s)
43,44c43,44
< system.physmem.bytesReadDRAM 18614208 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 20992 # Total number of bytes read from write queue
---
> system.physmem.bytesReadDRAM 18614336 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue
48c48
< system.physmem.servicedByWrQ 328 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue
52,56c52,56
< system.physmem.perBankRdBursts::1 18134 # Per bank write bursts
< system.physmem.perBankRdBursts::2 18219 # Per bank write bursts
< system.physmem.perBankRdBursts::3 18172 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18271 # Per bank write bursts
< system.physmem.perBankRdBursts::5 18399 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 18135 # Per bank write bursts
> system.physmem.perBankRdBursts::2 18220 # Per bank write bursts
> system.physmem.perBankRdBursts::3 18173 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18273 # Per bank write bursts
> system.physmem.perBankRdBursts::5 18400 # Per bank write bursts
58,59c58,59
< system.physmem.perBankRdBursts::7 17991 # Per bank write bursts
< system.physmem.perBankRdBursts::8 18028 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 17989 # Per bank write bursts
> system.physmem.perBankRdBursts::8 18030 # Per bank write bursts
63,66c63,66
< system.physmem.perBankRdBursts::12 18215 # Per bank write bursts
< system.physmem.perBankRdBursts::13 18268 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18078 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18258 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 18214 # Per bank write bursts
> system.physmem.perBankRdBursts::13 18267 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18257 # Per bank write bursts
85c85
< system.physmem.totGap 542257509000 # Total gap between requests
---
> system.physmem.totGap 542257582000 # Total gap between requests
100c100
< system.physmem.rdQLenPdf::0 290456 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 290458 # What read queue length does an incoming req see
196,203c196,203
< system.physmem.bytesPerActivate::samples 111041 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 205.695554 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 133.912944 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 256.637901 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 45880 41.32% 41.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 43577 39.24% 80.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 9434 8.50% 89.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1633 1.47% 90.53% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 111013 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 205.748588 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 133.953680 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 256.656452 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 45849 41.30% 41.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 43580 39.26% 80.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 9433 8.50% 89.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 1634 1.47% 90.53% # Bytes accessed per row activation
206c206
< system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::768-895 515 0.46% 92.21% # Bytes accessed per row activation
209c209
< system.physmem.bytesPerActivate::total 111041 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::total 111013 # Bytes accessed per row activation
211,213c211,213
< system.physmem.rdPerTurnAround::mean 48.509833 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 34.246439 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 506.588678 # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::mean 48.510331 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 34.246707 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 506.588684 # Reads before turning the bus around for writes
227,230c227,230
< system.physmem.totQLat 2871354000 # Total ticks spent queuing
< system.physmem.totMemAccLat 8324735250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1454235000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9872.39 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 2868100000 # Total ticks spent queuing
> system.physmem.totMemAccLat 8321518750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1454245000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9861.13 # Average queueing delay per DRAM burst
232c232
< system.physmem.avgMemAccLat 28622.39 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 28611.13 # Average memory access latency per DRAM burst
243,251c243,251
< system.physmem.readRowHits 194229 # Number of row buffer hits during reads
< system.physmem.writeRowHits 51633 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 66.78 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.12 # Row buffer hit rate for writes
< system.physmem.avgGap 1517767.95 # Average gap between requests
< system.physmem.pageHitRate 68.88 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 420124320 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 229234500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1135836000 # Energy for read commands per rank (pJ)
---
> system.physmem.readRowHits 194250 # Number of row buffer hits during reads
> system.physmem.writeRowHits 51642 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 66.79 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes
> system.physmem.avgGap 1517768.15 # Average gap between requests
> system.physmem.pageHitRate 68.89 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 419905080 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 229114875 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1135859400 # Energy for read commands per rank (pJ)
254,258c254,258
< system.physmem_0.actBackEnergy 107502461415 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 231049769250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 375970079325 # Total energy per rank (pJ)
< system.physmem_0.averagePower 693.351550 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 383670371250 # Time in different power states
---
> system.physmem_0.actBackEnergy 107383469355 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 231154143750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 375955146300 # Total energy per rank (pJ)
> system.physmem_0.averagePower 693.324021 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 383844481500 # Time in different power states
261c261
< system.physmem_0.memoryStateTime::ACT 140473012000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 140298894750 # Time in different power states
263,265c263,265
< system.physmem_1.actEnergy 419247360 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 228756000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1132271400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 419254920 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 228760125 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1132255800 # Energy for read commands per rank (pJ)
268,272c268,272
< system.physmem_1.actBackEnergy 108055650690 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 230564511000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 376030187250 # Total energy per rank (pJ)
< system.physmem_1.averagePower 693.462409 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 382864555750 # Time in different power states
---
> system.physmem_1.actBackEnergy 107988829875 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 230623125750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 376021977270 # Total energy per rank (pJ)
> system.physmem_1.averagePower 693.447269 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 382962347750 # Time in different power states
275c275
< system.physmem_1.memoryStateTime::ACT 141281958750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 141184235750 # Time in different power states
277c277
< system.cpu.branchPred.lookups 154805772 # Number of BP lookups
---
> system.cpu.branchPred.lookups 154805770 # Number of BP lookups
280c280
< system.cpu.branchPred.BTBLookups 90693369 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 90693367 # Number of BTB lookups
283c283
< system.cpu.branchPred.BTBHitPct 91.615651 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 91.615653 # BTB Hit Percentage
404c404
< system.cpu.numCycles 1084515205 # number of cpu cycles simulated
---
> system.cpu.numCycles 1084515353 # number of cpu cycles simulated
409c409
< system.cpu.discardedOps 23906785 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 23906784 # Number of ops (including micro ops) which were discarded before commit
411c411
< system.cpu.cpi 1.692822 # CPI: cycles per instruction
---
> system.cpu.cpi 1.692823 # CPI: cycles per instruction
413,414c413,414
< system.cpu.tickCycles 1025899032 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 58616173 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 1025899498 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 58615855 # Total number of cycles that the object has spent stopped
416c416
< system.cpu.dcache.tags.tagsinuse 4092.484062 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4092.484054 # Cycle average of tags in use
421c421
< system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484062 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484054 # Average occupied blocks per requestor
457,464c457,464
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762813000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 24762813000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105718500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10105718500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34868531500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34868531500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34868531500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34868531500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762143500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 24762143500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105570000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10105570000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 34867713500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 34867713500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 34867713500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 34867713500 # number of overall miss cycles
489,496c489,496
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34687.835142 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34687.835142 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73382.991315 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73382.991315 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 40945.306298 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 40945.306298 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 40938.527982 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 40938.527982 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34686.897304 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34686.897304 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73381.912978 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 73381.912978 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 40944.345740 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 40944.345740 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 40937.567583 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 40937.567583 # average overall miss latency
525,528c525,528
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24034165000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 24034165000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067912500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067912500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24033231500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 24033231500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067791500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067791500 # number of WriteReq MSHR miss cycles
531,534c531,534
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29102077500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 29102077500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29103932500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 29103932500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29101023000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 29101023000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29102878000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 29102878000 # number of overall MSHR miss cycles
545,548c545,548
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33709.735558 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33709.735558 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73106.841984 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73106.841984 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33708.426254 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33708.426254 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73105.096506 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73105.096506 # average WriteReq mshr miss latency
551,554c551,554
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37200.851724 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 37200.851724 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37196.613776 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 37196.613776 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37199.503768 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 37199.503768 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37195.266060 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 37195.266060 # average overall mshr miss latency
557,558c557,558
< system.cpu.icache.tags.tagsinuse 1713.095623 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 291576498 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1713.095615 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 291576499 # Total number of references to valid blocks.
560c560
< system.cpu.icache.tags.avg_refs 11505.662458 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 11505.662497 # Average number of references to valid blocks.
562c562
< system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095623 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095615 # Average occupied blocks per requestor
570,577c570,577
< system.cpu.icache.tags.tag_accesses 583229024 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 583229024 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 291576498 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 291576498 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 291576498 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 291576498 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 291576498 # number of overall hits
< system.cpu.icache.overall_hits::total 291576498 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 583229026 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 583229026 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 291576499 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 291576499 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 291576499 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 291576499 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 291576499 # number of overall hits
> system.cpu.icache.overall_hits::total 291576499 # number of overall hits
584,595c584,595
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 498098000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 498098000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 498098000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 498098000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 498098000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 498098000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 291601841 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 291601841 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 291601841 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 291601841 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 291601841 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 291601841 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 499290500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 499290500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 499290500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 499290500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 499290500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 499290500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 291601842 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 291601842 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 291601842 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 291601842 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 291601842 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 291601842 # number of overall (read+write) accesses
602,607c602,607
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19654.263505 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19654.263505 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19654.263505 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19654.263505 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19701.317918 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 19701.317918 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 19701.317918 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 19701.317918 # average overall miss latency
622,627c622,627
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 472756000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 472756000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 472756000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 472756000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 472756000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 472756000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 473948500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 473948500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 473948500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 473948500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 473948500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 473948500 # number of overall MSHR miss cycles
634,639c634,639
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18654.302963 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18654.302963 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18701.357377 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18701.357377 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency
642c642
< system.cpu.l2cache.tags.tagsinuse 32574.709364 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 32574.709394 # Cycle average of tags in use
647,649c647,649
< system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156166 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.700113 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 29894.853085 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156414 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.726448 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 29895.826532 # Average occupied blocks per requestor
651,652c651,652
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002768 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.912319 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002738 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.912348 # Average percentage of cache occupancy
689,700c689,700
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4930001500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4930001500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195708000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 195708000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17815243000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 17815243000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 195708000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 22745244500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 22940952500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 195708000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 22745244500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 22940952500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4929880500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4929880500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195624000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 195624000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17812302500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 17812302500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 195624000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 22742183000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 22937807000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 195624000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 22742183000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 22937807000 # number of overall miss cycles
727,738c727,738
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74594.142924 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74594.142924 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75914.662529 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75914.662529 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80054.475845 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80054.475845 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75914.662529 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78804.159304 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78778.579229 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75914.662529 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78804.159304 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78778.579229 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74592.312115 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74592.312115 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75882.079131 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75882.079131 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80041.262430 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80041.262430 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78767.777671 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78767.777671 # average overall miss latency
749,754c749,754
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 28 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 28 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
756,757c756,757
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits
---
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
763,768c763,768
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2574 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2574 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222511 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222511 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 288602 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2573 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2573 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222512 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222512 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2573 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 288603 # number of demand (read+write) MSHR misses
770,771c770,771
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 288602 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2573 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 288603 # number of overall MSHR misses
773,784c773,784
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4269091500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4269091500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169723000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169723000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15588307500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15588307500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169723000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19857399000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 20027122000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169723000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19857399000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20027122000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268970500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268970500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169583000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169583000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15585424500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15585424500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169583000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19854395000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 20023978000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169583000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19854395000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 20023978000 # number of overall MSHR miss cycles
789,794c789,794
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101567 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312028 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312028 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368851 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101527 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312029 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312029 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for demand accesses
796,797c796,797
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368851 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for overall accesses
799,810c799,810
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64594.142924 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64594.142924 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65937.451437 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65937.451437 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70056.345529 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70056.345529 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64592.312115 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64592.312115 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65908.666926 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65908.666926 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70043.074081 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70043.074081 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency
811a812,817
> system.cpu.toL2Bus.snoop_filter.tot_requests 1609708 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 801990 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3351 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
827,828c833,834
< system.cpu.toL2Bus.snoop_fanout::mean 1.138319 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.345235 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.004713 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.068609 # Request fanout histogram
830,832c836,838
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1609708 86.17% 86.17% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 258395 13.83% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1859313 99.53% 99.53% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 8775 0.47% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram
834c840
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
839c845
< system.cpu.toL2Bus.respLayer0.occupancy 38014996 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 38015495 # Layer occupancy (ticks)
841c847
< system.cpu.toL2Bus.respLayer1.occupancy 1173666472 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1173665973 # Layer occupancy (ticks)
864c870
< system.membus.reqLayer0.occupancy 917948500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 917954000 # Layer occupancy (ticks)
866c872
< system.membus.respLayer1.occupancy 1554418250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1554429500 # Layer occupancy (ticks)