3,5c3,5
< sim_seconds 0.545048 # Number of seconds simulated
< sim_ticks 545048444500 # Number of ticks simulated
< final_tick 545048444500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.541773 # Number of seconds simulated
> sim_ticks 541773299500 # Number of ticks simulated
> final_tick 541773299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,9c7,9
< host_inst_rate 177094 # Simulator instruction rate (inst/s)
< host_op_rate 218026 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 150665678 # Simulator tick rate (ticks/s)
---
> host_inst_rate 180126 # Simulator instruction rate (inst/s)
> host_op_rate 221759 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 152324877 # Simulator tick rate (ticks/s)
11c11
< host_seconds 3617.60 # Real time elapsed on the host
---
> host_seconds 3556.70 # Real time elapsed on the host
16,20c16,20
< system.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 18429312 # Number of bytes read from this memory
< system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 164800 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 18429120 # Number of bytes read from this memory
> system.physmem.bytes_read::total 18593920 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 164800 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 164800 # Number of instructions bytes read from this memory
23,25c23,25
< system.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 287958 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 2575 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 287955 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 290530 # Number of read requests responded to by this memory
28,39c28,39
< system.physmem.bw_read::cpu.inst 301889 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 33812246 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 34114135 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 301889 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 301889 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 7761277 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 7761277 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 7761277 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 301889 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 33812246 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 41875412 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 290529 # Number of read requests accepted
---
> system.physmem.bw_read::cpu.inst 304186 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 34016294 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 34320481 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 304186 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 304186 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 7808196 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 7808196 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 7808196 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 304186 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 34016294 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 42128676 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 290530 # Number of read requests accepted
41c41
< system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 290530 # Number of DRAM read bursts, including those serviced by the write queue
43,46c43,46
< system.physmem.bytesReadDRAM 18574016 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4228992 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side
---
> system.physmem.bytesReadDRAM 18574272 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4228608 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 18593920 # Total read bytes from the system interface side
48c48
< system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue
51,52c51,52
< system.physmem.perBankRdBursts::0 18284 # Per bank write bursts
< system.physmem.perBankRdBursts::1 18137 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 18288 # Per bank write bursts
> system.physmem.perBankRdBursts::1 18136 # Per bank write bursts
54,59c54,59
< system.physmem.perBankRdBursts::3 18185 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18266 # Per bank write bursts
< system.physmem.perBankRdBursts::5 18315 # Per bank write bursts
< system.physmem.perBankRdBursts::6 18094 # Per bank write bursts
< system.physmem.perBankRdBursts::7 17909 # Per bank write bursts
< system.physmem.perBankRdBursts::8 17941 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 18182 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18272 # Per bank write bursts
> system.physmem.perBankRdBursts::5 18313 # Per bank write bursts
> system.physmem.perBankRdBursts::6 18098 # Per bank write bursts
> system.physmem.perBankRdBursts::7 17913 # Per bank write bursts
> system.physmem.perBankRdBursts::8 17942 # Per bank write bursts
61,66c61,66
< system.physmem.perBankRdBursts::10 18019 # Per bank write bursts
< system.physmem.perBankRdBursts::11 18118 # Per bank write bursts
< system.physmem.perBankRdBursts::12 18147 # Per bank write bursts
< system.physmem.perBankRdBursts::13 18275 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18266 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 18020 # Per bank write bursts
> system.physmem.perBankRdBursts::11 18117 # Per bank write bursts
> system.physmem.perBankRdBursts::12 18146 # Per bank write bursts
> system.physmem.perBankRdBursts::13 18271 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18079 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18260 # Per bank write bursts
68c68
< system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
---
> system.physmem.perBankWrBursts::1 4100 # Per bank write bursts
71c71
< system.physmem.perBankWrBursts::4 4226 # Per bank write bursts
---
> system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
74,80c74,80
< system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
< system.physmem.perBankWrBursts::8 4095 # Per bank write bursts
< system.physmem.perBankWrBursts::9 4090 # Per bank write bursts
< system.physmem.perBankWrBursts::10 4090 # Per bank write bursts
< system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
< system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
< system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
> system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
> system.physmem.perBankWrBursts::9 4092 # Per bank write bursts
> system.physmem.perBankWrBursts::10 4093 # Per bank write bursts
> system.physmem.perBankWrBursts::11 4095 # Per bank write bursts
> system.physmem.perBankWrBursts::12 4096 # Per bank write bursts
> system.physmem.perBankWrBursts::13 4094 # Per bank write bursts
82c82
< system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
85c85
< system.physmem.totGap 545048350000 # Total gap between requests
---
> system.physmem.totGap 541773205000 # Total gap between requests
92c92
< system.physmem.readPktSize::6 290529 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 290530 # Read request sizes (log2)
100c100
< system.physmem.rdQLenPdf::0 289827 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see
102c102
< system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see
147,149c147,149
< system.physmem.wrQLenPdf::15 967 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 967 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4010 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 964 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 964 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see
152c152
< system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see
154,157c154,157
< system.physmem.wrQLenPdf::22 4009 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 4009 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 4009 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 4009 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 4010 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4011 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 4010 # What write queue length does an incoming req see
159c159
< system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::27 4011 # What write queue length does an incoming req see
196,209c196,209
< system.physmem.bytesPerActivate::samples 112309 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 203.026151 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 132.211216 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 254.422571 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 47277 42.10% 42.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 43772 38.97% 81.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8960 7.98% 89.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1911 1.70% 90.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 490 0.44% 91.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 736 0.66% 91.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 729 0.65% 92.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 499 0.44% 92.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7935 7.07% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 112309 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 112123 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 203.355529 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 132.415015 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 254.574164 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 47170 42.07% 42.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 43612 38.90% 80.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 9039 8.06% 89.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 1917 1.71% 90.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 483 0.43% 91.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 738 0.66% 91.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 730 0.65% 92.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 502 0.45% 92.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7932 7.07% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 112123 # Bytes accessed per row activation
212,213c212,213
< system.physmem.rdPerTurnAround::gmean 36.056534 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 507.518625 # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::gmean 36.058155 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 507.570273 # Reads before turning the bus around for writes
220,226c220,225
< system.physmem.wrPerTurnAround::mean 16.482415 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.461068 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.856030 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3042 75.88% 75.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 1 0.02% 75.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 965 24.07% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::mean 16.480918 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.459590 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.855706 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3046 75.98% 75.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 961 23.97% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
228,231c227,230
< system.physmem.totQLat 2724193250 # Total ticks spent queuing
< system.physmem.totMemAccLat 8165799500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1451095000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9386.68 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 2883248250 # Total ticks spent queuing
> system.physmem.totMemAccLat 8324929500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1451115000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9934.60 # Average queueing delay per DRAM burst
233,237c232,236
< system.physmem.avgMemAccLat 28136.68 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 7.76 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28684.60 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 7.81 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s
243,260c242,259
< system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing
< system.physmem.readRowHits 193908 # Number of row buffer hits during reads
< system.physmem.writeRowHits 50072 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes
< system.physmem.avgGap 1528342.92 # Average gap between requests
< system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 423889200 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 231288750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1134182400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 35599708560 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 106422668235 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 233674110000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 377701475625 # Total energy per rank (pJ)
< system.physmem_0.averagePower 692.972318 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 388027097500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 18200260000 # Time in different power states
---
> system.physmem.avgWrQLen 25.18 # Average write queue length when enqueuing
> system.physmem.readRowHits 194064 # Number of row buffer hits during reads
> system.physmem.writeRowHits 50094 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 66.87 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes
> system.physmem.avgGap 1519154.99 # Average gap between requests
> system.physmem.pageHitRate 68.52 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 423874080 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 231280500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1134198000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 215622000 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 35385604800 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 107588305125 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 230684814750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 375663699255 # Total energy per rank (pJ)
> system.physmem_0.averagePower 693.403859 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 383052702750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 18090800000 # Time in different power states
262c261
< system.physmem_0.memoryStateTime::ACT 138818528500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 140624192250 # Time in different power states
264,274c263,273
< system.physmem_1.actEnergy 425113920 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 231957000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1129245000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 212556960 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 35599708560 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 106328346345 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 233756848500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 377683776285 # Total energy per rank (pJ)
< system.physmem_1.averagePower 692.939845 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 388162097500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 18200260000 # Time in different power states
---
> system.physmem_1.actEnergy 423692640 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 231181500 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1129104600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 212524560 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 35385604800 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 107075040930 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 231135046500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 375592195530 # Total energy per rank (pJ)
> system.physmem_1.averagePower 693.271876 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 383804077000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 18090800000 # Time in different power states
276c275
< system.physmem_1.memoryStateTime::ACT 138683202500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 139874284500 # Time in different power states
278,282c277,281
< system.cpu.branchPred.lookups 155052076 # Number of BP lookups
< system.cpu.branchPred.condPredicted 105344550 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 12879569 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 90401009 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 82966187 # Number of BTB hits
---
> system.cpu.branchPred.lookups 156119313 # Number of BP lookups
> system.cpu.branchPred.condPredicted 106151666 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 12881666 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 90098747 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 82494804 # Number of BTB hits
284,286c283,285
< system.cpu.branchPred.BTBHitPct 91.775731 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 19284792 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 91.560434 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 19276925 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1327 # Number of incorrect RAS predictions.
405c404
< system.cpu.numCycles 1090096889 # number of cpu cycles simulated
---
> system.cpu.numCycles 1083546599 # number of cpu cycles simulated
410c409
< system.cpu.discardedOps 22623818 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 23911488 # Number of ops (including micro ops) which were discarded before commit
412,424c411,423
< system.cpu.cpi 1.701535 # CPI: cycles per instruction
< system.cpu.ipc 0.587705 # IPC: instructions per cycle
< system.cpu.tickCycles 1030366439 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 59730450 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 778156 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4092.460333 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 378456871 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 782252 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 483.804287 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460333 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999136 # Average percentage of cache occupancy
---
> system.cpu.cpi 1.691310 # CPI: cycles per instruction
> system.cpu.ipc 0.591258 # IPC: instructions per cycle
> system.cpu.tickCycles 1025165387 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 58381212 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 778275 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4092.437677 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 378454072 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 782371 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 483.727122 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 802618250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4092.437677 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999130 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999130 # Average percentage of cache occupancy
428,430c427,429
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 1339 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::4 1593 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1345 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::4 1586 # Occupied blocks per task id
432,437c431,436
< system.cpu.dcache.tags.tag_accesses 759399046 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 759399046 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 249628143 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 249628143 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 759393811 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 759393811 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 249625343 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 249625343 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits
444,451c443,450
< system.cpu.dcache.demand_hits::cpu.data 378441908 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 378441908 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 378445393 # number of overall hits
< system.cpu.dcache.overall_hits::total 378445393 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 713673 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 713673 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 378439109 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 378439109 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 378442594 # number of overall hits
> system.cpu.dcache.overall_hits::total 378442594 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 713796 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 713796 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses
454,467c453,466
< system.cpu.dcache.demand_misses::cpu.data 851385 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 851385 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 851526 # number of overall misses
< system.cpu.dcache.overall_misses::total 851526 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 24678796218 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 24678796218 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10203720250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10203720250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34882516468 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34882516468 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34882516468 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34882516468 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 250341816 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 250341816 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 851507 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 851507 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 851648 # number of overall misses
> system.cpu.dcache.overall_misses::total 851648 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 24839025218 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 24839025218 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10202615750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10202615750 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 35041640968 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 35041640968 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 35041640968 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 35041640968 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 250339139 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 250339139 # number of ReadReq accesses(hits+misses)
476,479c475,478
< system.cpu.dcache.demand_accesses::cpu.data 379293293 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 379293293 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 379296919 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 379296919 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 379290616 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 379290616 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 379294242 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 379294242 # number of overall (read+write) accesses
490,497c489,496
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34579.977410 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34579.977410 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74094.634091 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74094.634091 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 40971.495232 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 40971.495232 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.710964 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 40964.710964 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34798.493152 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34798.493152 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74087.151716 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74087.151716 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 41152.499002 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 41152.499002 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 41145.685739 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 41145.685739 # average overall miss latency
508,517c507,516
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 882 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 882 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 69272 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 69272 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 69272 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 69272 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712791 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 712791 # number of ReadReq MSHR misses
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 886 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 886 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 69275 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 69275 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 69275 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 69275 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712910 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 712910 # number of ReadReq MSHR misses
522,529c521,528
< system.cpu.dcache.demand_mshr_misses::cpu.data 782113 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 782113 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 782252 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 782252 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23523501277 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 23523501277 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5052240750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5052240750 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 782232 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 782232 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 782371 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 782371 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23683196777 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 23683196777 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5051765250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5051765250 # number of WriteReq MSHR miss cycles
532,537c531,536
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28575742027 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 28575742027 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28577461027 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 28577461027 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28734962027 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 28734962027 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28736681027 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28736681027 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
544,549c543,548
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33001.961693 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33001.961693 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72880.770174 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72880.770174 # average WriteReq mshr miss latency
---
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33220.458090 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33220.458090 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72873.910880 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72873.910880 # average WriteReq mshr miss latency
552,555c551,554
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36536.590016 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 36536.590016 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36532.295254 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 36532.295254 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36734.577500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 36734.577500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36730.248216 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 36730.248216 # average overall mshr miss latency
557,561c556,560
< system.cpu.icache.tags.replacements 23595 # number of replacements
< system.cpu.icache.tags.tagsinuse 1710.136306 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 292011682 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 25344 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 11521.925584 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 23596 # number of replacements
> system.cpu.icache.tags.tagsinuse 1712.059457 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 290105857 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 11445.372510 # Average number of references to valid blocks.
563,567c562,566
< system.cpu.icache.tags.occ_blocks::cpu.inst 1710.136306 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.835027 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.835027 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1712.059457 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.835967 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.835967 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
569,596c568,595
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1601 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.854004 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 584099398 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 584099398 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 292011682 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 292011682 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 292011682 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 292011682 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 292011682 # number of overall hits
< system.cpu.icache.overall_hits::total 292011682 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 25345 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 25345 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 25345 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 25345 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 25345 # number of overall misses
< system.cpu.icache.overall_misses::total 25345 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 498945745 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 498945745 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 498945745 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 498945745 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 498945745 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 498945745 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 292037027 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 292037027 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 292037027 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 292037027 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 292037027 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 292037027 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 580287757 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 580287757 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 290105857 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 290105857 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 290105857 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 290105857 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 290105857 # number of overall hits
> system.cpu.icache.overall_hits::total 290105857 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses
> system.cpu.icache.overall_misses::total 25348 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 499853745 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 499853745 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 499853745 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 499853745 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 499853745 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 499853745 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 290131205 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 290131205 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 290131205 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 290131205 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 290131205 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 290131205 # number of overall (read+write) accesses
603,608c602,607
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19686.160781 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19686.160781 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19686.160781 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19686.160781 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19686.160781 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19686.160781 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19719.652241 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 19719.652241 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 19719.652241 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 19719.652241 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 19719.652241 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 19719.652241 # average overall miss latency
617,628c616,627
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25345 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 25345 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 25345 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 25345 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 25345 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 25345 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 459825255 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 459825255 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 459825255 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 459825255 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 459825255 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 459825255 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460727755 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 460727755 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460727755 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 460727755 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460727755 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 460727755 # number of overall MSHR miss cycles
635,640c634,639
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18142.641744 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18142.641744 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18142.641744 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18142.641744 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18142.641744 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18142.641744 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18176.098903 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18176.098903 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18176.098903 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18176.098903 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18176.098903 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18176.098903 # average overall mshr miss latency
642,646c641,645
< system.cpu.l2cache.tags.replacements 257749 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 32573.780035 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 539008 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 1.855494 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 257750 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 32572.840203 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 539129 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 1.855904 # Average number of references to valid blocks.
648,654c647,653
< system.cpu.l2cache.tags.occ_blocks::writebacks 2882.224162 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.373270 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 29602.182603 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002727 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.903387 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.994073 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2880.993603 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.456847 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 29602.389753 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.087921 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002730 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.903393 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.994044 # Average percentage of cache occupancy
656c655
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
659,660c658,659
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2792 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29435 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2810 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29416 # Occupied blocks per task id
662,666c661,665
< system.cpu.l2cache.tags.tag_accesses 7551951 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 7551951 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 22768 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 491036 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 513804 # number of ReadReq hits
---
> system.cpu.l2cache.tags.tag_accesses 7552928 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 7552928 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 22767 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 491158 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 513925 # number of ReadReq hits
671,679c670,678
< system.cpu.l2cache.demand_hits::cpu.inst 22768 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 494267 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 517035 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 22768 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 494267 # number of overall hits
< system.cpu.l2cache.overall_hits::total 517035 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 2577 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 221894 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses
---
> system.cpu.l2cache.demand_hits::cpu.inst 22767 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 494389 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 517156 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 22767 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 494389 # number of overall hits
> system.cpu.l2cache.overall_hits::total 517156 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 2581 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 221891 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 224472 # number of ReadReq misses
682,701c681,700
< system.cpu.l2cache.demand_misses::cpu.inst 2577 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 287985 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2577 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 287985 # number of overall misses
< system.cpu.l2cache.overall_misses::total 290562 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 195416750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17656346250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 17851763000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4948991250 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4948991250 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 195416750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 22605337500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 22800754250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 195416750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 22605337500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 22800754250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 25345 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 712930 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 738275 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.demand_misses::cpu.inst 2581 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 287982 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 290563 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2581 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 287982 # number of overall misses
> system.cpu.l2cache.overall_misses::total 290563 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196326750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17814641750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18010968500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4948515750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4948515750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 196326750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 22763157500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 22959484250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 196326750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 22763157500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 22959484250 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 713049 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 738397 # number of ReadReq accesses(hits+misses)
706,714c705,713
< system.cpu.l2cache.demand_accesses::cpu.inst 25345 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 782252 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 807597 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 25345 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 782252 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 807597 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101677 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311242 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.304048 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 25348 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 782371 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 807719 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 25348 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 782371 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 807719 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101823 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311186 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.303999 # miss rate for ReadReq accesses
717,733c716,732
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101677 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.368149 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.359786 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101677 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.368149 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.359786 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75831.102057 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79571.084617 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 79528.148402 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74881.470246 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74881.470246 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75831.102057 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78494.843481 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78471.218707 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75831.102057 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78494.843481 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78471.218707 # average overall miss latency
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101823 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.368089 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.359733 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101823 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.368089 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.359733 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76066.156528 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80285.553492 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 80237.038473 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74874.275620 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74874.275620 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76066.156528 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79043.681550 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 79017.232924 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76066.156528 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79043.681550 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 79017.232924 # average overall miss latency
753,755c752,754
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2572 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221867 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2576 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221864 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 224440 # number of ReadReq MSHR misses
758,777c757,776
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 287958 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 287958 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 162876000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14878894250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15041770250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4120650250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4120650250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 162876000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18999544500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 19162420500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 162876000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18999544500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 19162420500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311204 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304005 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2576 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 287955 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 290531 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2576 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 287955 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 290531 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163738000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15037461500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15201199500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4120172250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4120172250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163738000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19157633750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 19321371750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163738000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19157633750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 19321371750 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311148 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303956 # mshr miss rate for ReadReq accesses
780,796c779,795
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368114 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.359746 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368114 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.359746 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63326.594090 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67062.223089 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67019.413961 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62348.129851 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62348.129851 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63326.594090 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65980.262747 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65956.770385 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63326.594090 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65980.262747 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65956.770385 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368054 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.359693 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368054 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.359693 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63562.888199 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67777.834619 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67729.457762 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62340.897399 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62340.897399 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63562.888199 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66529.956938 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66503.649352 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63562.888199 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66529.956938 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66503.649352 # average overall mshr miss latency
798,799c797,798
< system.cpu.toL2Bus.trans_dist::ReadReq 738275 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 738274 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 738397 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 738396 # Transaction distribution
803,808c802,807
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50689 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655924 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 1706613 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622016 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55915008 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 57537024 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656162 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 1706857 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55922624 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 57544832 # Cumulative packet size per connected master and slave (bytes)
810c809
< system.cpu.toL2Bus.snoop_fanout::samples 899017 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 899139 # Request fanout histogram
815c814
< system.cpu.toL2Bus.snoop_fanout::1 899017 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 899139 100.00% 100.00% # Request fanout histogram
820,821c819,820
< system.cpu.toL2Bus.snoop_fanout::total 899017 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 540928500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 899139 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 540989500 # Layer occupancy (ticks)
823c822
< system.cpu.toL2Bus.respLayer0.occupancy 38568245 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 38573245 # Layer occupancy (ticks)
825c824
< system.cpu.toL2Bus.respLayer1.occupancy 1224009973 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1224491973 # Layer occupancy (ticks)
827,828c826,827
< system.membus.trans_dist::ReadReq 224438 # Transaction distribution
< system.membus.trans_dist::ReadResp 224438 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 224439 # Transaction distribution
> system.membus.trans_dist::ReadResp 224439 # Transaction distribution
832,835c831,834
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647158 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 647158 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824192 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22824192 # Cumulative packet size per connected master and slave (bytes)
837c836
< system.membus.snoop_fanout::samples 356627 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 356628 # Request fanout histogram
841c840
< system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 356628 100.00% 100.00% # Request fanout histogram
846,847c845,846
< system.membus.snoop_fanout::total 356627 # Request fanout histogram
< system.membus.reqLayer0.occupancy 732101500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 356628 # Request fanout histogram
> system.membus.reqLayer0.occupancy 731800000 # Layer occupancy (ticks)
849c848
< system.membus.respLayer1.occupancy 1551130500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1550863750 # Layer occupancy (ticks)