3,5c3,5
< sim_seconds 0.541786 # Number of seconds simulated
< sim_ticks 541786101000 # Number of ticks simulated
< final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.545057 # Number of seconds simulated
> sim_ticks 545056655500 # Number of ticks simulated
> final_tick 545056655500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 115987 # Simulator instruction rate (inst/s)
< host_op_rate 142796 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 98087491 # Simulator tick rate (ticks/s)
< host_mem_usage 309428 # Number of bytes of host memory used
< host_seconds 5523.50 # Real time elapsed on the host
---
> host_inst_rate 182072 # Simulator instruction rate (inst/s)
> host_op_rate 224154 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 154902851 # Simulator tick rate (ticks/s)
> host_mem_usage 321108 # Number of bytes of host memory used
> host_seconds 3518.70 # Real time elapsed on the host
16,20c16,20
< system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 18429184 # Number of bytes read from this memory
< system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 164864 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 18429248 # Number of bytes read from this memory
> system.physmem.bytes_read::total 18594112 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 164864 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 164864 # Number of instructions bytes read from this memory
23,25c23,25
< system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 287956 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 2576 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 287957 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 290533 # Number of read requests responded to by this memory
28,39c28,39
< system.physmem.bw_read::cpu.inst 303943 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 34015609 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 303943 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 34015609 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 290529 # Number of read requests accepted
---
> system.physmem.bw_read::cpu.inst 302471 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 33811619 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 34114090 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 302471 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 302471 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 7761160 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 7761160 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 7761160 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 302471 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 33811619 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 41875251 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 290533 # Number of read requests accepted
41c41
< system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 290533 # Number of DRAM read bursts, including those serviced by the write queue
43,46c43,46
< system.physmem.bytesReadDRAM 18572736 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side
---
> system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 18594112 # Total read bytes from the system interface side
48c48
< system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue
51,53c51,53
< system.physmem.perBankRdBursts::0 18289 # Per bank write bursts
< system.physmem.perBankRdBursts::1 18137 # Per bank write bursts
< system.physmem.perBankRdBursts::2 18222 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 18287 # Per bank write bursts
> system.physmem.perBankRdBursts::1 18141 # Per bank write bursts
> system.physmem.perBankRdBursts::2 18224 # Per bank write bursts
55,62c55,62
< system.physmem.perBankRdBursts::4 18266 # Per bank write bursts
< system.physmem.perBankRdBursts::5 18308 # Per bank write bursts
< system.physmem.perBankRdBursts::6 18094 # Per bank write bursts
< system.physmem.perBankRdBursts::7 17914 # Per bank write bursts
< system.physmem.perBankRdBursts::8 17939 # Per bank write bursts
< system.physmem.perBankRdBursts::9 17962 # Per bank write bursts
< system.physmem.perBankRdBursts::10 18018 # Per bank write bursts
< system.physmem.perBankRdBursts::11 18110 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 18267 # Per bank write bursts
> system.physmem.perBankRdBursts::5 18318 # Per bank write bursts
> system.physmem.perBankRdBursts::6 18100 # Per bank write bursts
> system.physmem.perBankRdBursts::7 17916 # Per bank write bursts
> system.physmem.perBankRdBursts::8 17940 # Per bank write bursts
> system.physmem.perBankRdBursts::9 17966 # Per bank write bursts
> system.physmem.perBankRdBursts::10 18025 # Per bank write bursts
> system.physmem.perBankRdBursts::11 18111 # Per bank write bursts
64,70c64,70
< system.physmem.perBankRdBursts::13 18270 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18266 # Per bank write bursts
< system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
< system.physmem.perBankWrBursts::1 4101 # Per bank write bursts
< system.physmem.perBankWrBursts::2 4137 # Per bank write bursts
< system.physmem.perBankWrBursts::3 4147 # Per bank write bursts
---
> system.physmem.perBankRdBursts::13 18269 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18078 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
> system.physmem.perBankWrBursts::0 4173 # Per bank write bursts
> system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
> system.physmem.perBankWrBursts::2 4136 # Per bank write bursts
> system.physmem.perBankWrBursts::3 4146 # Per bank write bursts
72c72
< system.physmem.perBankWrBursts::5 4225 # Per bank write bursts
---
> system.physmem.perBankWrBursts::5 4223 # Per bank write bursts
74,75c74,75
< system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
< system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
> system.physmem.perBankWrBursts::8 4094 # Per bank write bursts
77,80c77,80
< system.physmem.perBankWrBursts::10 4090 # Per bank write bursts
< system.physmem.perBankWrBursts::11 4094 # Per bank write bursts
< system.physmem.perBankWrBursts::12 4096 # Per bank write bursts
< system.physmem.perBankWrBursts::13 4094 # Per bank write bursts
---
> system.physmem.perBankWrBursts::10 4093 # Per bank write bursts
> system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
> system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
> system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
82c82
< system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
85c85
< system.physmem.totGap 541786012500 # Total gap between requests
---
> system.physmem.totGap 545056561000 # Total gap between requests
92c92
< system.physmem.readPktSize::6 290529 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 290533 # Read request sizes (log2)
100,101c100,101
< system.physmem.rdQLenPdf::0 289803 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 289840 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 375 # What read queue length does an incoming req see
147,164c147,164
< system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 989 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4006 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4007 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4007 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4007 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 4006 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 4006 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4006 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4006 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4006 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 966 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 966 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 4011 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4009 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 4009 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 4009 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4009 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see
196,214c196,214
< system.physmem.bytesPerActivate::samples 111554 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 204.382452 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 132.554579 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 255.928936 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 47007 42.14% 42.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 43571 39.06% 81.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8721 7.82% 89.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 769 0.69% 89.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 1361 1.22% 90.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1221 1.09% 92.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 537 0.48% 92.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 497 0.45% 92.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 111554 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4006 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 48.553919 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 36.073633 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 507.732262 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 4003 99.93% 99.93% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 112305 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 203.035662 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 132.214062 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 254.437736 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 47268 42.09% 42.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 43750 38.96% 81.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 8988 8.00% 89.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 1909 1.70% 90.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 489 0.44% 91.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 737 0.66% 91.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 726 0.65% 92.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 505 0.45% 92.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7933 7.06% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 112305 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 48.526066 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 36.050433 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 507.549530 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes
218,231c218,229
< system.physmem.rdPerTurnAround::total 4006 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4006 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.492761 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.471115 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.861913 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3018 75.34% 75.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 3 0.07% 75.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 984 24.56% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4006 # Writes before turning the bus around for reads
< system.physmem.totQLat 2707676000 # Total ticks spent queuing
< system.physmem.totMemAccLat 8148907250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1450995000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9330.41 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.481417 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.460113 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.855134 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3044 75.93% 75.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 965 24.07% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads
> system.physmem.totQLat 2737356250 # Total ticks spent queuing
> system.physmem.totMemAccLat 8179187500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9431.65 # Average queueing delay per DRAM burst
233,237c231,235
< system.physmem.avgMemAccLat 28080.41 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28181.65 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 7.76 # Average system write bandwidth in MiByte/s
243,246c241,244
< system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing
< system.physmem.readRowHits 194608 # Number of row buffer hits during reads
< system.physmem.writeRowHits 50098 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 67.06 # Row buffer hit rate for reads
---
> system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing
> system.physmem.readRowHits 193898 # Number of row buffer hits during reads
> system.physmem.writeRowHits 50093 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads
248,260c246,258
< system.physmem.avgGap 1519195.16 # Average gap between requests
< system.physmem.pageHitRate 68.68 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 421810200 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 230154375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1134190200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 106352983170 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 231777774000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 375519162345 # Total energy per rank (pJ)
< system.physmem_0.averagePower 693.117148 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 384873582500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 18091320000 # Time in different power states
---
> system.physmem.avgGap 1528348.80 # Average gap between requests
> system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 424002600 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 231350625 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1134369600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 215570160 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 106884947925 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 233273273250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 377763731280 # Total energy per rank (pJ)
> system.physmem_0.averagePower 693.076638 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 387358600750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 18200520000 # Time in different power states
262c260
< system.physmem_0.memoryStateTime::ACT 138818819500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 139494961250 # Time in different power states
264,274c262,272
< system.physmem_1.actEnergy 421477560 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 229972875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1129034400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 212505120 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 105425199585 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 232591619250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 375396430710 # Total energy per rank (pJ)
< system.physmem_1.averagePower 692.890615 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 386233048000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 18091320000 # Time in different power states
---
> system.physmem_1.actEnergy 424962720 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 231874500 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1129096800 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 105917359815 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 234122034750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 377638135065 # Total energy per rank (pJ)
> system.physmem_1.averagePower 692.846209 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 388771820250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 18200520000 # Time in different power states
276c274
< system.physmem_1.memoryStateTime::ACT 137458753250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 138081006000 # Time in different power states
278,282c276,280
< system.cpu.branchPred.lookups 156937341 # Number of BP lookups
< system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 97536058 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 81874318 # Number of BTB hits
---
> system.cpu.branchPred.lookups 155213668 # Number of BP lookups
> system.cpu.branchPred.condPredicted 105449696 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 12879317 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 90304208 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 82854286 # Number of BTB hits
284,286c282,284
< system.cpu.branchPred.BTBHitPct 83.942615 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 91.750194 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 19341274 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions.
405c403
< system.cpu.numCycles 1083572202 # number of cpu cycles simulated
---
> system.cpu.numCycles 1090113311 # number of cpu cycles simulated
410c408
< system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 22623250 # Number of ops (including micro ops) which were discarded before commit
412,424c410,422
< system.cpu.cpi 1.691350 # CPI: cycles per instruction
< system.cpu.ipc 0.591244 # IPC: instructions per cycle
< system.cpu.tickCycles 1029141566 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 54430636 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 778221 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4092.645412 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4092.645412 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999181 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy
---
> system.cpu.cpi 1.701560 # CPI: cycles per instruction
> system.cpu.ipc 0.587696 # IPC: instructions per cycle
> system.cpu.tickCycles 1030411592 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 59701719 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 778141 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4092.460106 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 378456482 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 782237 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 483.813067 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460106 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999136 # Average percentage of cache occupancy
427,430c425,428
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 1341 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1339 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::4 1594 # Occupied blocks per task id
432,437c430,435
< system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 249632505 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 128813764 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 759397955 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 759397955 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 249631239 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 249631239 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits
442,463c440,461
< system.cpu.dcache.demand_hits::cpu.data 378446269 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 378446269 # number of overall hits
< system.cpu.dcache.overall_hits::total 378446269 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 713747 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 137713 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 851460 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 851460 # number of overall misses
< system.cpu.dcache.overall_misses::total 851460 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 23055853217 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9199211000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 32255064217 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 32255064217 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 250346252 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 378445004 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 378445004 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 378445004 # number of overall hits
> system.cpu.dcache.overall_hits::total 378445004 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 713665 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 713665 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 851377 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 851377 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 851377 # number of overall misses
> system.cpu.dcache.overall_misses::total 851377 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 24698082718 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 24698082718 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10190251750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10190251750 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 34888334468 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 34888334468 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 34888334468 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 34888334468 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 250344904 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 250344904 # number of ReadReq accesses(hits+misses)
470,473c468,471
< system.cpu.dcache.demand_accesses::cpu.data 379297729 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 379297729 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 379296381 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 379296381 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 379296381 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 379296381 # number of overall (read+write) accesses
482,489c480,487
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32302.557092 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66799.873650 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.389627 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.389627 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73996.832157 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 73996.832157 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 40978.713858 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 40978.713858 # average overall miss latency
500,509c498,507
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 752 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68391 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 69143 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 69143 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712995 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 750 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 750 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 69140 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 69140 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 69140 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 69140 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712915 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 712915 # number of ReadReq MSHR misses
512,523c510,521
< system.cpu.dcache.demand_mshr_misses::cpu.data 782317 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 782317 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21545578028 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4531082000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26076660028 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26076660028 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 782237 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 782237 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 782237 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 782237 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23543649027 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 23543649027 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5045531250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5045531250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28589180277 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 28589180277 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589180277 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28589180277 # number of overall MSHR miss cycles
528,539c526,537
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30218.413913 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65362.828539 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33024.482620 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33024.482620 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72783.982718 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72783.982718 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency
541,545c539,543
< system.cpu.icache.tags.replacements 23590 # number of replacements
< system.cpu.icache.tags.tagsinuse 1712.180561 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 289921723 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 11440.816187 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 23596 # number of replacements
> system.cpu.icache.tags.tagsinuse 1712.064969 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 291953853 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 11518.280388 # Average number of references to valid blocks.
547,549c545,547
< system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180561 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064969 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.835969 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.835969 # Average percentage of cache occupancy
551c549
< system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
553c551
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id
555,580c553,578
< system.cpu.icache.tags.tag_accesses 579919471 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 579919471 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 289921723 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 289921723 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 289921723 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 289921723 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 289921723 # number of overall hits
< system.cpu.icache.overall_hits::total 289921723 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses
< system.cpu.icache.overall_misses::total 25342 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 480693746 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 480693746 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 480693746 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 480693746 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 480693746 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 480693746 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 289947065 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 289947065 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 289947065 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 289947065 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 289947065 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 289947065 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 583983749 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 583983749 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 291953853 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 291953853 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 291953853 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 291953853 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 291953853 # number of overall hits
> system.cpu.icache.overall_hits::total 291953853 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses
> system.cpu.icache.overall_misses::total 25348 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 499968245 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 499968245 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 499968245 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 499968245 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 499968245 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 499968245 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 291979201 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 291979201 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 291979201 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 291979201 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 291979201 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 291979201 # number of overall (read+write) accesses
587,592c585,590
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.263989 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18968.263989 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18968.263989 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18968.263989 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19724.169362 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 19724.169362 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 19724.169362 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 19724.169362 # average overall miss latency
601,612c599,610
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25342 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 25342 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 25342 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 25342 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 25342 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 25342 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428909254 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 428909254 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428909254 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 428909254 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428909254 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 428909254 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460840255 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 460840255 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460840255 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 460840255 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460840255 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 460840255 # number of overall MSHR miss cycles
619,624c617,622
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.838371 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.838371 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18180.537123 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18180.537123 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency
626,630c624,628
< system.cpu.l2cache.tags.replacements 257749 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 32583.111771 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 257753 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 32573.758002 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 538992 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 290497 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 1.855413 # Average number of references to valid blocks.
632,638c630,636
< system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.519731 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 29632.926805 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002732 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.904325 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231587 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601373 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925042 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002734 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.903379 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.994072 # Average percentage of cache occupancy
640,644c638,642
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2800 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 287 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2793 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29433 # Occupied blocks per task id
646,650c644,648
< system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 7552447 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 22764 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 491102 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 513866 # number of ReadReq hits
---
> system.cpu.l2cache.tags.tag_accesses 7551859 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 7551859 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 22766 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 491022 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 513788 # number of ReadReq hits
655,661c653,659
< system.cpu.l2cache.demand_hits::cpu.inst 22764 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 494333 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 517097 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 22764 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 494333 # number of overall hits
< system.cpu.l2cache.overall_hits::total 517097 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 2578 # number of ReadReq misses
---
> system.cpu.l2cache.demand_hits::cpu.inst 22766 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 494253 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 517019 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 22766 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 494253 # number of overall hits
> system.cpu.l2cache.overall_hits::total 517019 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 2582 # number of ReadReq misses
663c661
< system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 224475 # number of ReadReq misses
666c664
< system.cpu.l2cache.demand_misses::cpu.inst 2578 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 2582 # number of demand (read+write) misses
668,669c666,667
< system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 290566 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2582 # number of overall misses
671,685c669,683
< system.cpu.l2cache.overall_misses::total 290562 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175909750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15921496500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 16097406250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4429448000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4429448000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 175909750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 20350944500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 20526854250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 175909750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 20350944500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 20526854250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 25342 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 712995 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 290566 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196449750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17674937000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 17871386750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942281750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4942281750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 196449750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 22617218750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 22813668500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 196449750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 22617218750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 22813668500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 712915 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 738263 # number of ReadReq accesses(hits+misses)
690,698c688,696
< system.cpu.l2cache.demand_accesses::cpu.inst 25342 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 782317 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 807659 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 25342 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 782317 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 807659 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101728 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311213 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.304022 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 25348 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 782237 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 807585 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 25348 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 782237 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 807585 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101862 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311247 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.304058 # miss rate for ReadReq accesses
701,717c699,715
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101728 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.368117 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101728 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.368117 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68234.968968 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71753.036373 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67020.441512 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101862 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.368154 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.359796 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101862 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.368154 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.359796 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76084.333850 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79655.225717 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 79614.151910 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74779.951128 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74779.951128 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78514.583606 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78514.583606 # average overall miss latency
728,729c726,727
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 28 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits
731,732c729,730
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
734,735c732,733
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits
---
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
737,739c735,737
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2574 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221865 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2577 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221866 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 224443 # number of ReadReq MSHR misses
742,761c740,759
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 287956 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 287956 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143321250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13141995500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577310000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143321250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16719305500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143321250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16719305500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311173 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2577 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 287957 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 290534 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2577 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 287957 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 290534 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163845000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14897681250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15061526250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113937750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113937750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163845000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19011619000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 19175464000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163845000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19011619000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 19175464000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311210 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304015 # mshr miss rate for ReadReq accesses
764,780c762,778
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55680.361305 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59234.198724 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54127.036964 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.359757 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.359757 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63579.743888 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67147.202591 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67106.241897 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62246.565342 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62246.565342 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency
782,783c780,781
< system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 738263 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 738262 # Transaction distribution
787,792c785,790
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656054 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 1706737 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621824 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55919168 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 57540992 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655894 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 1706589 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55914048 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 57536256 # Cumulative packet size per connected master and slave (bytes)
794,795c792,793
< system.cpu.toL2Bus.snoop_fanout::samples 899079 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 899005 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
801,804c799,800
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 899079 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 899005 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
806,809c802,805
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 899079 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 899005 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 540922500 # Layer occupancy (ticks)
811c807
< system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 38574245 # Layer occupancy (ticks)
813c809
< system.cpu.toL2Bus.respLayer1.occupancy 1224351972 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1224003723 # Layer occupancy (ticks)
815,816c811,812
< system.membus.trans_dist::ReadReq 224438 # Transaction distribution
< system.membus.trans_dist::ReadResp 224438 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 224442 # Transaction distribution
> system.membus.trans_dist::ReadResp 224442 # Transaction distribution
820,823c816,819
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647164 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 647164 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824384 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22824384 # Cumulative packet size per connected master and slave (bytes)
825c821
< system.membus.snoop_fanout::samples 356627 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 356631 # Request fanout histogram
829c825
< system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 356631 100.00% 100.00% # Request fanout histogram
834,838c830,834
< system.membus.snoop_fanout::total 356627 # Request fanout histogram
< system.membus.reqLayer0.occupancy 983550500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2739032750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
---
> system.membus.snoop_fanout::total 356631 # Request fanout histogram
> system.membus.reqLayer0.occupancy 731515500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer1.occupancy 1551221000 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.3 # Layer utilization (%)