7,11c7,11
< host_inst_rate 114564 # Simulator instruction rate (inst/s)
< host_op_rate 141043 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 96175687 # Simulator tick rate (ticks/s)
< host_mem_usage 263048 # Number of bytes of host memory used
< host_seconds 5592.13 # Real time elapsed on the host
---
> host_inst_rate 160425 # Simulator instruction rate (inst/s)
> host_op_rate 197504 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 134676016 # Simulator tick rate (ticks/s)
> host_mem_usage 315984 # Number of bytes of host memory used
> host_seconds 3993.48 # Real time elapsed on the host
39,41c39,41
< system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM
---
> system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 19200 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM
44c44
< system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 300 # Number of DRAM read bursts serviced by the write queue
47,48c47,48
< system.physmem.perBankRdBursts::0 18283 # Per bank write bursts
< system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 18291 # Per bank write bursts
> system.physmem.perBankRdBursts::1 18140 # Per bank write bursts
50,62c50,62
< system.physmem.perBankRdBursts::3 18187 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18258 # Per bank write bursts
< system.physmem.perBankRdBursts::5 18313 # Per bank write bursts
< system.physmem.perBankRdBursts::6 18090 # Per bank write bursts
< system.physmem.perBankRdBursts::7 17910 # Per bank write bursts
< system.physmem.perBankRdBursts::8 17943 # Per bank write bursts
< system.physmem.perBankRdBursts::9 17966 # Per bank write bursts
< system.physmem.perBankRdBursts::10 18023 # Per bank write bursts
< system.physmem.perBankRdBursts::11 18118 # Per bank write bursts
< system.physmem.perBankRdBursts::12 18159 # Per bank write bursts
< system.physmem.perBankRdBursts::13 18277 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18081 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18260 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 18183 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18268 # Per bank write bursts
> system.physmem.perBankRdBursts::5 18315 # Per bank write bursts
> system.physmem.perBankRdBursts::6 18099 # Per bank write bursts
> system.physmem.perBankRdBursts::7 17920 # Per bank write bursts
> system.physmem.perBankRdBursts::8 17939 # Per bank write bursts
> system.physmem.perBankRdBursts::9 17964 # Per bank write bursts
> system.physmem.perBankRdBursts::10 18020 # Per bank write bursts
> system.physmem.perBankRdBursts::11 18110 # Per bank write bursts
> system.physmem.perBankRdBursts::12 18148 # Per bank write bursts
> system.physmem.perBankRdBursts::13 18270 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18079 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
70,71c70,71
< system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
< system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
> system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
73,74c73,74
< system.physmem.perBankWrBursts::10 4094 # Per bank write bursts
< system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
---
> system.physmem.perBankWrBursts::10 4091 # Per bank write bursts
> system.physmem.perBankWrBursts::11 4094 # Per bank write bursts
76c76
< system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
---
> system.physmem.perBankWrBursts::13 4094 # Per bank write bursts
96c96
< system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see
143,144c143,144
< system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see
152,160c152,160
< system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see
192,210c192,210
< system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 111650 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 204.222194 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 132.352958 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 255.940958 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 47308 42.37% 42.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 43452 38.92% 81.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 8609 7.71% 89.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 837 0.75% 89.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 1286 1.15% 90.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1285 1.15% 92.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 530 0.47% 92.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 473 0.42% 92.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 111650 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 36.062915 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 507.683026 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes
214,227c214,227
< system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads
< system.physmem.totQLat 3341298000 # Total ticks spent queuing
< system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.489643 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 3 0.07% 75.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 978 24.41% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads
> system.physmem.totQLat 3341982750 # Total ticks spent queuing
> system.physmem.totMemAccLat 8783814000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 11514.91 # Average queueing delay per DRAM burst
229c229
< system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 30264.91 # Average memory access latency per DRAM burst
239,243c239,243
< system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing
< system.physmem.readRowHits 194846 # Number of row buffer hits during reads
< system.physmem.writeRowHits 49995 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes
---
> system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing
> system.physmem.readRowHits 194589 # Number of row buffer hits during reads
> system.physmem.writeRowHits 50052 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 67.05 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 75.72 # Row buffer hit rate for writes
245,246c245,246
< system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states
---
> system.physmem.pageHitRate 68.66 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 253474796750 # Time in different power states
249c249
< system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 266386143250 # Time in different power states
251d250
< system.membus.throughput 42437954 # Throughput (bytes/s)
259,263c258,271
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 22824256 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 356629 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 356629 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 356629 # Request fanout histogram
> system.membus.reqLayer0.occupancy 974401000 # Layer occupancy (ticks)
265c273
< system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2738560500 # Layer occupancy (ticks)
371,372c379,380
< system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 1020176456 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 55476541 # Total number of cycles that the object has spent stopped
374c382
< system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1711.183580 # Cycle average of tags in use
379,381c387,389
< system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1711.183580 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.835539 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.835539 # Average percentage of cache occupancy
401,406c409,414
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 480691746 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 480691746 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 480691746 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 480691746 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 480691746 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 480691746 # number of overall miss cycles
419,424c427,432
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18963.695203 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 18963.695203 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 18963.695203 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 18963.695203 # average overall miss latency
439,444c447,452
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428895254 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 428895254 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428895254 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 428895254 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428895254 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 428895254 # number of overall MSHR miss cycles
451,456c459,464
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16920.279864 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16920.279864 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency
458d465
< system.cpu.toL2Bus.throughput 107000990 # Throughput (bytes/s)
467,471c474,492
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 57547968 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 899188 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 899188 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 899188 # Request fanout histogram
474c495
< system.cpu.toL2Bus.respLayer0.occupancy 38572246 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 38571746 # Layer occupancy (ticks)
476c497
< system.cpu.toL2Bus.respLayer1.occupancy 1224995475 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1224928725 # Layer occupancy (ticks)
479c500
< system.cpu.l2cache.tags.tagsinuse 32582.970291 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 32583.011088 # Cycle average of tags in use
484,488c505,509
< system.cpu.l2cache.tags.occ_blocks::writebacks 2866.246405 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.087471 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906882 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.994353 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2866.114553 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.896535 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.087467 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906888 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.994355 # Average percentage of cache occupancy
516,523c537,544
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16737523000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 16737523000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4423362750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4423362750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21160885750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 21160885750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21160885750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 21160885750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16739408750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 16739408750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4422117750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4422117750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21161526500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 21161526500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21161526500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 21161526500 # number of overall miss cycles
542,549c563,570
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.964427 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74573.365364 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 74573.365364 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66908.517672 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66908.517672 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72829.892862 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72829.892862 # average overall miss latency
574,581c595,602
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13902147000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13902147000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3594959250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3594959250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497106250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17497106250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497106250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17497106250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13904175250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13904175250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3593710250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3593710250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497885500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 17497885500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497885500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 17497885500 # number of overall MSHR miss cycles
590,597c611,618
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61950.522411 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61950.522411 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54374.360740 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54374.360740 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency
637,644c658,665
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23698499970 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 23698499970 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9186329500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9186329500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 32884829470 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 32884829470 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 32884829470 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32884829470 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23700601220 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 23700601220 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9183787250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9183787250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 32884388470 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 32884388470 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 32884388470 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 32884388470 # number of overall miss cycles
665,672c686,693
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33201.094376 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 33201.094376 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66750.401573 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 66750.401573 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 38622.357658 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 38622.357658 # average overall miss latency
699,706c720,727
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22188801525 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 22188801525 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4523752250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4523752250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26712553775 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 26712553775 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26712553775 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26712553775 # number of overall MSHR miss cycles
715,722c736,743
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.105558 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31116.105558 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65256.152359 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65256.152359 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency
< host_inst_rate 114564 # Simulator instruction rate (inst/s)
< host_op_rate 141043 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 96175687 # Simulator tick rate (ticks/s)
< host_mem_usage 263048 # Number of bytes of host memory used
< host_seconds 5592.13 # Real time elapsed on the host
---
> host_inst_rate 160425 # Simulator instruction rate (inst/s)
> host_op_rate 197504 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 134676016 # Simulator tick rate (ticks/s)
> host_mem_usage 315984 # Number of bytes of host memory used
> host_seconds 3993.48 # Real time elapsed on the host
39,41c39,41
< system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM
---
> system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 19200 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM
44c44
< system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 300 # Number of DRAM read bursts serviced by the write queue
47,48c47,48
< system.physmem.perBankRdBursts::0 18283 # Per bank write bursts
< system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 18291 # Per bank write bursts
> system.physmem.perBankRdBursts::1 18140 # Per bank write bursts
50,62c50,62
< system.physmem.perBankRdBursts::3 18187 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18258 # Per bank write bursts
< system.physmem.perBankRdBursts::5 18313 # Per bank write bursts
< system.physmem.perBankRdBursts::6 18090 # Per bank write bursts
< system.physmem.perBankRdBursts::7 17910 # Per bank write bursts
< system.physmem.perBankRdBursts::8 17943 # Per bank write bursts
< system.physmem.perBankRdBursts::9 17966 # Per bank write bursts
< system.physmem.perBankRdBursts::10 18023 # Per bank write bursts
< system.physmem.perBankRdBursts::11 18118 # Per bank write bursts
< system.physmem.perBankRdBursts::12 18159 # Per bank write bursts
< system.physmem.perBankRdBursts::13 18277 # Per bank write bursts
< system.physmem.perBankRdBursts::14 18081 # Per bank write bursts
< system.physmem.perBankRdBursts::15 18260 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 18183 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18268 # Per bank write bursts
> system.physmem.perBankRdBursts::5 18315 # Per bank write bursts
> system.physmem.perBankRdBursts::6 18099 # Per bank write bursts
> system.physmem.perBankRdBursts::7 17920 # Per bank write bursts
> system.physmem.perBankRdBursts::8 17939 # Per bank write bursts
> system.physmem.perBankRdBursts::9 17964 # Per bank write bursts
> system.physmem.perBankRdBursts::10 18020 # Per bank write bursts
> system.physmem.perBankRdBursts::11 18110 # Per bank write bursts
> system.physmem.perBankRdBursts::12 18148 # Per bank write bursts
> system.physmem.perBankRdBursts::13 18270 # Per bank write bursts
> system.physmem.perBankRdBursts::14 18079 # Per bank write bursts
> system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
70,71c70,71
< system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
< system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
> system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
73,74c73,74
< system.physmem.perBankWrBursts::10 4094 # Per bank write bursts
< system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
---
> system.physmem.perBankWrBursts::10 4091 # Per bank write bursts
> system.physmem.perBankWrBursts::11 4094 # Per bank write bursts
76c76
< system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
---
> system.physmem.perBankWrBursts::13 4094 # Per bank write bursts
96c96
< system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see
143,144c143,144
< system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see
152,160c152,160
< system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see
192,210c192,210
< system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 111650 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 204.222194 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 132.352958 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 255.940958 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 47308 42.37% 42.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 43452 38.92% 81.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 8609 7.71% 89.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 837 0.75% 89.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 1286 1.15% 90.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1285 1.15% 92.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 530 0.47% 92.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 473 0.42% 92.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 111650 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 36.062915 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 507.683026 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes
214,227c214,227
< system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads
< system.physmem.totQLat 3341298000 # Total ticks spent queuing
< system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.489643 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 3 0.07% 75.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 978 24.41% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads
> system.physmem.totQLat 3341982750 # Total ticks spent queuing
> system.physmem.totMemAccLat 8783814000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 11514.91 # Average queueing delay per DRAM burst
229c229
< system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 30264.91 # Average memory access latency per DRAM burst
239,243c239,243
< system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing
< system.physmem.readRowHits 194846 # Number of row buffer hits during reads
< system.physmem.writeRowHits 49995 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes
---
> system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing
> system.physmem.readRowHits 194589 # Number of row buffer hits during reads
> system.physmem.writeRowHits 50052 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 67.05 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 75.72 # Row buffer hit rate for writes
245,246c245,246
< system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states
---
> system.physmem.pageHitRate 68.66 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 253474796750 # Time in different power states
249c249
< system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 266386143250 # Time in different power states
251d250
< system.membus.throughput 42437954 # Throughput (bytes/s)
259,263c258,271
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 22824256 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 356629 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 356629 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 356629 # Request fanout histogram
> system.membus.reqLayer0.occupancy 974401000 # Layer occupancy (ticks)
265c273
< system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2738560500 # Layer occupancy (ticks)
371,372c379,380
< system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 1020176456 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 55476541 # Total number of cycles that the object has spent stopped
374c382
< system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1711.183580 # Cycle average of tags in use
379,381c387,389
< system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1711.183580 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.835539 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.835539 # Average percentage of cache occupancy
401,406c409,414
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 480691746 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 480691746 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 480691746 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 480691746 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 480691746 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 480691746 # number of overall miss cycles
419,424c427,432
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18963.695203 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 18963.695203 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 18963.695203 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 18963.695203 # average overall miss latency
439,444c447,452
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428895254 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 428895254 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428895254 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 428895254 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428895254 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 428895254 # number of overall MSHR miss cycles
451,456c459,464
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16920.279864 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16920.279864 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency
458d465
< system.cpu.toL2Bus.throughput 107000990 # Throughput (bytes/s)
467,471c474,492
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 57547968 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 899188 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 899188 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 899188 # Request fanout histogram
474c495
< system.cpu.toL2Bus.respLayer0.occupancy 38572246 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 38571746 # Layer occupancy (ticks)
476c497
< system.cpu.toL2Bus.respLayer1.occupancy 1224995475 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1224928725 # Layer occupancy (ticks)
479c500
< system.cpu.l2cache.tags.tagsinuse 32582.970291 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 32583.011088 # Cycle average of tags in use
484,488c505,509
< system.cpu.l2cache.tags.occ_blocks::writebacks 2866.246405 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.087471 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906882 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.994353 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2866.114553 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.896535 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.087467 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906888 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.994355 # Average percentage of cache occupancy
516,523c537,544
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16737523000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 16737523000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4423362750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4423362750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21160885750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 21160885750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21160885750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 21160885750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16739408750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 16739408750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4422117750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4422117750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21161526500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 21161526500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21161526500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 21161526500 # number of overall miss cycles
542,549c563,570
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.964427 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74573.365364 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 74573.365364 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66908.517672 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66908.517672 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72829.892862 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72829.892862 # average overall miss latency
574,581c595,602
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13902147000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13902147000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3594959250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3594959250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497106250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17497106250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497106250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17497106250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13904175250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13904175250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3593710250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3593710250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497885500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 17497885500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497885500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 17497885500 # number of overall MSHR miss cycles
590,597c611,618
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61950.522411 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61950.522411 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54374.360740 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54374.360740 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency
637,644c658,665
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23698499970 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 23698499970 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9186329500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9186329500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 32884829470 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 32884829470 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 32884829470 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32884829470 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23700601220 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 23700601220 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9183787250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9183787250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 32884388470 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 32884388470 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 32884388470 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 32884388470 # number of overall miss cycles
665,672c686,693
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33201.094376 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 33201.094376 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66750.401573 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 66750.401573 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 38622.357658 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 38622.357658 # average overall miss latency
699,706c720,727
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22188801525 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 22188801525 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4523752250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4523752250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26712553775 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 26712553775 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26712553775 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26712553775 # number of overall MSHR miss cycles
715,722c736,743
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.105558 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31116.105558 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65256.152359 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65256.152359 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency