Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.537826 # Number of seconds simulated
4sim_ticks 537826498500 # Number of ticks simulated
5final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 114564 # Simulator instruction rate (inst/s)
8host_op_rate 141043 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 96175687 # Simulator tick rate (ticks/s)
10host_mem_usage 263048 # Number of bytes of host memory used
11host_seconds 5592.13 # Real time elapsed on the host

7host_inst_rate 160425 # Simulator instruction rate (inst/s)
8host_op_rate 197504 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 134676016 # Simulator tick rate (ticks/s)
10host_mem_usage 315984 # Number of bytes of host memory used
11host_seconds 3993.48 # Real time elapsed on the host

12sim_insts 640655084 # Number of instructions simulated
13sim_ops 788730743 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 18593984 # Number of bytes read from this memory
17system.physmem.bytes_read::total 18593984 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 165056 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 165056 # Number of instructions bytes read from this memory
20system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
21system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
22system.physmem.num_reads::cpu.inst 290531 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 290531 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 34572458 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 34572458 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 306895 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 306895 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_write::writebacks 7865496 # Write bandwidth from this memory (bytes/s)
31system.physmem.bw_write::total 7865496 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_total::writebacks 7865496 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.bw_total::cpu.inst 34572458 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::total 42437954 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.readReqs 290531 # Number of read requests accepted
36system.physmem.writeReqs 66098 # Number of write requests accepted
37system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue
38system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue

39system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM
40system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
41system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM

39system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM
40system.physmem.bytesReadWrQ 19200 # Total number of bytes read from write queue
41system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM

42system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side
43system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side

44system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue

44system.physmem.servicedByWrQ 300 # Number of DRAM read bursts serviced by the write queue

45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write

47system.physmem.perBankRdBursts::0 18283 # Per bank write bursts
48system.physmem.perBankRdBursts::1 18133 # Per bank write bursts

47system.physmem.perBankRdBursts::0 18291 # Per bank write bursts
48system.physmem.perBankRdBursts::1 18140 # Per bank write bursts

49system.physmem.perBankRdBursts::2 18223 # Per bank write bursts

50system.physmem.perBankRdBursts::3 18187 # Per bank write bursts
51system.physmem.perBankRdBursts::4 18258 # Per bank write bursts
52system.physmem.perBankRdBursts::5 18313 # Per bank write bursts
53system.physmem.perBankRdBursts::6 18090 # Per bank write bursts
54system.physmem.perBankRdBursts::7 17910 # Per bank write bursts
55system.physmem.perBankRdBursts::8 17943 # Per bank write bursts
56system.physmem.perBankRdBursts::9 17966 # Per bank write bursts
57system.physmem.perBankRdBursts::10 18023 # Per bank write bursts
58system.physmem.perBankRdBursts::11 18118 # Per bank write bursts
59system.physmem.perBankRdBursts::12 18159 # Per bank write bursts
60system.physmem.perBankRdBursts::13 18277 # Per bank write bursts
61system.physmem.perBankRdBursts::14 18081 # Per bank write bursts
62system.physmem.perBankRdBursts::15 18260 # Per bank write bursts

50system.physmem.perBankRdBursts::3 18183 # Per bank write bursts
51system.physmem.perBankRdBursts::4 18268 # Per bank write bursts
52system.physmem.perBankRdBursts::5 18315 # Per bank write bursts
53system.physmem.perBankRdBursts::6 18099 # Per bank write bursts
54system.physmem.perBankRdBursts::7 17920 # Per bank write bursts
55system.physmem.perBankRdBursts::8 17939 # Per bank write bursts
56system.physmem.perBankRdBursts::9 17964 # Per bank write bursts
57system.physmem.perBankRdBursts::10 18020 # Per bank write bursts
58system.physmem.perBankRdBursts::11 18110 # Per bank write bursts
59system.physmem.perBankRdBursts::12 18148 # Per bank write bursts
60system.physmem.perBankRdBursts::13 18270 # Per bank write bursts
61system.physmem.perBankRdBursts::14 18079 # Per bank write bursts
62system.physmem.perBankRdBursts::15 18262 # Per bank write bursts

63system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
64system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
65system.physmem.perBankWrBursts::2 4137 # Per bank write bursts
66system.physmem.perBankWrBursts::3 4147 # Per bank write bursts
67system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
68system.physmem.perBankWrBursts::5 4225 # Per bank write bursts
69system.physmem.perBankWrBursts::6 4171 # Per bank write bursts

70system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
71system.physmem.perBankWrBursts::8 4096 # Per bank write bursts

70system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
71system.physmem.perBankWrBursts::8 4093 # Per bank write bursts

72system.physmem.perBankWrBursts::9 4093 # Per bank write bursts

73system.physmem.perBankWrBursts::10 4094 # Per bank write bursts
74system.physmem.perBankWrBursts::11 4097 # Per bank write bursts

73system.physmem.perBankWrBursts::10 4091 # Per bank write bursts
74system.physmem.perBankWrBursts::11 4094 # Per bank write bursts

75system.physmem.perBankWrBursts::12 4098 # Per bank write bursts

76system.physmem.perBankWrBursts::13 4096 # Per bank write bursts

76system.physmem.perBankWrBursts::13 4094 # Per bank write bursts

77system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
78system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
81system.physmem.totGap 537826410500 # Total gap between requests
82system.physmem.readPktSize::0 0 # Read request sizes (log2)
83system.physmem.readPktSize::1 0 # Read request sizes (log2)
84system.physmem.readPktSize::2 0 # Read request sizes (log2)
85system.physmem.readPktSize::3 0 # Read request sizes (log2)
86system.physmem.readPktSize::4 0 # Read request sizes (log2)
87system.physmem.readPktSize::5 0 # Read request sizes (log2)
88system.physmem.readPktSize::6 290531 # Read request sizes (log2)
89system.physmem.writePktSize::0 0 # Write request sizes (log2)
90system.physmem.writePktSize::1 0 # Write request sizes (log2)
91system.physmem.writePktSize::2 0 # Write request sizes (log2)
92system.physmem.writePktSize::3 0 # Write request sizes (log2)
93system.physmem.writePktSize::4 0 # Write request sizes (log2)
94system.physmem.writePktSize::5 0 # Write request sizes (log2)
95system.physmem.writePktSize::6 66098 # Write request sizes (log2)

96system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see

96system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see

97system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
128system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see

143system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see

143system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see

145system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::20 4008 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see

152system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see

152system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see

161system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see

192system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation
206system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes
207system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes
208system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes
209system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes
210system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes

192system.physmem.bytesPerActivate::samples 111650 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::mean 204.222194 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::gmean 132.352958 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::stdev 255.940958 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::0-127 47308 42.37% 42.37% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::128-255 43452 38.92% 81.29% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::256-383 8609 7.71% 89.00% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::384-511 837 0.75% 89.75% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::512-639 1286 1.15% 90.90% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::640-767 1285 1.15% 92.05% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::768-895 530 0.47% 92.53% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::896-1023 473 0.42% 92.95% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::total 111650 # Bytes accessed per row activation
206system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes
207system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes
208system.physmem.rdPerTurnAround::gmean 36.062915 # Reads before turning the bus around for writes
209system.physmem.rdPerTurnAround::stdev 507.683026 # Reads before turning the bus around for writes
210system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes

211system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes

214system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes
215system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads
216system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads
217system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads
218system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads
224system.physmem.totQLat 3341298000 # Total ticks spent queuing
225system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM
226system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers
227system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst

214system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes
215system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads
216system.physmem.wrPerTurnAround::mean 16.489643 # Writes before turning the bus around for reads
217system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads
218system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::17 3 0.07% 75.57% # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::18 978 24.41% 99.98% # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads
224system.physmem.totQLat 3341982750 # Total ticks spent queuing
225system.physmem.totMemAccLat 8783814000 # Total ticks spent from burst creation until serviced by the DRAM
226system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers
227system.physmem.avgQLat 11514.91 # Average queueing delay per DRAM burst

228system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

229system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst

229system.physmem.avgMemAccLat 30264.91 # Average memory access latency per DRAM burst

230system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s
231system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s
232system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s
233system.physmem.avgWrBWSys 7.87 # Average system write bandwidth in MiByte/s
234system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
235system.physmem.busUtil 0.33 # Data bus utilization in percentage
236system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads
237system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
238system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing

239system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing
240system.physmem.readRowHits 194846 # Number of row buffer hits during reads
241system.physmem.writeRowHits 49995 # Number of row buffer hits during writes
242system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads
243system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes

239system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing
240system.physmem.readRowHits 194589 # Number of row buffer hits during reads
241system.physmem.writeRowHits 50052 # Number of row buffer hits during writes
242system.physmem.readRowHitRate 67.05 # Row buffer hit rate for reads
243system.physmem.writeRowHitRate 75.72 # Row buffer hit rate for writes

244system.physmem.avgGap 1508083.78 # Average gap between requests

245system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined
246system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states

245system.physmem.pageHitRate 68.66 # Row buffer hit rate, read and write combined
246system.physmem.memoryStateTime::IDLE 253474796750 # Time in different power states

247system.physmem.memoryStateTime::REF 17958980000 # Time in different power states
248system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states

249system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states

249system.physmem.memoryStateTime::ACT 266386143250 # Time in different power states

250system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states

251system.membus.throughput 42437954 # Throughput (bytes/s)

252system.membus.trans_dist::ReadReq 224439 # Transaction distribution
253system.membus.trans_dist::ReadResp 224439 # Transaction distribution
254system.membus.trans_dist::Writeback 66098 # Transaction distribution
255system.membus.trans_dist::ReadExReq 66092 # Transaction distribution
256system.membus.trans_dist::ReadExResp 66092 # Transaction distribution
257system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes)
258system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes)

251system.membus.trans_dist::ReadReq 224439 # Transaction distribution
252system.membus.trans_dist::ReadResp 224439 # Transaction distribution
253system.membus.trans_dist::Writeback 66098 # Transaction distribution
254system.membus.trans_dist::ReadExReq 66092 # Transaction distribution
255system.membus.trans_dist::ReadExResp 66092 # Transaction distribution
256system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes)
257system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes)

259system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes)
260system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes)
261system.membus.data_through_bus 22824256 # Total data (bytes)
262system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
263system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks)

258system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes)
259system.membus.pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes)
260system.membus.snoops 0 # Total snoops (count)
261system.membus.snoop_fanout::samples 356629 # Request fanout histogram
262system.membus.snoop_fanout::mean 0 # Request fanout histogram
263system.membus.snoop_fanout::stdev 0 # Request fanout histogram
264system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
265system.membus.snoop_fanout::0 356629 100.00% 100.00% # Request fanout histogram
266system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
267system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
268system.membus.snoop_fanout::min_value 0 # Request fanout histogram
269system.membus.snoop_fanout::max_value 0 # Request fanout histogram
270system.membus.snoop_fanout::total 356629 # Request fanout histogram
271system.membus.reqLayer0.occupancy 974401000 # Layer occupancy (ticks)

264system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)

272system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)

265system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks)

273system.membus.respLayer1.occupancy 2738560500 # Layer occupancy (ticks)

266system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
267system.cpu_clk_domain.clock 500 # Clock period in ticks
268system.cpu.branchPred.lookups 154837020 # Number of BP lookups
269system.cpu.branchPred.condPredicted 104970668 # Number of conditional branches predicted
270system.cpu.branchPred.condIncorrect 12892448 # Number of conditional branches incorrect
271system.cpu.branchPred.BTBLookups 106220966 # Number of BTB lookups
272system.cpu.branchPred.BTBHits 82647169 # Number of BTB hits
273system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
274system.cpu.branchPred.BTBHitPct 77.806832 # BTB Hit Percentage
275system.cpu.branchPred.usedRAS 19441660 # Number of times the RAS was used to get a target.
276system.cpu.branchPred.RASInCorrect 1323 # Number of incorrect RAS predictions.
277system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
278system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
279system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
280system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
281system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
282system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
285system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
286system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
287system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
288system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
289system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
290system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
291system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
292system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
293system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
294system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
295system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
296system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
297system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
298system.cpu.dtb.inst_hits 0 # ITB inst hits
299system.cpu.dtb.inst_misses 0 # ITB inst misses
300system.cpu.dtb.read_hits 0 # DTB read hits
301system.cpu.dtb.read_misses 0 # DTB read misses
302system.cpu.dtb.write_hits 0 # DTB write hits
303system.cpu.dtb.write_misses 0 # DTB write misses
304system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
305system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
306system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
307system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
308system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
309system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
310system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
311system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
312system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
313system.cpu.dtb.read_accesses 0 # DTB read accesses
314system.cpu.dtb.write_accesses 0 # DTB write accesses
315system.cpu.dtb.inst_accesses 0 # ITB inst accesses
316system.cpu.dtb.hits 0 # DTB hits
317system.cpu.dtb.misses 0 # DTB misses
318system.cpu.dtb.accesses 0 # DTB accesses
319system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
320system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
321system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
322system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
323system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
324system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
325system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
326system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
327system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
328system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
329system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
330system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
331system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
332system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
333system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
334system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
335system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
336system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
337system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
338system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
339system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
340system.cpu.itb.inst_hits 0 # ITB inst hits
341system.cpu.itb.inst_misses 0 # ITB inst misses
342system.cpu.itb.read_hits 0 # DTB read hits
343system.cpu.itb.read_misses 0 # DTB read misses
344system.cpu.itb.write_hits 0 # DTB write hits
345system.cpu.itb.write_misses 0 # DTB write misses
346system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
347system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
348system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
349system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
350system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
351system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
352system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
353system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
354system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
355system.cpu.itb.read_accesses 0 # DTB read accesses
356system.cpu.itb.write_accesses 0 # DTB write accesses
357system.cpu.itb.inst_accesses 0 # ITB inst accesses
358system.cpu.itb.hits 0 # DTB hits
359system.cpu.itb.misses 0 # DTB misses
360system.cpu.itb.accesses 0 # DTB accesses
361system.cpu.workload.num_syscalls 673 # Number of system calls
362system.cpu.numCycles 1075652997 # number of cpu cycles simulated
363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
364system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
365system.cpu.committedInsts 640655084 # Number of instructions committed
366system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed
367system.cpu.discardedOps 25219021 # Number of ops (including micro ops) which were discarded before commit
368system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
369system.cpu.cpi 1.678989 # CPI: cycles per instruction
370system.cpu.ipc 0.595596 # IPC: instructions per cycle

274system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
275system.cpu_clk_domain.clock 500 # Clock period in ticks
276system.cpu.branchPred.lookups 154837020 # Number of BP lookups
277system.cpu.branchPred.condPredicted 104970668 # Number of conditional branches predicted
278system.cpu.branchPred.condIncorrect 12892448 # Number of conditional branches incorrect
279system.cpu.branchPred.BTBLookups 106220966 # Number of BTB lookups
280system.cpu.branchPred.BTBHits 82647169 # Number of BTB hits
281system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
282system.cpu.branchPred.BTBHitPct 77.806832 # BTB Hit Percentage
283system.cpu.branchPred.usedRAS 19441660 # Number of times the RAS was used to get a target.
284system.cpu.branchPred.RASInCorrect 1323 # Number of incorrect RAS predictions.
285system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
286system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
287system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
288system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
289system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
290system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
291system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
292system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
293system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
294system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
295system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
296system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
297system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
298system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
299system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
300system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
301system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
302system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
303system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
304system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
305system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
306system.cpu.dtb.inst_hits 0 # ITB inst hits
307system.cpu.dtb.inst_misses 0 # ITB inst misses
308system.cpu.dtb.read_hits 0 # DTB read hits
309system.cpu.dtb.read_misses 0 # DTB read misses
310system.cpu.dtb.write_hits 0 # DTB write hits
311system.cpu.dtb.write_misses 0 # DTB write misses
312system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
313system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
314system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
315system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
316system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
317system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
318system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
319system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
320system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
321system.cpu.dtb.read_accesses 0 # DTB read accesses
322system.cpu.dtb.write_accesses 0 # DTB write accesses
323system.cpu.dtb.inst_accesses 0 # ITB inst accesses
324system.cpu.dtb.hits 0 # DTB hits
325system.cpu.dtb.misses 0 # DTB misses
326system.cpu.dtb.accesses 0 # DTB accesses
327system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
328system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
329system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
330system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
331system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
332system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
333system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
334system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
335system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
336system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
337system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
338system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
339system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
340system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
341system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
342system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
343system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
344system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
345system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
346system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
347system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
348system.cpu.itb.inst_hits 0 # ITB inst hits
349system.cpu.itb.inst_misses 0 # ITB inst misses
350system.cpu.itb.read_hits 0 # DTB read hits
351system.cpu.itb.read_misses 0 # DTB read misses
352system.cpu.itb.write_hits 0 # DTB write hits
353system.cpu.itb.write_misses 0 # DTB write misses
354system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
355system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
356system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
357system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
358system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
359system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
360system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
361system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
362system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
363system.cpu.itb.read_accesses 0 # DTB read accesses
364system.cpu.itb.write_accesses 0 # DTB write accesses
365system.cpu.itb.inst_accesses 0 # ITB inst accesses
366system.cpu.itb.hits 0 # DTB hits
367system.cpu.itb.misses 0 # DTB misses
368system.cpu.itb.accesses 0 # DTB accesses
369system.cpu.workload.num_syscalls 673 # Number of system calls
370system.cpu.numCycles 1075652997 # number of cpu cycles simulated
371system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
372system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
373system.cpu.committedInsts 640655084 # Number of instructions committed
374system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed
375system.cpu.discardedOps 25219021 # Number of ops (including micro ops) which were discarded before commit
376system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
377system.cpu.cpi 1.678989 # CPI: cycles per instruction
378system.cpu.ipc 0.595596 # IPC: instructions per cycle

371system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked
372system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped

379system.cpu.tickCycles 1020176456 # Number of cycles that the object actually ticked
380system.cpu.idleCycles 55476541 # Total number of cycles that the object has spent stopped

373system.cpu.icache.tags.replacements 23597 # number of replacements

381system.cpu.icache.tags.replacements 23597 # number of replacements

374system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use

382system.cpu.icache.tags.tagsinuse 1711.183580 # Cycle average of tags in use

375system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks.
376system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks.
377system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks.
378system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

383system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks.
384system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks.
385system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks.
386system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

379system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor
380system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy
381system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy

387system.cpu.icache.tags.occ_blocks::cpu.inst 1711.183580 # Average occupied blocks per requestor
388system.cpu.icache.tags.occ_percent::cpu.inst 0.835539 # Average percentage of cache occupancy
389system.cpu.icache.tags.occ_percent::total 0.835539 # Average percentage of cache occupancy

382system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id
383system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
384system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
385system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id
386system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id
387system.cpu.icache.tags.tag_accesses 580074571 # Number of tag accesses
388system.cpu.icache.tags.data_accesses 580074571 # Number of data accesses
389system.cpu.icache.ReadReq_hits::cpu.inst 289999264 # number of ReadReq hits
390system.cpu.icache.ReadReq_hits::total 289999264 # number of ReadReq hits
391system.cpu.icache.demand_hits::cpu.inst 289999264 # number of demand (read+write) hits
392system.cpu.icache.demand_hits::total 289999264 # number of demand (read+write) hits
393system.cpu.icache.overall_hits::cpu.inst 289999264 # number of overall hits
394system.cpu.icache.overall_hits::total 289999264 # number of overall hits
395system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses
396system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses
397system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses
398system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses
399system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses
400system.cpu.icache.overall_misses::total 25348 # number of overall misses

390system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id
391system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
392system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
393system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id
394system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id
395system.cpu.icache.tags.tag_accesses 580074571 # Number of tag accesses
396system.cpu.icache.tags.data_accesses 580074571 # Number of data accesses
397system.cpu.icache.ReadReq_hits::cpu.inst 289999264 # number of ReadReq hits
398system.cpu.icache.ReadReq_hits::total 289999264 # number of ReadReq hits
399system.cpu.icache.demand_hits::cpu.inst 289999264 # number of demand (read+write) hits
400system.cpu.icache.demand_hits::total 289999264 # number of demand (read+write) hits
401system.cpu.icache.overall_hits::cpu.inst 289999264 # number of overall hits
402system.cpu.icache.overall_hits::total 289999264 # number of overall hits
403system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses
404system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses
405system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses
406system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses
407system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses
408system.cpu.icache.overall_misses::total 25348 # number of overall misses

401system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles
402system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles
403system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles
404system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles
405system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles
406system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles

409system.cpu.icache.ReadReq_miss_latency::cpu.inst 480691746 # number of ReadReq miss cycles
410system.cpu.icache.ReadReq_miss_latency::total 480691746 # number of ReadReq miss cycles
411system.cpu.icache.demand_miss_latency::cpu.inst 480691746 # number of demand (read+write) miss cycles
412system.cpu.icache.demand_miss_latency::total 480691746 # number of demand (read+write) miss cycles
413system.cpu.icache.overall_miss_latency::cpu.inst 480691746 # number of overall miss cycles
414system.cpu.icache.overall_miss_latency::total 480691746 # number of overall miss cycles

407system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses)
408system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses)
409system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses
410system.cpu.icache.demand_accesses::total 290024612 # number of demand (read+write) accesses
411system.cpu.icache.overall_accesses::cpu.inst 290024612 # number of overall (read+write) accesses
412system.cpu.icache.overall_accesses::total 290024612 # number of overall (read+write) accesses
413system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses
414system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses
415system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses
416system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses
417system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
418system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses

415system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses)
416system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses)
417system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses
418system.cpu.icache.demand_accesses::total 290024612 # number of demand (read+write) accesses
419system.cpu.icache.overall_accesses::cpu.inst 290024612 # number of overall (read+write) accesses
420system.cpu.icache.overall_accesses::total 290024612 # number of overall (read+write) accesses
421system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses
422system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses
423system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses
424system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses
425system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
426system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses

419system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency
420system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency
421system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
422system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency
423system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
424system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency

427system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18963.695203 # average ReadReq miss latency
428system.cpu.icache.ReadReq_avg_miss_latency::total 18963.695203 # average ReadReq miss latency
429system.cpu.icache.demand_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency
430system.cpu.icache.demand_avg_miss_latency::total 18963.695203 # average overall miss latency
431system.cpu.icache.overall_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency
432system.cpu.icache.overall_avg_miss_latency::total 18963.695203 # average overall miss latency

425system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
426system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
427system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
428system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
429system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
430system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
431system.cpu.icache.fast_writes 0 # number of fast writes performed
432system.cpu.icache.cache_copies 0 # number of cache copies performed
433system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses
434system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses
435system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses
436system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses
437system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses
438system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses

433system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
434system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
435system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
436system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
437system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
438system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
439system.cpu.icache.fast_writes 0 # number of fast writes performed
440system.cpu.icache.cache_copies 0 # number of cache copies performed
441system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses
442system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses
443system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses
444system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses
445system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses
446system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses

439system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles
440system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles
441system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles
442system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles
443system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles
444system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles

447system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428895254 # number of ReadReq MSHR miss cycles
448system.cpu.icache.ReadReq_mshr_miss_latency::total 428895254 # number of ReadReq MSHR miss cycles
449system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428895254 # number of demand (read+write) MSHR miss cycles
450system.cpu.icache.demand_mshr_miss_latency::total 428895254 # number of demand (read+write) MSHR miss cycles
451system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428895254 # number of overall MSHR miss cycles
452system.cpu.icache.overall_mshr_miss_latency::total 428895254 # number of overall MSHR miss cycles

445system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
446system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
447system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
448system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
449system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
450system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses

453system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
454system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
455system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
456system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
457system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
458system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses

451system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633 # average ReadReq mshr miss latency
452system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633 # average ReadReq mshr miss latency
453system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency
454system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency
455system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency
456system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency

459system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16920.279864 # average ReadReq mshr miss latency
460system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16920.279864 # average ReadReq mshr miss latency
461system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency
462system.cpu.icache.demand_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency
463system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency
464system.cpu.icache.overall_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency

457system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

465system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

458system.cpu.toL2Bus.throughput 107000990 # Throughput (bytes/s)

459system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution
460system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution
461system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
463system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
464system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes)
465system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes)
466system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes)

466system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution
467system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution
468system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution
469system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
470system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
471system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes)
472system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes)
473system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes)

467system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
468system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes)
469system.cpu.toL2Bus.tot_pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes)
470system.cpu.toL2Bus.data_through_bus 57547968 # Total data (bytes)
471system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)

474system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
475system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes)
476system.cpu.toL2Bus.pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes)
477system.cpu.toL2Bus.snoops 0 # Total snoops (count)
478system.cpu.toL2Bus.snoop_fanout::samples 899188 # Request fanout histogram
479system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
482system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
483system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
484system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
485system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
486system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
487system.cpu.toL2Bus.snoop_fanout::5 899188 100.00% 100.00% # Request fanout histogram
488system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
489system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
490system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
491system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
492system.cpu.toL2Bus.snoop_fanout::total 899188 # Request fanout histogram

472system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks)
473system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)

493system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks)
494system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)

474system.cpu.toL2Bus.respLayer0.occupancy 38572246 # Layer occupancy (ticks)

495system.cpu.toL2Bus.respLayer0.occupancy 38571746 # Layer occupancy (ticks)

475system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)

496system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)

476system.cpu.toL2Bus.respLayer1.occupancy 1224995475 # Layer occupancy (ticks)

497system.cpu.toL2Bus.respLayer1.occupancy 1224928725 # Layer occupancy (ticks)

477system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
478system.cpu.l2cache.tags.replacements 257750 # number of replacements

498system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
499system.cpu.l2cache.tags.replacements 257750 # number of replacements

479system.cpu.l2cache.tags.tagsinuse 32582.970291 # Cycle average of tags in use

500system.cpu.l2cache.tags.tagsinuse 32583.011088 # Cycle average of tags in use

480system.cpu.l2cache.tags.total_refs 539180 # Total number of references to valid blocks.
481system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks.
482system.cpu.l2cache.tags.avg_refs 1.856080 # Average number of references to valid blocks.
483system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

501system.cpu.l2cache.tags.total_refs 539180 # Total number of references to valid blocks.
502system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks.
503system.cpu.l2cache.tags.avg_refs 1.856080 # Average number of references to valid blocks.
504system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

484system.cpu.l2cache.tags.occ_blocks::writebacks 2866.246405 # Average occupied blocks per requestor
485system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886 # Average occupied blocks per requestor
486system.cpu.l2cache.tags.occ_percent::writebacks 0.087471 # Average percentage of cache occupancy
487system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906882 # Average percentage of cache occupancy
488system.cpu.l2cache.tags.occ_percent::total 0.994353 # Average percentage of cache occupancy

505system.cpu.l2cache.tags.occ_blocks::writebacks 2866.114553 # Average occupied blocks per requestor
506system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.896535 # Average occupied blocks per requestor
507system.cpu.l2cache.tags.occ_percent::writebacks 0.087467 # Average percentage of cache occupancy
508system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906888 # Average percentage of cache occupancy
509system.cpu.l2cache.tags.occ_percent::total 0.994355 # Average percentage of cache occupancy

489system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id
490system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
491system.cpu.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id
492system.cpu.l2cache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id
493system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2831 # Occupied blocks per task id
494system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29389 # Occupied blocks per task id
495system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
496system.cpu.l2cache.tags.tag_accesses 7553321 # Number of tag accesses
497system.cpu.l2cache.tags.data_accesses 7553321 # Number of data accesses
498system.cpu.l2cache.ReadReq_hits::cpu.inst 513976 # number of ReadReq hits
499system.cpu.l2cache.ReadReq_hits::total 513976 # number of ReadReq hits
500system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits
501system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits
502system.cpu.l2cache.ReadExReq_hits::cpu.inst 3231 # number of ReadExReq hits
503system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
504system.cpu.l2cache.demand_hits::cpu.inst 517207 # number of demand (read+write) hits
505system.cpu.l2cache.demand_hits::total 517207 # number of demand (read+write) hits
506system.cpu.l2cache.overall_hits::cpu.inst 517207 # number of overall hits
507system.cpu.l2cache.overall_hits::total 517207 # number of overall hits
508system.cpu.l2cache.ReadReq_misses::cpu.inst 224469 # number of ReadReq misses
509system.cpu.l2cache.ReadReq_misses::total 224469 # number of ReadReq misses
510system.cpu.l2cache.ReadExReq_misses::cpu.inst 66092 # number of ReadExReq misses
511system.cpu.l2cache.ReadExReq_misses::total 66092 # number of ReadExReq misses
512system.cpu.l2cache.demand_misses::cpu.inst 290561 # number of demand (read+write) misses
513system.cpu.l2cache.demand_misses::total 290561 # number of demand (read+write) misses
514system.cpu.l2cache.overall_misses::cpu.inst 290561 # number of overall misses
515system.cpu.l2cache.overall_misses::total 290561 # number of overall misses

510system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id
511system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
512system.cpu.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id
513system.cpu.l2cache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id
514system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2831 # Occupied blocks per task id
515system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29389 # Occupied blocks per task id
516system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
517system.cpu.l2cache.tags.tag_accesses 7553321 # Number of tag accesses
518system.cpu.l2cache.tags.data_accesses 7553321 # Number of data accesses
519system.cpu.l2cache.ReadReq_hits::cpu.inst 513976 # number of ReadReq hits
520system.cpu.l2cache.ReadReq_hits::total 513976 # number of ReadReq hits
521system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits
522system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits
523system.cpu.l2cache.ReadExReq_hits::cpu.inst 3231 # number of ReadExReq hits
524system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
525system.cpu.l2cache.demand_hits::cpu.inst 517207 # number of demand (read+write) hits
526system.cpu.l2cache.demand_hits::total 517207 # number of demand (read+write) hits
527system.cpu.l2cache.overall_hits::cpu.inst 517207 # number of overall hits
528system.cpu.l2cache.overall_hits::total 517207 # number of overall hits
529system.cpu.l2cache.ReadReq_misses::cpu.inst 224469 # number of ReadReq misses
530system.cpu.l2cache.ReadReq_misses::total 224469 # number of ReadReq misses
531system.cpu.l2cache.ReadExReq_misses::cpu.inst 66092 # number of ReadExReq misses
532system.cpu.l2cache.ReadExReq_misses::total 66092 # number of ReadExReq misses
533system.cpu.l2cache.demand_misses::cpu.inst 290561 # number of demand (read+write) misses
534system.cpu.l2cache.demand_misses::total 290561 # number of demand (read+write) misses
535system.cpu.l2cache.overall_misses::cpu.inst 290561 # number of overall misses
536system.cpu.l2cache.overall_misses::total 290561 # number of overall misses

516system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16737523000 # number of ReadReq miss cycles
517system.cpu.l2cache.ReadReq_miss_latency::total 16737523000 # number of ReadReq miss cycles
518system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4423362750 # number of ReadExReq miss cycles
519system.cpu.l2cache.ReadExReq_miss_latency::total 4423362750 # number of ReadExReq miss cycles
520system.cpu.l2cache.demand_miss_latency::cpu.inst 21160885750 # number of demand (read+write) miss cycles
521system.cpu.l2cache.demand_miss_latency::total 21160885750 # number of demand (read+write) miss cycles
522system.cpu.l2cache.overall_miss_latency::cpu.inst 21160885750 # number of overall miss cycles
523system.cpu.l2cache.overall_miss_latency::total 21160885750 # number of overall miss cycles

537system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16739408750 # number of ReadReq miss cycles
538system.cpu.l2cache.ReadReq_miss_latency::total 16739408750 # number of ReadReq miss cycles
539system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4422117750 # number of ReadExReq miss cycles
540system.cpu.l2cache.ReadExReq_miss_latency::total 4422117750 # number of ReadExReq miss cycles
541system.cpu.l2cache.demand_miss_latency::cpu.inst 21161526500 # number of demand (read+write) miss cycles
542system.cpu.l2cache.demand_miss_latency::total 21161526500 # number of demand (read+write) miss cycles
543system.cpu.l2cache.overall_miss_latency::cpu.inst 21161526500 # number of overall miss cycles
544system.cpu.l2cache.overall_miss_latency::total 21161526500 # number of overall miss cycles

524system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses)
525system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses)
526system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses)
527system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses)
528system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69323 # number of ReadExReq accesses(hits+misses)
529system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses)
530system.cpu.l2cache.demand_accesses::cpu.inst 807768 # number of demand (read+write) accesses
531system.cpu.l2cache.demand_accesses::total 807768 # number of demand (read+write) accesses
532system.cpu.l2cache.overall_accesses::cpu.inst 807768 # number of overall (read+write) accesses
533system.cpu.l2cache.overall_accesses::total 807768 # number of overall (read+write) accesses
534system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.303975 # miss rate for ReadReq accesses
535system.cpu.l2cache.ReadReq_miss_rate::total 0.303975 # miss rate for ReadReq accesses
536system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953392 # miss rate for ReadExReq accesses
537system.cpu.l2cache.ReadExReq_miss_rate::total 0.953392 # miss rate for ReadExReq accesses
538system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359708 # miss rate for demand accesses
539system.cpu.l2cache.demand_miss_rate::total 0.359708 # miss rate for demand accesses
540system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359708 # miss rate for overall accesses
541system.cpu.l2cache.overall_miss_rate::total 0.359708 # miss rate for overall accesses

545system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses)
546system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses)
547system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses)
548system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses)
549system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69323 # number of ReadExReq accesses(hits+misses)
550system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses)
551system.cpu.l2cache.demand_accesses::cpu.inst 807768 # number of demand (read+write) accesses
552system.cpu.l2cache.demand_accesses::total 807768 # number of demand (read+write) accesses
553system.cpu.l2cache.overall_accesses::cpu.inst 807768 # number of overall (read+write) accesses
554system.cpu.l2cache.overall_accesses::total 807768 # number of overall (read+write) accesses
555system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.303975 # miss rate for ReadReq accesses
556system.cpu.l2cache.ReadReq_miss_rate::total 0.303975 # miss rate for ReadReq accesses
557system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953392 # miss rate for ReadExReq accesses
558system.cpu.l2cache.ReadExReq_miss_rate::total 0.953392 # miss rate for ReadExReq accesses
559system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359708 # miss rate for demand accesses
560system.cpu.l2cache.demand_miss_rate::total 0.359708 # miss rate for demand accesses
561system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359708 # miss rate for overall accesses
562system.cpu.l2cache.overall_miss_rate::total 0.359708 # miss rate for overall accesses

542system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.964427 # average ReadReq miss latency
543system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427 # average ReadReq miss latency
544system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051 # average ReadExReq miss latency
545system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051 # average ReadExReq miss latency
546system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency
547system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646 # average overall miss latency
548system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency
549system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646 # average overall miss latency

563system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74573.365364 # average ReadReq miss latency
564system.cpu.l2cache.ReadReq_avg_miss_latency::total 74573.365364 # average ReadReq miss latency
565system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66908.517672 # average ReadExReq miss latency
566system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66908.517672 # average ReadExReq miss latency
567system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency
568system.cpu.l2cache.demand_avg_miss_latency::total 72829.892862 # average overall miss latency
569system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency
570system.cpu.l2cache.overall_avg_miss_latency::total 72829.892862 # average overall miss latency

550system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
551system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
552system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
553system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
554system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
555system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
556system.cpu.l2cache.fast_writes 0 # number of fast writes performed
557system.cpu.l2cache.cache_copies 0 # number of cache copies performed
558system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
559system.cpu.l2cache.writebacks::total 66098 # number of writebacks
560system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 29 # number of ReadReq MSHR hits
561system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits
562system.cpu.l2cache.demand_mshr_hits::cpu.inst 29 # number of demand (read+write) MSHR hits
563system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits
564system.cpu.l2cache.overall_mshr_hits::cpu.inst 29 # number of overall MSHR hits
565system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits
566system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224440 # number of ReadReq MSHR misses
567system.cpu.l2cache.ReadReq_mshr_misses::total 224440 # number of ReadReq MSHR misses
568system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66092 # number of ReadExReq MSHR misses
569system.cpu.l2cache.ReadExReq_mshr_misses::total 66092 # number of ReadExReq MSHR misses
570system.cpu.l2cache.demand_mshr_misses::cpu.inst 290532 # number of demand (read+write) MSHR misses
571system.cpu.l2cache.demand_mshr_misses::total 290532 # number of demand (read+write) MSHR misses
572system.cpu.l2cache.overall_mshr_misses::cpu.inst 290532 # number of overall MSHR misses
573system.cpu.l2cache.overall_mshr_misses::total 290532 # number of overall MSHR misses

571system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
572system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
573system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
574system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
575system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
576system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
577system.cpu.l2cache.fast_writes 0 # number of fast writes performed
578system.cpu.l2cache.cache_copies 0 # number of cache copies performed
579system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
580system.cpu.l2cache.writebacks::total 66098 # number of writebacks
581system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 29 # number of ReadReq MSHR hits
582system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits
583system.cpu.l2cache.demand_mshr_hits::cpu.inst 29 # number of demand (read+write) MSHR hits
584system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits
585system.cpu.l2cache.overall_mshr_hits::cpu.inst 29 # number of overall MSHR hits
586system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits
587system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224440 # number of ReadReq MSHR misses
588system.cpu.l2cache.ReadReq_mshr_misses::total 224440 # number of ReadReq MSHR misses
589system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66092 # number of ReadExReq MSHR misses
590system.cpu.l2cache.ReadExReq_mshr_misses::total 66092 # number of ReadExReq MSHR misses
591system.cpu.l2cache.demand_mshr_misses::cpu.inst 290532 # number of demand (read+write) MSHR misses
592system.cpu.l2cache.demand_mshr_misses::total 290532 # number of demand (read+write) MSHR misses
593system.cpu.l2cache.overall_mshr_misses::cpu.inst 290532 # number of overall MSHR misses
594system.cpu.l2cache.overall_mshr_misses::total 290532 # number of overall MSHR misses

574system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13902147000 # number of ReadReq MSHR miss cycles
575system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13902147000 # number of ReadReq MSHR miss cycles
576system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3594959250 # number of ReadExReq MSHR miss cycles
577system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3594959250 # number of ReadExReq MSHR miss cycles
578system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497106250 # number of demand (read+write) MSHR miss cycles
579system.cpu.l2cache.demand_mshr_miss_latency::total 17497106250 # number of demand (read+write) MSHR miss cycles
580system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497106250 # number of overall MSHR miss cycles
581system.cpu.l2cache.overall_mshr_miss_latency::total 17497106250 # number of overall MSHR miss cycles

595system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13904175250 # number of ReadReq MSHR miss cycles
596system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13904175250 # number of ReadReq MSHR miss cycles
597system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3593710250 # number of ReadExReq MSHR miss cycles
598system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3593710250 # number of ReadExReq MSHR miss cycles
599system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497885500 # number of demand (read+write) MSHR miss cycles
600system.cpu.l2cache.demand_mshr_miss_latency::total 17497885500 # number of demand (read+write) MSHR miss cycles
601system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497885500 # number of overall MSHR miss cycles
602system.cpu.l2cache.overall_mshr_miss_latency::total 17497885500 # number of overall MSHR miss cycles

582system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303936 # mshr miss rate for ReadReq accesses
583system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303936 # mshr miss rate for ReadReq accesses
584system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953392 # mshr miss rate for ReadExReq accesses
585system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953392 # mshr miss rate for ReadExReq accesses
586system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for demand accesses
587system.cpu.l2cache.demand_mshr_miss_rate::total 0.359673 # mshr miss rate for demand accesses
588system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for overall accesses
589system.cpu.l2cache.overall_mshr_miss_rate::total 0.359673 # mshr miss rate for overall accesses

603system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303936 # mshr miss rate for ReadReq accesses
604system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303936 # mshr miss rate for ReadReq accesses
605system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953392 # mshr miss rate for ReadExReq accesses
606system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953392 # mshr miss rate for ReadExReq accesses
607system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for demand accesses
608system.cpu.l2cache.demand_mshr_miss_rate::total 0.359673 # mshr miss rate for demand accesses
609system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for overall accesses
610system.cpu.l2cache.overall_mshr_miss_rate::total 0.359673 # mshr miss rate for overall accesses

590system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475 # average ReadReq mshr miss latency
591system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475 # average ReadReq mshr miss latency
592system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639 # average ReadExReq mshr miss latency
593system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639 # average ReadExReq mshr miss latency
594system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency
595system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency
596system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency
597system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency

611system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61950.522411 # average ReadReq mshr miss latency
612system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61950.522411 # average ReadReq mshr miss latency
613system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54374.360740 # average ReadExReq mshr miss latency
614system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54374.360740 # average ReadExReq mshr miss latency
615system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency
616system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency
617system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency
618system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency

598system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
599system.cpu.dcache.tags.replacements 778324 # number of replacements
600system.cpu.dcache.tags.tagsinuse 4092.650508 # Cycle average of tags in use
601system.cpu.dcache.tags.total_refs 378453595 # Total number of references to valid blocks.
602system.cpu.dcache.tags.sampled_refs 782420 # Sample count of references to valid blocks.
603system.cpu.dcache.tags.avg_refs 483.696218 # Average number of references to valid blocks.
604system.cpu.dcache.tags.warmup_cycle 745524250 # Cycle when the warmup percentage was hit.
605system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.650508 # Average occupied blocks per requestor
606system.cpu.dcache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy
607system.cpu.dcache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy
608system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
609system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
610system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
611system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id
612system.cpu.dcache.tags.age_task_id_blocks_1024::3 1354 # Occupied blocks per task id
613system.cpu.dcache.tags.age_task_id_blocks_1024::4 1577 # Occupied blocks per task id
614system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
615system.cpu.dcache.tags.tag_accesses 759392478 # Number of tag accesses
616system.cpu.dcache.tags.data_accesses 759392478 # Number of data accesses
617system.cpu.dcache.ReadReq_hits::cpu.inst 249628224 # number of ReadReq hits
618system.cpu.dcache.ReadReq_hits::total 249628224 # number of ReadReq hits
619system.cpu.dcache.WriteReq_hits::cpu.inst 128813893 # number of WriteReq hits
620system.cpu.dcache.WriteReq_hits::total 128813893 # number of WriteReq hits
621system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits
622system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
623system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits
624system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
625system.cpu.dcache.demand_hits::cpu.inst 378442117 # number of demand (read+write) hits
626system.cpu.dcache.demand_hits::total 378442117 # number of demand (read+write) hits
627system.cpu.dcache.overall_hits::cpu.inst 378442117 # number of overall hits
628system.cpu.dcache.overall_hits::total 378442117 # number of overall hits
629system.cpu.dcache.ReadReq_misses::cpu.inst 713850 # number of ReadReq misses
630system.cpu.dcache.ReadReq_misses::total 713850 # number of ReadReq misses
631system.cpu.dcache.WriteReq_misses::cpu.inst 137584 # number of WriteReq misses
632system.cpu.dcache.WriteReq_misses::total 137584 # number of WriteReq misses
633system.cpu.dcache.demand_misses::cpu.inst 851434 # number of demand (read+write) misses
634system.cpu.dcache.demand_misses::total 851434 # number of demand (read+write) misses
635system.cpu.dcache.overall_misses::cpu.inst 851434 # number of overall misses
636system.cpu.dcache.overall_misses::total 851434 # number of overall misses

619system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
620system.cpu.dcache.tags.replacements 778324 # number of replacements
621system.cpu.dcache.tags.tagsinuse 4092.650508 # Cycle average of tags in use
622system.cpu.dcache.tags.total_refs 378453595 # Total number of references to valid blocks.
623system.cpu.dcache.tags.sampled_refs 782420 # Sample count of references to valid blocks.
624system.cpu.dcache.tags.avg_refs 483.696218 # Average number of references to valid blocks.
625system.cpu.dcache.tags.warmup_cycle 745524250 # Cycle when the warmup percentage was hit.
626system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.650508 # Average occupied blocks per requestor
627system.cpu.dcache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy
628system.cpu.dcache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy
629system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
630system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
631system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
632system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id
633system.cpu.dcache.tags.age_task_id_blocks_1024::3 1354 # Occupied blocks per task id
634system.cpu.dcache.tags.age_task_id_blocks_1024::4 1577 # Occupied blocks per task id
635system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
636system.cpu.dcache.tags.tag_accesses 759392478 # Number of tag accesses
637system.cpu.dcache.tags.data_accesses 759392478 # Number of data accesses
638system.cpu.dcache.ReadReq_hits::cpu.inst 249628224 # number of ReadReq hits
639system.cpu.dcache.ReadReq_hits::total 249628224 # number of ReadReq hits
640system.cpu.dcache.WriteReq_hits::cpu.inst 128813893 # number of WriteReq hits
641system.cpu.dcache.WriteReq_hits::total 128813893 # number of WriteReq hits
642system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits
643system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
644system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits
645system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
646system.cpu.dcache.demand_hits::cpu.inst 378442117 # number of demand (read+write) hits
647system.cpu.dcache.demand_hits::total 378442117 # number of demand (read+write) hits
648system.cpu.dcache.overall_hits::cpu.inst 378442117 # number of overall hits
649system.cpu.dcache.overall_hits::total 378442117 # number of overall hits
650system.cpu.dcache.ReadReq_misses::cpu.inst 713850 # number of ReadReq misses
651system.cpu.dcache.ReadReq_misses::total 713850 # number of ReadReq misses
652system.cpu.dcache.WriteReq_misses::cpu.inst 137584 # number of WriteReq misses
653system.cpu.dcache.WriteReq_misses::total 137584 # number of WriteReq misses
654system.cpu.dcache.demand_misses::cpu.inst 851434 # number of demand (read+write) misses
655system.cpu.dcache.demand_misses::total 851434 # number of demand (read+write) misses
656system.cpu.dcache.overall_misses::cpu.inst 851434 # number of overall misses
657system.cpu.dcache.overall_misses::total 851434 # number of overall misses

637system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23698499970 # number of ReadReq miss cycles
638system.cpu.dcache.ReadReq_miss_latency::total 23698499970 # number of ReadReq miss cycles
639system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9186329500 # number of WriteReq miss cycles
640system.cpu.dcache.WriteReq_miss_latency::total 9186329500 # number of WriteReq miss cycles
641system.cpu.dcache.demand_miss_latency::cpu.inst 32884829470 # number of demand (read+write) miss cycles
642system.cpu.dcache.demand_miss_latency::total 32884829470 # number of demand (read+write) miss cycles
643system.cpu.dcache.overall_miss_latency::cpu.inst 32884829470 # number of overall miss cycles
644system.cpu.dcache.overall_miss_latency::total 32884829470 # number of overall miss cycles

658system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23700601220 # number of ReadReq miss cycles
659system.cpu.dcache.ReadReq_miss_latency::total 23700601220 # number of ReadReq miss cycles
660system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9183787250 # number of WriteReq miss cycles
661system.cpu.dcache.WriteReq_miss_latency::total 9183787250 # number of WriteReq miss cycles
662system.cpu.dcache.demand_miss_latency::cpu.inst 32884388470 # number of demand (read+write) miss cycles
663system.cpu.dcache.demand_miss_latency::total 32884388470 # number of demand (read+write) miss cycles
664system.cpu.dcache.overall_miss_latency::cpu.inst 32884388470 # number of overall miss cycles
665system.cpu.dcache.overall_miss_latency::total 32884388470 # number of overall miss cycles

645system.cpu.dcache.ReadReq_accesses::cpu.inst 250342074 # number of ReadReq accesses(hits+misses)
646system.cpu.dcache.ReadReq_accesses::total 250342074 # number of ReadReq accesses(hits+misses)
647system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses)
648system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
649system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses)
650system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
651system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses)
652system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
653system.cpu.dcache.demand_accesses::cpu.inst 379293551 # number of demand (read+write) accesses
654system.cpu.dcache.demand_accesses::total 379293551 # number of demand (read+write) accesses
655system.cpu.dcache.overall_accesses::cpu.inst 379293551 # number of overall (read+write) accesses
656system.cpu.dcache.overall_accesses::total 379293551 # number of overall (read+write) accesses
657system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses
658system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses
659system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001067 # miss rate for WriteReq accesses
660system.cpu.dcache.WriteReq_miss_rate::total 0.001067 # miss rate for WriteReq accesses
661system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses
662system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
663system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses
664system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses

666system.cpu.dcache.ReadReq_accesses::cpu.inst 250342074 # number of ReadReq accesses(hits+misses)
667system.cpu.dcache.ReadReq_accesses::total 250342074 # number of ReadReq accesses(hits+misses)
668system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses)
669system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
670system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses)
671system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
672system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses)
673system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
674system.cpu.dcache.demand_accesses::cpu.inst 379293551 # number of demand (read+write) accesses
675system.cpu.dcache.demand_accesses::total 379293551 # number of demand (read+write) accesses
676system.cpu.dcache.overall_accesses::cpu.inst 379293551 # number of overall (read+write) accesses
677system.cpu.dcache.overall_accesses::total 379293551 # number of overall (read+write) accesses
678system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses
679system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses
680system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001067 # miss rate for WriteReq accesses
681system.cpu.dcache.WriteReq_miss_rate::total 0.001067 # miss rate for WriteReq accesses
682system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses
683system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
684system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses
685system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses

665system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency
666system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency
667system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency
668system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency
669system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency
670system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency
671system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency
672system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency

686system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33201.094376 # average ReadReq miss latency
687system.cpu.dcache.ReadReq_avg_miss_latency::total 33201.094376 # average ReadReq miss latency
688system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66750.401573 # average WriteReq miss latency
689system.cpu.dcache.WriteReq_avg_miss_latency::total 66750.401573 # average WriteReq miss latency
690system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency
691system.cpu.dcache.demand_avg_miss_latency::total 38622.357658 # average overall miss latency
692system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency
693system.cpu.dcache.overall_avg_miss_latency::total 38622.357658 # average overall miss latency

673system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
674system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
675system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
676system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
677system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
678system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
679system.cpu.dcache.fast_writes 0 # number of fast writes performed
680system.cpu.dcache.cache_copies 0 # number of cache copies performed
681system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks
682system.cpu.dcache.writebacks::total 91420 # number of writebacks
683system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 753 # number of ReadReq MSHR hits
684system.cpu.dcache.ReadReq_mshr_hits::total 753 # number of ReadReq MSHR hits
685system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68261 # number of WriteReq MSHR hits
686system.cpu.dcache.WriteReq_mshr_hits::total 68261 # number of WriteReq MSHR hits
687system.cpu.dcache.demand_mshr_hits::cpu.inst 69014 # number of demand (read+write) MSHR hits
688system.cpu.dcache.demand_mshr_hits::total 69014 # number of demand (read+write) MSHR hits
689system.cpu.dcache.overall_mshr_hits::cpu.inst 69014 # number of overall MSHR hits
690system.cpu.dcache.overall_mshr_hits::total 69014 # number of overall MSHR hits
691system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 713097 # number of ReadReq MSHR misses
692system.cpu.dcache.ReadReq_mshr_misses::total 713097 # number of ReadReq MSHR misses
693system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69323 # number of WriteReq MSHR misses
694system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
695system.cpu.dcache.demand_mshr_misses::cpu.inst 782420 # number of demand (read+write) MSHR misses
696system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses
697system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses
698system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses

694system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
695system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
696system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
697system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
698system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
699system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
700system.cpu.dcache.fast_writes 0 # number of fast writes performed
701system.cpu.dcache.cache_copies 0 # number of cache copies performed
702system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks
703system.cpu.dcache.writebacks::total 91420 # number of writebacks
704system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 753 # number of ReadReq MSHR hits
705system.cpu.dcache.ReadReq_mshr_hits::total 753 # number of ReadReq MSHR hits
706system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68261 # number of WriteReq MSHR hits
707system.cpu.dcache.WriteReq_mshr_hits::total 68261 # number of WriteReq MSHR hits
708system.cpu.dcache.demand_mshr_hits::cpu.inst 69014 # number of demand (read+write) MSHR hits
709system.cpu.dcache.demand_mshr_hits::total 69014 # number of demand (read+write) MSHR hits
710system.cpu.dcache.overall_mshr_hits::cpu.inst 69014 # number of overall MSHR hits
711system.cpu.dcache.overall_mshr_hits::total 69014 # number of overall MSHR hits
712system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 713097 # number of ReadReq MSHR misses
713system.cpu.dcache.ReadReq_mshr_misses::total 713097 # number of ReadReq MSHR misses
714system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69323 # number of WriteReq MSHR misses
715system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
716system.cpu.dcache.demand_mshr_misses::cpu.inst 782420 # number of demand (read+write) MSHR misses
717system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses
718system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses
719system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses

699system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles
700system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles
701system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles
702system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles
703system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles
704system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles
705system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles
706system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles

720system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22188801525 # number of ReadReq MSHR miss cycles
721system.cpu.dcache.ReadReq_mshr_miss_latency::total 22188801525 # number of ReadReq MSHR miss cycles
722system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4523752250 # number of WriteReq MSHR miss cycles
723system.cpu.dcache.WriteReq_mshr_miss_latency::total 4523752250 # number of WriteReq MSHR miss cycles
724system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26712553775 # number of demand (read+write) MSHR miss cycles
725system.cpu.dcache.demand_mshr_miss_latency::total 26712553775 # number of demand (read+write) MSHR miss cycles
726system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26712553775 # number of overall MSHR miss cycles
727system.cpu.dcache.overall_mshr_miss_latency::total 26712553775 # number of overall MSHR miss cycles

707system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses
708system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
709system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses
710system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
711system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses
712system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses
713system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses
714system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses

728system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses
729system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
730system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses
731system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
732system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses
733system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses
734system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses
735system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses

715system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency
716system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency
717system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency
718system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency
719system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency
720system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency
721system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency
722system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency

736system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.105558 # average ReadReq mshr miss latency
737system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31116.105558 # average ReadReq mshr miss latency
738system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65256.152359 # average WriteReq mshr miss latency
739system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65256.152359 # average WriteReq mshr miss latency
740system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency
741system.cpu.dcache.demand_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency
742system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency
743system.cpu.dcache.overall_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency