| stats.txt (9079:9a244ebdc3c9) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.525854 # Number of seconds simulated 4sim_ticks 525854423000 # Number of ticks simulated 5final_tick 525854423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.525920 # Number of seconds simulated 4sim_ticks 525920061000 # Number of ticks simulated 5final_tick 525920061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1009014 # Simulator instruction rate (inst/s) 8host_op_rate 1289987 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1945426950 # Simulator tick rate (ticks/s) 10host_mem_usage 241152 # Number of bytes of host memory used 11host_seconds 270.30 # Real time elapsed on the host | 7host_inst_rate 966127 # Simulator instruction rate (inst/s) 8host_op_rate 1235157 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1862970627 # Simulator tick rate (ticks/s) 10host_mem_usage 241076 # Number of bytes of host memory used 11host_seconds 282.30 # Real time elapsed on the host |
| 12sim_insts 272739283 # Number of instructions simulated 13sim_ops 348687122 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 16system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory | 12sim_insts 272739283 # Number of instructions simulated 13sim_ops 348687122 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 16system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 317533 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 513967 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 831500 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 317533 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 317533 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 317533 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 513967 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 831500 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 317493 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 513903 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 831396 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 317493 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 317493 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 317493 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 513903 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 831396 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 191 # Number of system calls | 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 191 # Number of system calls |
| 73system.cpu.numCycles 1051708846 # number of cpu cycles simulated | 73system.cpu.numCycles 1051840122 # number of cpu cycles simulated |
| 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.committedInsts 272739283 # Number of instructions committed 77system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed 78system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses 79system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 80system.cpu.num_func_calls 12448615 # number of times a function call or return occured 81system.cpu.num_conditional_control_insts 18087060 # number of instructions that are conditional controls 82system.cpu.num_int_insts 279584917 # number of integer instructions 83system.cpu.num_fp_insts 114216705 # number of float instructions 84system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read 85system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written 86system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 87system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 88system.cpu.num_mem_refs 177024356 # number of memory refs 89system.cpu.num_load_insts 94648757 # Number of load instructions 90system.cpu.num_store_insts 82375599 # Number of store instructions 91system.cpu.num_idle_cycles 0 # Number of idle cycles | 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.committedInsts 272739283 # Number of instructions committed 77system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed 78system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses 79system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 80system.cpu.num_func_calls 12448615 # number of times a function call or return occured 81system.cpu.num_conditional_control_insts 18087060 # number of instructions that are conditional controls 82system.cpu.num_int_insts 279584917 # number of integer instructions 83system.cpu.num_fp_insts 114216705 # number of float instructions 84system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read 85system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written 86system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 87system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 88system.cpu.num_mem_refs 177024356 # number of memory refs 89system.cpu.num_load_insts 94648757 # Number of load instructions 90system.cpu.num_store_insts 82375599 # Number of store instructions 91system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 92system.cpu.num_busy_cycles 1051708846 # Number of busy cycles | 92system.cpu.num_busy_cycles 1051840122 # Number of busy cycles |
| 93system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 94system.cpu.idle_fraction 0 # Percentage of idle cycles 95system.cpu.icache.replacements 13796 # number of replacements | 93system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 94system.cpu.idle_fraction 0 # Percentage of idle cycles 95system.cpu.icache.replacements 13796 # number of replacements |
| 96system.cpu.icache.tagsinuse 1765.984191 # Cycle average of tags in use | 96system.cpu.icache.tagsinuse 1765.965460 # Cycle average of tags in use |
| 97system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. 98system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. 99system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. 100system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 97system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. 98system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. 99system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. 100system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 101system.cpu.icache.occ_blocks::cpu.inst 1765.984191 # Average occupied blocks per requestor 102system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy 103system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy | 101system.cpu.icache.occ_blocks::cpu.inst 1765.965460 # Average occupied blocks per requestor 102system.cpu.icache.occ_percent::cpu.inst 0.862288 # Average percentage of cache occupancy 103system.cpu.icache.occ_percent::total 0.862288 # Average percentage of cache occupancy |
| 104system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits 105system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits 106system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits 107system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits 108system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits 109system.cpu.icache.overall_hits::total 348644747 # number of overall hits 110system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 111system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 112system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 113system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 114system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 115system.cpu.icache.overall_misses::total 15603 # number of overall misses | 104system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits 105system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits 106system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits 107system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits 108system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits 109system.cpu.icache.overall_hits::total 348644747 # number of overall hits 110system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 111system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 112system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 113system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 114system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 115system.cpu.icache.overall_misses::total 15603 # number of overall misses |
| 116system.cpu.icache.ReadReq_miss_latency::cpu.inst 328020000 # number of ReadReq miss cycles 117system.cpu.icache.ReadReq_miss_latency::total 328020000 # number of ReadReq miss cycles 118system.cpu.icache.demand_miss_latency::cpu.inst 328020000 # number of demand (read+write) miss cycles 119system.cpu.icache.demand_miss_latency::total 328020000 # number of demand (read+write) miss cycles 120system.cpu.icache.overall_miss_latency::cpu.inst 328020000 # number of overall miss cycles 121system.cpu.icache.overall_miss_latency::total 328020000 # number of overall miss cycles | 116system.cpu.icache.ReadReq_miss_latency::cpu.inst 328087000 # number of ReadReq miss cycles 117system.cpu.icache.ReadReq_miss_latency::total 328087000 # number of ReadReq miss cycles 118system.cpu.icache.demand_miss_latency::cpu.inst 328087000 # number of demand (read+write) miss cycles 119system.cpu.icache.demand_miss_latency::total 328087000 # number of demand (read+write) miss cycles 120system.cpu.icache.overall_miss_latency::cpu.inst 328087000 # number of overall miss cycles 121system.cpu.icache.overall_miss_latency::total 328087000 # number of overall miss cycles |
| 122system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) 123system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) 124system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses 125system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses 126system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses 127system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses 128system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 129system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 130system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 131system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 132system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 133system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses | 122system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) 123system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) 124system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses 125system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses 126system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses 127system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses 128system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 129system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 130system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 131system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 132system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 133system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses |
| 134system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21022.880215 # average ReadReq miss latency 135system.cpu.icache.ReadReq_avg_miss_latency::total 21022.880215 # average ReadReq miss latency 136system.cpu.icache.demand_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency 137system.cpu.icache.demand_avg_miss_latency::total 21022.880215 # average overall miss latency 138system.cpu.icache.overall_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency 139system.cpu.icache.overall_avg_miss_latency::total 21022.880215 # average overall miss latency | 134system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21027.174261 # average ReadReq miss latency 135system.cpu.icache.ReadReq_avg_miss_latency::total 21027.174261 # average ReadReq miss latency 136system.cpu.icache.demand_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency 137system.cpu.icache.demand_avg_miss_latency::total 21027.174261 # average overall miss latency 138system.cpu.icache.overall_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency 139system.cpu.icache.overall_avg_miss_latency::total 21027.174261 # average overall miss latency |
| 140system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 141system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 142system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 143system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 144system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 145system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146system.cpu.icache.fast_writes 0 # number of fast writes performed 147system.cpu.icache.cache_copies 0 # number of cache copies performed 148system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 149system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 150system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 151system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 152system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 153system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses | 140system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 141system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 142system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 143system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 144system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 145system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146system.cpu.icache.fast_writes 0 # number of fast writes performed 147system.cpu.icache.cache_copies 0 # number of cache copies performed 148system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 149system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 150system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 151system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 152system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 153system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses |
| 154system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles 155system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles 156system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles 157system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles 158system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles 159system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles | 154system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281278000 # number of ReadReq MSHR miss cycles 155system.cpu.icache.ReadReq_mshr_miss_latency::total 281278000 # number of ReadReq MSHR miss cycles 156system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281278000 # number of demand (read+write) MSHR miss cycles 157system.cpu.icache.demand_mshr_miss_latency::total 281278000 # number of demand (read+write) MSHR miss cycles 158system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281278000 # number of overall MSHR miss cycles 159system.cpu.icache.overall_mshr_miss_latency::total 281278000 # number of overall MSHR miss cycles |
| 160system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 161system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 162system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 163system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 164system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 165system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses | 160system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 161system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 162system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 163system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 164system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 165system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses |
| 166system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency 167system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency 168system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency 169system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency 170system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency 171system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency | 166system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18027.174261 # average ReadReq mshr miss latency 167system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18027.174261 # average ReadReq mshr miss latency 168system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency 169system.cpu.icache.demand_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency 170system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency 171system.cpu.icache.overall_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency |
| 172system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 173system.cpu.dcache.replacements 1332 # number of replacements | 172system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 173system.cpu.dcache.replacements 1332 # number of replacements |
| 174system.cpu.dcache.tagsinuse 3078.396294 # Cycle average of tags in use | 174system.cpu.dcache.tagsinuse 3078.361570 # Cycle average of tags in use |
| 175system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. 176system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. 177system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. 178system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 175system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. 176system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. 177system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. 178system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 179system.cpu.dcache.occ_blocks::cpu.data 3078.396294 # Average occupied blocks per requestor 180system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy 181system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy | 179system.cpu.dcache.occ_blocks::cpu.data 3078.361570 # Average occupied blocks per requestor 180system.cpu.dcache.occ_percent::cpu.data 0.751553 # Average percentage of cache occupancy 181system.cpu.dcache.occ_percent::total 0.751553 # Average percentage of cache occupancy |
| 182system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits 183system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits 184system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 185system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 186system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 187system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 188system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 189system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits --- 4 unchanged lines hidden (view full) --- 194system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses 195system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses 196system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 197system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 198system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses 199system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses 200system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses 201system.cpu.dcache.overall_misses::total 4478 # number of overall misses | 182system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits 183system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits 184system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 185system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 186system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 187system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 188system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 189system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits --- 4 unchanged lines hidden (view full) --- 194system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses 195system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses 196system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 197system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 198system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses 199system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses 200system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses 201system.cpu.dcache.overall_misses::total 4478 # number of overall misses |
| 202system.cpu.dcache.ReadReq_miss_latency::cpu.data 79898000 # number of ReadReq miss cycles 203system.cpu.dcache.ReadReq_miss_latency::total 79898000 # number of ReadReq miss cycles 204system.cpu.dcache.WriteReq_miss_latency::cpu.data 160160000 # number of WriteReq miss cycles 205system.cpu.dcache.WriteReq_miss_latency::total 160160000 # number of WriteReq miss cycles 206system.cpu.dcache.demand_miss_latency::cpu.data 240058000 # number of demand (read+write) miss cycles 207system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles 208system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles 209system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles | 202system.cpu.dcache.ReadReq_miss_latency::cpu.data 80120000 # number of ReadReq miss cycles 203system.cpu.dcache.ReadReq_miss_latency::total 80120000 # number of ReadReq miss cycles 204system.cpu.dcache.WriteReq_miss_latency::cpu.data 160192000 # number of WriteReq miss cycles 205system.cpu.dcache.WriteReq_miss_latency::total 160192000 # number of WriteReq miss cycles 206system.cpu.dcache.demand_miss_latency::cpu.data 240312000 # number of demand (read+write) miss cycles 207system.cpu.dcache.demand_miss_latency::total 240312000 # number of demand (read+write) miss cycles 208system.cpu.dcache.overall_miss_latency::cpu.data 240312000 # number of overall miss cycles 209system.cpu.dcache.overall_miss_latency::total 240312000 # number of overall miss cycles |
| 210system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) 211system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) 212system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 213system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 214system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 215system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 216system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 217system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 222system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 223system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 224system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 225system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 226system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses 227system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses 228system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses 229system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses | 210system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) 211system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) 212system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 213system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 214system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 215system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 216system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 217system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 222system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 223system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 224system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 225system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 226system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses 227system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses 228system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses 229system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses |
| 230system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency 231system.cpu.dcache.ReadReq_avg_miss_latency::total 49749.688667 # average ReadReq miss latency 232system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency 233system.cpu.dcache.WriteReq_avg_miss_latency::total 55766.016713 # average WriteReq miss latency 234system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency 235system.cpu.dcache.demand_avg_miss_latency::total 53608.307280 # average overall miss latency 236system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency 237system.cpu.dcache.overall_avg_miss_latency::total 53608.307280 # average overall miss latency | 230system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49887.920299 # average ReadReq miss latency 231system.cpu.dcache.ReadReq_avg_miss_latency::total 49887.920299 # average ReadReq miss latency 232system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55777.158774 # average WriteReq miss latency 233system.cpu.dcache.WriteReq_avg_miss_latency::total 55777.158774 # average WriteReq miss latency 234system.cpu.dcache.demand_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency 235system.cpu.dcache.demand_avg_miss_latency::total 53665.029031 # average overall miss latency 236system.cpu.dcache.overall_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency 237system.cpu.dcache.overall_avg_miss_latency::total 53665.029031 # average overall miss latency |
| 238system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 239system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 240system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 241system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 242system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 243system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 244system.cpu.dcache.fast_writes 0 # number of fast writes performed 245system.cpu.dcache.cache_copies 0 # number of cache copies performed 246system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 247system.cpu.dcache.writebacks::total 998 # number of writebacks 248system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses 249system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses 250system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 251system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 252system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses 253system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses 254system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 255system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses | 238system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 239system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 240system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 241system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 242system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 243system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 244system.cpu.dcache.fast_writes 0 # number of fast writes performed 245system.cpu.dcache.cache_copies 0 # number of cache copies performed 246system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 247system.cpu.dcache.writebacks::total 998 # number of writebacks 248system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses 249system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses 250system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 251system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 252system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses 253system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses 254system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 255system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses |
| 256system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles 257system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles 258system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles 259system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles 260system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles 261system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles 262system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles 263system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles | 256system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75302000 # number of ReadReq MSHR miss cycles 257system.cpu.dcache.ReadReq_mshr_miss_latency::total 75302000 # number of ReadReq MSHR miss cycles 258system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151576000 # number of WriteReq MSHR miss cycles 259system.cpu.dcache.WriteReq_mshr_miss_latency::total 151576000 # number of WriteReq MSHR miss cycles 260system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226878000 # number of demand (read+write) MSHR miss cycles 261system.cpu.dcache.demand_mshr_miss_latency::total 226878000 # number of demand (read+write) MSHR miss cycles 262system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226878000 # number of overall MSHR miss cycles 263system.cpu.dcache.overall_mshr_miss_latency::total 226878000 # number of overall MSHR miss cycles |
| 264system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses 265system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses 266system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 267system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 268system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses 269system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses 270system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses 271system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses | 264system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses 265system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses 266system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 267system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 268system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses 269system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses 270system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses 271system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses |
| 272system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency 273system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency 274system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency 275system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency 276system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency 277system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency 278system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency 279system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency | 272system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46887.920299 # average ReadReq mshr miss latency 273system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46887.920299 # average ReadReq mshr miss latency 274system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52777.158774 # average WriteReq mshr miss latency 275system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52777.158774 # average WriteReq mshr miss latency 276system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency 277system.cpu.dcache.demand_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency 278system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency 279system.cpu.dcache.overall_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency |
| 280system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 281system.cpu.l2cache.replacements 0 # number of replacements | 280system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 281system.cpu.l2cache.replacements 0 # number of replacements |
| 282system.cpu.l2cache.tagsinuse 3487.701804 # Cycle average of tags in use | 282system.cpu.l2cache.tagsinuse 3487.655618 # Cycle average of tags in use |
| 283system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. 284system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. 285system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. 286system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 283system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. 284system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. 285system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. 286system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 287system.cpu.l2cache.occ_blocks::writebacks 341.613277 # Average occupied blocks per requestor 288system.cpu.l2cache.occ_blocks::cpu.inst 2408.384377 # Average occupied blocks per requestor 289system.cpu.l2cache.occ_blocks::cpu.data 737.704150 # Average occupied blocks per requestor | 287system.cpu.l2cache.occ_blocks::writebacks 341.607182 # Average occupied blocks per requestor 288system.cpu.l2cache.occ_blocks::cpu.inst 2408.352970 # Average occupied blocks per requestor 289system.cpu.l2cache.occ_blocks::cpu.data 737.695465 # Average occupied blocks per requestor |
| 290system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy | 290system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy |
| 291system.cpu.l2cache.occ_percent::cpu.inst 0.073498 # Average percentage of cache occupancy | 291system.cpu.l2cache.occ_percent::cpu.inst 0.073497 # Average percentage of cache occupancy |
| 292system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy | 292system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy |
| 293system.cpu.l2cache.occ_percent::total 0.106436 # Average percentage of cache occupancy | 293system.cpu.l2cache.occ_percent::total 0.106435 # Average percentage of cache occupancy |
| 294system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits 295system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits 296system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits 297system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits 298system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits 299system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 300system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 301system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits --- 117 unchanged lines hidden --- | 294system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits 295system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits 296system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits 297system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits 298system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits 299system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 300system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 301system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits --- 117 unchanged lines hidden --- |