| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.525854 # Number of seconds simulated 4sim_ticks 525854475000 # Number of ticks simulated 5final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.525854 # Number of seconds simulated 4sim_ticks 525854475000 # Number of ticks simulated 5final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1189484 # Simulator instruction rate (inst/s) 8host_op_rate 1520711 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2293381880 # Simulator tick rate (ticks/s) 10host_mem_usage 230756 # Number of bytes of host memory used 11host_seconds 229.29 # Real time elapsed on the host | 7host_inst_rate 425859 # Simulator instruction rate (inst/s) 8host_op_rate 544445 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 821076045 # Simulator tick rate (ticks/s) 10host_mem_usage 237820 # Number of bytes of host memory used 11host_seconds 640.45 # Real time elapsed on the host |
| 12sim_insts 272739291 # Number of instructions simulated 13sim_ops 348687131 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 437312 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 6833 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 103 unchanged lines hidden (view full) --- 123system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 124system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency 125system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency 126system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency 127system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 128system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 129system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 130system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 272739291 # Number of instructions simulated 13sim_ops 348687131 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 437312 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 6833 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 103 unchanged lines hidden (view full) --- 123system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 124system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency 125system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency 126system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency 127system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 128system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 129system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 130system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 131system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 132system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 131system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 132system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 133system.cpu.icache.fast_writes 0 # number of fast writes performed 134system.cpu.icache.cache_copies 0 # number of cache copies performed 135system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 136system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 137system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 138system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 139system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 140system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses --- 66 unchanged lines hidden (view full) --- 207system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency 208system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency 209system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency 210system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency 211system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 213system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 214system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 133system.cpu.icache.fast_writes 0 # number of fast writes performed 134system.cpu.icache.cache_copies 0 # number of cache copies performed 135system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 136system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 137system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 138system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 139system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 140system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses --- 66 unchanged lines hidden (view full) --- 207system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency 208system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency 209system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency 210system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency 211system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 213system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 214system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 215system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 216system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 215system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 216system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 217system.cpu.dcache.fast_writes 0 # number of fast writes performed 218system.cpu.dcache.cache_copies 0 # number of cache copies performed 219system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 220system.cpu.dcache.writebacks::total 998 # number of writebacks 221system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses 222system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses 223system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 224system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses --- 92 unchanged lines hidden (view full) --- 317system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 318system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 319system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 320system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 321system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 322system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 323system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 324system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 217system.cpu.dcache.fast_writes 0 # number of fast writes performed 218system.cpu.dcache.cache_copies 0 # number of cache copies performed 219system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 220system.cpu.dcache.writebacks::total 998 # number of writebacks 221system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses 222system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses 223system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 224system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses --- 92 unchanged lines hidden (view full) --- 317system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 318system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 319system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 320system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 321system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 322system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 323system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 324system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 325system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 326system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 325system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 326system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 327system.cpu.l2cache.fast_writes 0 # number of fast writes performed 328system.cpu.l2cache.cache_copies 0 # number of cache copies performed 329system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses 330system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses 331system.cpu.l2cache.ReadReq_mshr_misses::total 3977 # number of ReadReq MSHR misses 332system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 333system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 334system.cpu.l2cache.demand_mshr_misses::cpu.inst 2610 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- | 327system.cpu.l2cache.fast_writes 0 # number of fast writes performed 328system.cpu.l2cache.cache_copies 0 # number of cache copies performed 329system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses 330system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses 331system.cpu.l2cache.ReadReq_mshr_misses::total 3977 # number of ReadReq MSHR misses 332system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 333system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 334system.cpu.l2cache.demand_mshr_misses::cpu.inst 2610 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- |