Cross Reference: /gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt

stats.txt (11515:c48c7cc5a522)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517291 # Number of seconds simulated 4sim_ticks 517291025500 # Number of ticks simulated 5final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517291 # Number of seconds simulated 4sim_ticks 517291025500 # Number of ticks simulated 5final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 977708 # Simulator instruction rate (inst/s) 8host_op_rate 1173775 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1854370201 # Simulator tick rate (ticks/s) 10host_mem_usage 319164 # Number of bytes of host memory used 11host_seconds 278.96 # Real time elapsed on the host	7host_inst_rate 968617 # Simulator instruction rate (inst/s) 8host_op_rate 1162861 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1837127354 # Simulator tick rate (ticks/s) 10host_mem_usage 320856 # Number of bytes of host memory used 11host_seconds 281.58 # Real time elapsed on the host
12sim_insts 272739286 # Number of instructions simulated 13sim_ops 327433744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 272739286 # Number of instructions simulated 13sim_ops 327433744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)	17system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory 19system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
	33system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
32system.cpu_clk_domain.clock 500 # Clock period in ticks	34system.cpu_clk_domain.clock 500 # Clock period in ticks
	35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses	66system.cpu.dtb.walker.walks 0 # Table walker walks requested 67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.dtb.read_accesses 0 # DTB read accesses 90system.cpu.dtb.write_accesses 0 # DTB write accesses 91system.cpu.dtb.inst_accesses 0 # ITB inst accesses 92system.cpu.dtb.hits 0 # DTB hits 93system.cpu.dtb.misses 0 # DTB misses 94system.cpu.dtb.accesses 0 # DTB accesses
	95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 191 # Number of system calls	126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 191 # Number of system calls
	156system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states
150system.cpu.numCycles 1034582051 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 272739286 # Number of instructions committed 154system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 157system.cpu.num_func_calls 12448615 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 202system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 205system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 206system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 327812214 # Class of executed instruction	157system.cpu.numCycles 1034582051 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 272739286 # Number of instructions committed 161system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 164system.cpu.num_func_calls 12448615 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 209system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 212system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 213system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 327812214 # Class of executed instruction
	217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
210system.cpu.dcache.tags.replacements 1332 # number of replacements 211system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 222system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 223system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 224system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 225system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 226system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses 227system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses	218system.cpu.dcache.tags.replacements 1332 # number of replacements 219system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use 220system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 221system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 222system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 224system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor 225system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy 227system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 232system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 233system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 234system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses 235system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
	236system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
228system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits 229system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits 230system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 231system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 232system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits 233system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits 234system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 235system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits --- 102 unchanged lines hidden (view full) --- 338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency 339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency 340system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 342system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency 343system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency 344system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency 345system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency	237system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits 238system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits 239system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 240system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 241system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits 242system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits 243system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 244system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits --- 102 unchanged lines hidden (view full) --- 347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency 348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency 349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 350system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 351system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency 352system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency 353system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency 354system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
	355system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
346system.cpu.icache.tags.replacements 13796 # number of replacements 347system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use 348system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. 349system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 350system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. 351system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 352system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor 353system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy 354system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy 355system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 356system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id 361system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id 362system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses 363system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses	356system.cpu.icache.tags.replacements 13796 # number of replacements 357system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use 358system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. 359system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 360system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. 361system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 362system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor 363system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy 364system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy 365system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 368system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 369system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 370system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id 371system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id 372system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses 373system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
	374system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
364system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits 365system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits 366system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits 367system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits 368system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits 369system.cpu.icache.overall_hits::total 348644750 # number of overall hits 370system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 371system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency	375system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits 376system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits 377system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits 378system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits 379system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits 380system.cpu.icache.overall_hits::total 348644750 # number of overall hits 381system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 382system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 435system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 436system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 437system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency 438system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency 439system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 440system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency 441system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 442system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
	443system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
432system.cpu.l2cache.tags.replacements 0 # number of replacements 433system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use 434system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. 435system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 436system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. 437system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 438system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor 439system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 446system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 447system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 448system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 449system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id 450system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id 451system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id 452system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses 453system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses	444system.cpu.l2cache.tags.replacements 0 # number of replacements 445system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use 446system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. 447system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 448system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. 449system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 450system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor 451system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 458system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 459system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 460system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 461system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id 462system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id 463system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id 464system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses 465system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
	466system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
454system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits 455system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits 456system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits 457system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits 458system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 459system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 460system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits 461system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits --- 124 unchanged lines hidden (view full) --- 586system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 587system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency 588system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. 589system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 590system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 591system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 592system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 593system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	467system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits 468system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits 469system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits 470system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits 471system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 472system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 473system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits 474system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits --- 124 unchanged lines hidden (view full) --- 599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 600system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency 601system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. 602system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 603system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 604system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 605system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 606system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	607system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
594system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 595system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution 596system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution 597system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution 598system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 599system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 600system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 618system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 619system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram 620system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks) 621system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 622system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 623system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 624system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 625system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)	608system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 613system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 614system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution 615system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 632system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 633system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram 634system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks) 635system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 636system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 637system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 638system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 639system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
	640system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
626system.membus.trans_dist::ReadResp 3976 # Transaction distribution 627system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 628system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 629system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution 630system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 631system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) 632system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 633system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden ---	641system.membus.trans_dist::ReadResp 3976 # Transaction distribution 642system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 643system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 644system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution 645system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 646system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) 647system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 648system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.517291 # Number of seconds simulated
4sim_ticks 517291025500 # Number of ticks simulated
5final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 977708 # Simulator instruction rate (inst/s)
8host_op_rate 1173775 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1854370201 # Simulator tick rate (ticks/s)
10host_mem_usage 319164 # Number of bytes of host memory used
11host_seconds 278.96 # Real time elapsed on the host

7host_inst_rate 968617 # Simulator instruction rate (inst/s)
8host_op_rate 1162861 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1837127354 # Simulator tick rate (ticks/s)
10host_mem_usage 320856 # Number of bytes of host memory used
11host_seconds 281.58 # Real time elapsed on the host

12sim_insts 272739286 # Number of instructions simulated
13sim_ops 327433744 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)

17system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
19system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)

33system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

32system.cpu_clk_domain.clock 500 # Clock period in ticks

34system.cpu_clk_domain.clock 500 # Clock period in ticks

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

62system.cpu.dtb.walker.walks 0 # Table walker walks requested
63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
85system.cpu.dtb.read_accesses 0 # DTB read accesses
86system.cpu.dtb.write_accesses 0 # DTB write accesses
87system.cpu.dtb.inst_accesses 0 # ITB inst accesses
88system.cpu.dtb.hits 0 # DTB hits
89system.cpu.dtb.misses 0 # DTB misses
90system.cpu.dtb.accesses 0 # DTB accesses

66system.cpu.dtb.walker.walks 0 # Table walker walks requested
67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
89system.cpu.dtb.read_accesses 0 # DTB read accesses
90system.cpu.dtb.write_accesses 0 # DTB write accesses
91system.cpu.dtb.inst_accesses 0 # ITB inst accesses
92system.cpu.dtb.hits 0 # DTB hits
93system.cpu.dtb.misses 0 # DTB misses
94system.cpu.dtb.accesses 0 # DTB accesses

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

120system.cpu.itb.walker.walks 0 # Table walker walks requested
121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
143system.cpu.itb.read_accesses 0 # DTB read accesses
144system.cpu.itb.write_accesses 0 # DTB write accesses
145system.cpu.itb.inst_accesses 0 # ITB inst accesses
146system.cpu.itb.hits 0 # DTB hits
147system.cpu.itb.misses 0 # DTB misses
148system.cpu.itb.accesses 0 # DTB accesses
149system.cpu.workload.num_syscalls 191 # Number of system calls

126system.cpu.itb.walker.walks 0 # Table walker walks requested
127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149system.cpu.itb.read_accesses 0 # DTB read accesses
150system.cpu.itb.write_accesses 0 # DTB write accesses
151system.cpu.itb.inst_accesses 0 # ITB inst accesses
152system.cpu.itb.hits 0 # DTB hits
153system.cpu.itb.misses 0 # DTB misses
154system.cpu.itb.accesses 0 # DTB accesses
155system.cpu.workload.num_syscalls 191 # Number of system calls

156system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states

150system.cpu.numCycles 1034582051 # number of cpu cycles simulated
151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
153system.cpu.committedInsts 272739286 # Number of instructions committed
154system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
155system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
156system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
157system.cpu.num_func_calls 12448615 # number of times a function call or return occured

--- 44 unchanged lines hidden (view full) ---

202system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
203system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
204system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
205system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
206system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
209system.cpu.op_class::total 327812214 # Class of executed instruction

157system.cpu.numCycles 1034582051 # number of cpu cycles simulated
158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 272739286 # Number of instructions committed
161system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
164system.cpu.num_func_calls 12448615 # number of times a function call or return occured

--- 44 unchanged lines hidden (view full) ---

209system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
212system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
213system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 327812214 # Class of executed instruction

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

210system.cpu.dcache.tags.replacements 1332 # number of replacements
211system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
212system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
213system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
214system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
216system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
217system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
218system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
219system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
220system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
221system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
222system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
223system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
224system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
225system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
226system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
227system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses

218system.cpu.dcache.tags.replacements 1332 # number of replacements
219system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
220system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
221system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
222system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
224system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
227system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
232system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
233system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
234system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
235system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses

236system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

228system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
229system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
230system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
231system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
232system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
233system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
234system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
235system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits

--- 102 unchanged lines hidden (view full) ---

338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
340system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
342system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
343system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
344system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
345system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency

237system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
238system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
239system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
240system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
241system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
242system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
243system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
244system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits

--- 102 unchanged lines hidden (view full) ---

347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
350system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
351system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
352system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
353system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
354system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency

355system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

346system.cpu.icache.tags.replacements 13796 # number of replacements
347system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
348system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
349system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
350system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
351system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
352system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
353system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
354system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
355system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
356system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
357system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
358system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
359system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
361system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
362system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
363system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses

356system.cpu.icache.tags.replacements 13796 # number of replacements
357system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
358system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
359system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
360system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
361system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
362system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
363system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
364system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
365system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
366system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
367system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
368system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
369system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
370system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
371system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
372system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
373system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses

374system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

364system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
365system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
366system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
367system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
368system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
369system.cpu.icache.overall_hits::total 348644750 # number of overall hits
370system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
371system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
425system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
429system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
431system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency

375system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
376system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
377system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
378system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
379system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
380system.cpu.icache.overall_hits::total 348644750 # number of overall hits
381system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
382system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

435system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
436system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
437system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
438system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
439system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
440system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
441system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
442system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency

443system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

432system.cpu.l2cache.tags.replacements 0 # number of replacements
433system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
434system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
435system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
436system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
437system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
438system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
439system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

446system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
447system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
448system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
449system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
450system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
451system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
452system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
453system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses

444system.cpu.l2cache.tags.replacements 0 # number of replacements
445system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
446system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
447system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
448system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
449system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
450system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
451system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

458system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
459system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
460system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
461system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
462system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
463system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
464system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
465system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses

466system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

454system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
455system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
456system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
457system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
458system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
459system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
460system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
461system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits

--- 124 unchanged lines hidden (view full) ---

586system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
587system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
588system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
589system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
590system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
591system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
592system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
593system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

467system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
468system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
469system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
470system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
471system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
472system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
473system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
474system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits

--- 124 unchanged lines hidden (view full) ---

599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
600system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
601system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
602system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
603system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
604system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
605system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
606system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

607system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

594system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
595system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
596system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
597system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
598system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
599system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
600system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
601system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution

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618system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
619system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
620system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
621system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
622system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
623system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
624system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
625system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

608system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
611system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
612system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
613system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
614system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
615system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution

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632system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
633system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
634system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
635system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
636system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
637system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
638system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
639system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

640system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states