| stats.txt (11390:f40859930028) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517291 # Number of seconds simulated 4sim_ticks 517291025500 # Number of ticks simulated 5final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517291 # Number of seconds simulated 4sim_ticks 517291025500 # Number of ticks simulated 5final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 222408 # Simulator instruction rate (inst/s) 8host_op_rate 267009 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 421830266 # Simulator tick rate (ticks/s) 10host_mem_usage 307072 # Number of bytes of host memory used 11host_seconds 1226.30 # Real time elapsed on the host | 7host_inst_rate 647052 # Simulator instruction rate (inst/s) 8host_op_rate 776811 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1227232141 # Simulator tick rate (ticks/s) 10host_mem_usage 277364 # Number of bytes of host memory used 11host_seconds 421.51 # Real time elapsed on the host |
| 12sim_insts 272739286 # Number of instructions simulated 13sim_ops 327433744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory --- 270 unchanged lines hidden (view full) --- 290system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency 291system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency 292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 272739286 # Number of instructions simulated 13sim_ops 327433744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory --- 270 unchanged lines hidden (view full) --- 290system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency 291system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency 292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 298system.cpu.dcache.fast_writes 0 # number of fast writes performed 299system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 300system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 301system.cpu.dcache.writebacks::total 998 # number of writebacks 302system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 303system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 304system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 305system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 306system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 307system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits --- 32 unchanged lines hidden (view full) --- 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency 341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency 345system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency 347system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency | 298system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 299system.cpu.dcache.writebacks::total 998 # number of writebacks 300system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 301system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 302system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 303system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 304system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 305system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits --- 32 unchanged lines hidden (view full) --- 338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency 339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency 340system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 342system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency 343system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency 344system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency 345system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency |
| 348system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 349system.cpu.icache.tags.replacements 13796 # number of replacements 350system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use 351system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. 352system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 353system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. 354system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 355system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor 356system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 401system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency 402system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency 403system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 407system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 408system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 346system.cpu.icache.tags.replacements 13796 # number of replacements 347system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use 348system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. 349system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 350system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. 351system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 352system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor 353system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 398system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency 399system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency 400system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 401system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 402system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 404system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 405system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 409system.cpu.icache.fast_writes 0 # number of fast writes performed 410system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 411system.cpu.icache.writebacks::writebacks 13796 # number of writebacks 412system.cpu.icache.writebacks::total 13796 # number of writebacks 413system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 414system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 415system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 416system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 417system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 418system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 429system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 430system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency 432system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 434system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 436system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency | 406system.cpu.icache.writebacks::writebacks 13796 # number of writebacks 407system.cpu.icache.writebacks::total 13796 # number of writebacks 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency |
| 437system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 438system.cpu.l2cache.tags.replacements 0 # number of replacements 439system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use 440system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. 441system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 442system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. 443system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 444system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor 445system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 538system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency 539system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency 540system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 543system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 544system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 545system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 432system.cpu.l2cache.tags.replacements 0 # number of replacements 433system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use 434system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. 435system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 436system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. 437system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 438system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor 439system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 532system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency 534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 546system.cpu.l2cache.fast_writes 0 # number of fast writes performed 547system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 548system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 549system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 550system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses 551system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses 552system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses 553system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses 554system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses 555system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 588system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency 589system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency 591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 592system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency 594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 595system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency | 540system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 541system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 542system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses 543system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses 544system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses 545system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses 546system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses 547system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 580system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency 581system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency 582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency 583system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 584system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency 586system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 587system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency |
| 596system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 597system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. 598system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 599system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 600system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 601system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 602system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 603system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution --- 55 unchanged lines hidden --- | 588system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. 589system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 590system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 591system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 592system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 593system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 594system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 595system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution --- 55 unchanged lines hidden --- |