Cross Reference: /gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.517291 # Number of seconds simulated
4sim_ticks 517291025500 # Number of ticks simulated
5final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.517287 # Number of seconds simulated
4sim_ticks 517287152500 # Number of ticks simulated
5final_tick 517287152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 634406 # Simulator instruction rate (inst/s)
8host_op_rate 761628 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1203245454 # Simulator tick rate (ticks/s)
10host_mem_usage 324572 # Number of bytes of host memory used
11host_seconds 429.91 # Real time elapsed on the host
12sim_insts 272739286 # Number of instructions simulated
13sim_ops 327433744 # Number of ops (including micro ops) simulated

7host_inst_rate 131506 # Simulator instruction rate (inst/s)
8host_op_rate 157879 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 249419657 # Simulator tick rate (ticks/s)
10host_mem_usage 307088 # Number of bytes of host memory used
11host_seconds 2073.96 # Real time elapsed on the host
12sim_insts 272737951 # Number of instructions simulated
13sim_ops 327435116 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)

16system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 269696 # Number of bytes read from this memory
18system.physmem.bytes_read::total 436672 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 4214 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 6823 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 322792 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 521366 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 844158 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 322792 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 322792 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 322792 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 521366 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 844158 # Total bandwidth to/from this memory (bytes/s)

32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
143system.cpu.itb.read_accesses 0 # DTB read accesses
144system.cpu.itb.write_accesses 0 # DTB write accesses
145system.cpu.itb.inst_accesses 0 # ITB inst accesses
146system.cpu.itb.hits 0 # DTB hits
147system.cpu.itb.misses 0 # DTB misses
148system.cpu.itb.accesses 0 # DTB accesses
149system.cpu.workload.num_syscalls 191 # Number of system calls

150system.cpu.numCycles 1034582051 # number of cpu cycles simulated

150system.cpu.numCycles 1034574305 # number of cpu cycles simulated

151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

153system.cpu.committedInsts 272739286 # Number of instructions committed
154system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
155system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses

153system.cpu.committedInsts 272737951 # Number of instructions committed
154system.cpu.committedOps 327435116 # Number of ops (including micro ops) committed
155system.cpu.num_int_alu_accesses 258332236 # Number of integer alu accesses

156system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses

157system.cpu.num_func_calls 12448615 # number of times a function call or return occured
158system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
159system.cpu.num_int_insts 258331537 # number of integer instructions

157system.cpu.num_func_calls 12449970 # number of times a function call or return occured
158system.cpu.num_conditional_control_insts 15800021 # number of instructions that are conditional controls
159system.cpu.num_int_insts 258332236 # number of integer instructions

160system.cpu.num_fp_insts 114216705 # number of float instructions

161system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
162system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written

161system.cpu.num_int_register_reads 1215886434 # number of times the integer registers were read
162system.cpu.num_int_register_writes 162499715 # number of times the integer registers were written

163system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
164system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written

165system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
166system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
167system.cpu.num_mem_refs 168107847 # number of memory refs
168system.cpu.num_load_insts 85732248 # Number of load instructions
169system.cpu.num_store_insts 82375599 # Number of store instructions

165system.cpu.num_cc_register_reads 1242911540 # number of times the CC registers were read
166system.cpu.num_cc_register_writes 76355719 # number of times the CC registers were written
167system.cpu.num_mem_refs 168105830 # number of memory refs
168system.cpu.num_load_insts 85730232 # Number of load instructions
169system.cpu.num_store_insts 82375598 # Number of store instructions

170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

171system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles

171system.cpu.num_busy_cycles 1034574304.998000 # Number of busy cycles

172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles

174system.cpu.Branches 30563503 # Number of branches fetched

174system.cpu.Branches 30566209 # Number of branches fetched

175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction

176system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction

176system.cpu.op_class::IntAlu 104315933 31.82% 31.82% # Class of executed instruction

177system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
178system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
179system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
180system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
181system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
182system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
183system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
184system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction

--- 8 unchanged lines hidden (view full) ---

193system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
194system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
195system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
196system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
197system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
198system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
199system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
200system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction

201system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction

201system.cpu.op_class::SimdFloatMisc 19652356 5.99% 44.33% # Class of executed instruction

202system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction

203system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction

203system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.67% # Class of executed instruction

204system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction

205system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
206system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction

205system.cpu.op_class::MemRead 85730232 26.15% 74.87% # Class of executed instruction
206system.cpu.op_class::MemWrite 82375598 25.13% 100.00% # Class of executed instruction

207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction

209system.cpu.op_class::total 327812214 # Class of executed instruction
210system.cpu.dcache.tags.replacements 1332 # number of replacements
211system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
212system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
213system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
214system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.

209system.cpu.op_class::total 327813586 # Class of executed instruction
210system.cpu.dcache.tags.replacements 1326 # number of replacements
211system.cpu.dcache.tags.tagsinuse 3078.339297 # Cycle average of tags in use
212system.cpu.dcache.tags.total_refs 168357609 # Total number of references to valid blocks.
213system.cpu.dcache.tags.sampled_refs 4469 # Sample count of references to valid blocks.
214system.cpu.dcache.tags.avg_refs 37672.322443 # Average number of references to valid blocks.

215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

216system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
217system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
218system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
219system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id

216system.cpu.dcache.tags.occ_blocks::cpu.data 3078.339297 # Average occupied blocks per requestor
217system.cpu.dcache.tags.occ_percent::cpu.data 0.751548 # Average percentage of cache occupancy
218system.cpu.dcache.tags.occ_percent::total 0.751548 # Average percentage of cache occupancy
219system.cpu.dcache.tags.occ_task_id_blocks::1024 3143 # Occupied blocks per task id

220system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id

221system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
222system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
223system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
224system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
225system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
226system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
227system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
228system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
229system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
230system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
231system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits

221system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
222system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
223system.cpu.dcache.tags.age_task_id_blocks_1024::3 678 # Occupied blocks per task id
224system.cpu.dcache.tags.age_task_id_blocks_1024::4 2434 # Occupied blocks per task id
225system.cpu.dcache.tags.occ_task_id_percent::1024 0.767334 # Percentage of cache occupancy per task id
226system.cpu.dcache.tags.tag_accesses 336728627 # Number of tag accesses
227system.cpu.dcache.tags.data_accesses 336728627 # Number of data accesses
228system.cpu.dcache.ReadReq_hits::cpu.data 86231946 # number of ReadReq hits
229system.cpu.dcache.ReadReq_hits::total 86231946 # number of ReadReq hits
230system.cpu.dcache.WriteReq_hits::cpu.data 82049814 # number of WriteReq hits
231system.cpu.dcache.WriteReq_hits::total 82049814 # number of WriteReq hits

232system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
233system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
234system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
235system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
236system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
237system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits

238system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
239system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
240system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
241system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
242system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
243system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
244system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
245system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses

238system.cpu.dcache.demand_hits::cpu.data 168281760 # number of demand (read+write) hits
239system.cpu.dcache.demand_hits::total 168281760 # number of demand (read+write) hits
240system.cpu.dcache.overall_hits::cpu.data 168335819 # number of overall hits
241system.cpu.dcache.overall_hits::total 168335819 # number of overall hits
242system.cpu.dcache.ReadReq_misses::cpu.data 1605 # number of ReadReq misses
243system.cpu.dcache.ReadReq_misses::total 1605 # number of ReadReq misses
244system.cpu.dcache.WriteReq_misses::cpu.data 2862 # number of WriteReq misses
245system.cpu.dcache.WriteReq_misses::total 2862 # number of WriteReq misses

246system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
247system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses

248system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
249system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
250system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
251system.cpu.dcache.overall_misses::total 4479 # number of overall misses
252system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
253system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
254system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
255system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
256system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
257system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
258system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
259system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
260system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
261system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
262system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
263system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)

248system.cpu.dcache.demand_misses::cpu.data 4467 # number of demand (read+write) misses
249system.cpu.dcache.demand_misses::total 4467 # number of demand (read+write) misses
250system.cpu.dcache.overall_misses::cpu.data 4470 # number of overall misses
251system.cpu.dcache.overall_misses::total 4470 # number of overall misses
252system.cpu.dcache.ReadReq_miss_latency::cpu.data 88066000 # number of ReadReq miss cycles
253system.cpu.dcache.ReadReq_miss_latency::total 88066000 # number of ReadReq miss cycles
254system.cpu.dcache.WriteReq_miss_latency::cpu.data 176802500 # number of WriteReq miss cycles
255system.cpu.dcache.WriteReq_miss_latency::total 176802500 # number of WriteReq miss cycles
256system.cpu.dcache.demand_miss_latency::cpu.data 264868500 # number of demand (read+write) miss cycles
257system.cpu.dcache.demand_miss_latency::total 264868500 # number of demand (read+write) miss cycles
258system.cpu.dcache.overall_miss_latency::cpu.data 264868500 # number of overall miss cycles
259system.cpu.dcache.overall_miss_latency::total 264868500 # number of overall miss cycles
260system.cpu.dcache.ReadReq_accesses::cpu.data 86233551 # number of ReadReq accesses(hits+misses)
261system.cpu.dcache.ReadReq_accesses::total 86233551 # number of ReadReq accesses(hits+misses)
262system.cpu.dcache.WriteReq_accesses::cpu.data 82052676 # number of WriteReq accesses(hits+misses)
263system.cpu.dcache.WriteReq_accesses::total 82052676 # number of WriteReq accesses(hits+misses)

264system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
265system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
267system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
268system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
269system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)

270system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
271system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
272system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
273system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses

270system.cpu.dcache.demand_accesses::cpu.data 168286227 # number of demand (read+write) accesses
271system.cpu.dcache.demand_accesses::total 168286227 # number of demand (read+write) accesses
272system.cpu.dcache.overall_accesses::cpu.data 168340289 # number of overall (read+write) accesses
273system.cpu.dcache.overall_accesses::total 168340289 # number of overall (read+write) accesses

274system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
275system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
276system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
277system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
278system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
279system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
280system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
281system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
282system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
283system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses

284system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
285system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
286system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
287system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
288system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
289system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
290system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
291system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency

284system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54869.781931 # average ReadReq miss latency
285system.cpu.dcache.ReadReq_avg_miss_latency::total 54869.781931 # average ReadReq miss latency
286system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61775.856045 # average WriteReq miss latency
287system.cpu.dcache.WriteReq_avg_miss_latency::total 61775.856045 # average WriteReq miss latency
288system.cpu.dcache.demand_avg_miss_latency::cpu.data 59294.492948 # average overall miss latency
289system.cpu.dcache.demand_avg_miss_latency::total 59294.492948 # average overall miss latency
290system.cpu.dcache.overall_avg_miss_latency::cpu.data 59254.697987 # average overall miss latency
291system.cpu.dcache.overall_avg_miss_latency::total 59254.697987 # average overall miss latency

292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
298system.cpu.dcache.fast_writes 0 # number of fast writes performed
299system.cpu.dcache.cache_copies 0 # number of cache copies performed

300system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
301system.cpu.dcache.writebacks::total 998 # number of writebacks

300system.cpu.dcache.writebacks::writebacks 997 # number of writebacks
301system.cpu.dcache.writebacks::total 997 # number of writebacks

302system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
303system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
304system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
305system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
306system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
307system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits

308system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
309system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
310system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
311system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses

308system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1604 # number of ReadReq MSHR misses
309system.cpu.dcache.ReadReq_mshr_misses::total 1604 # number of ReadReq MSHR misses
310system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2862 # number of WriteReq MSHR misses
311system.cpu.dcache.WriteReq_mshr_misses::total 2862 # number of WriteReq MSHR misses

312system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
313system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses

314system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
315system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
316system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
317system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
318system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
319system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
320system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
321system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles

314system.cpu.dcache.demand_mshr_misses::cpu.data 4466 # number of demand (read+write) MSHR misses
315system.cpu.dcache.demand_mshr_misses::total 4466 # number of demand (read+write) MSHR misses
316system.cpu.dcache.overall_mshr_misses::cpu.data 4469 # number of overall MSHR misses
317system.cpu.dcache.overall_mshr_misses::total 4469 # number of overall MSHR misses
318system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86415000 # number of ReadReq MSHR miss cycles
319system.cpu.dcache.ReadReq_mshr_miss_latency::total 86415000 # number of ReadReq MSHR miss cycles
320system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 173940500 # number of WriteReq MSHR miss cycles
321system.cpu.dcache.WriteReq_mshr_miss_latency::total 173940500 # number of WriteReq MSHR miss cycles

322system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
323system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles

324system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
325system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
326system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
327system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles

324system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260355500 # number of demand (read+write) MSHR miss cycles
325system.cpu.dcache.demand_mshr_miss_latency::total 260355500 # number of demand (read+write) MSHR miss cycles
326system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260538500 # number of overall MSHR miss cycles
327system.cpu.dcache.overall_mshr_miss_latency::total 260538500 # number of overall MSHR miss cycles

328system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
329system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
330system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
331system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
332system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
333system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
334system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
335system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
336system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
337system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses

338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency

338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53874.688279 # average ReadReq mshr miss latency
339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53874.688279 # average ReadReq mshr miss latency
340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60775.856045 # average WriteReq mshr miss latency
341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60775.856045 # average WriteReq mshr miss latency

342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency

344system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
345system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
346system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
347system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency

344system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58297.245858 # average overall mshr miss latency
345system.cpu.dcache.demand_avg_mshr_miss_latency::total 58297.245858 # average overall mshr miss latency
346system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58299.060192 # average overall mshr miss latency
347system.cpu.dcache.overall_avg_mshr_miss_latency::total 58299.060192 # average overall mshr miss latency

348system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

349system.cpu.icache.tags.replacements 13796 # number of replacements
350system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
351system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
352system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
353system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.

349system.cpu.icache.tags.replacements 13798 # number of replacements
350system.cpu.icache.tags.tagsinuse 1765.947853 # Cycle average of tags in use
351system.cpu.icache.tags.total_refs 348643415 # Total number of references to valid blocks.
352system.cpu.icache.tags.sampled_refs 15605 # Sample count of references to valid blocks.
353system.cpu.icache.tags.avg_refs 22341.776033 # Average number of references to valid blocks.

354system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

355system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor

355system.cpu.icache.tags.occ_blocks::cpu.inst 1765.947853 # Average occupied blocks per requestor

356system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
357system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
358system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
359system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
361system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id

362system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
363system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id

362system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id
363system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id

364system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id

365system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
366system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
367system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
368system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
369system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
370system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
371system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
372system.cpu.icache.overall_hits::total 348644750 # number of overall hits
373system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
374system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
375system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
376system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
377system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
378system.cpu.icache.overall_misses::total 15603 # number of overall misses
379system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
380system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
381system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
382system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
383system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
384system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
385system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
386system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
387system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
388system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses
389system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses
390system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses

365system.cpu.icache.tags.tag_accesses 697333645 # Number of tag accesses
366system.cpu.icache.tags.data_accesses 697333645 # Number of data accesses
367system.cpu.icache.ReadReq_hits::cpu.inst 348643415 # number of ReadReq hits
368system.cpu.icache.ReadReq_hits::total 348643415 # number of ReadReq hits
369system.cpu.icache.demand_hits::cpu.inst 348643415 # number of demand (read+write) hits
370system.cpu.icache.demand_hits::total 348643415 # number of demand (read+write) hits
371system.cpu.icache.overall_hits::cpu.inst 348643415 # number of overall hits
372system.cpu.icache.overall_hits::total 348643415 # number of overall hits
373system.cpu.icache.ReadReq_misses::cpu.inst 15605 # number of ReadReq misses
374system.cpu.icache.ReadReq_misses::total 15605 # number of ReadReq misses
375system.cpu.icache.demand_misses::cpu.inst 15605 # number of demand (read+write) misses
376system.cpu.icache.demand_misses::total 15605 # number of demand (read+write) misses
377system.cpu.icache.overall_misses::cpu.inst 15605 # number of overall misses
378system.cpu.icache.overall_misses::total 15605 # number of overall misses
379system.cpu.icache.ReadReq_miss_latency::cpu.inst 338522000 # number of ReadReq miss cycles
380system.cpu.icache.ReadReq_miss_latency::total 338522000 # number of ReadReq miss cycles
381system.cpu.icache.demand_miss_latency::cpu.inst 338522000 # number of demand (read+write) miss cycles
382system.cpu.icache.demand_miss_latency::total 338522000 # number of demand (read+write) miss cycles
383system.cpu.icache.overall_miss_latency::cpu.inst 338522000 # number of overall miss cycles
384system.cpu.icache.overall_miss_latency::total 338522000 # number of overall miss cycles
385system.cpu.icache.ReadReq_accesses::cpu.inst 348659020 # number of ReadReq accesses(hits+misses)
386system.cpu.icache.ReadReq_accesses::total 348659020 # number of ReadReq accesses(hits+misses)
387system.cpu.icache.demand_accesses::cpu.inst 348659020 # number of demand (read+write) accesses
388system.cpu.icache.demand_accesses::total 348659020 # number of demand (read+write) accesses
389system.cpu.icache.overall_accesses::cpu.inst 348659020 # number of overall (read+write) accesses
390system.cpu.icache.overall_accesses::total 348659020 # number of overall (read+write) accesses

391system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
392system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
393system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
394system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
395system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
396system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses

397system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
398system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
399system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
400system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
401system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
402system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency

397system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21693.175264 # average ReadReq miss latency
398system.cpu.icache.ReadReq_avg_miss_latency::total 21693.175264 # average ReadReq miss latency
399system.cpu.icache.demand_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency
400system.cpu.icache.demand_avg_miss_latency::total 21693.175264 # average overall miss latency
401system.cpu.icache.overall_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency
402system.cpu.icache.overall_avg_miss_latency::total 21693.175264 # average overall miss latency

403system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
404system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
405system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
406system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
407system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
408system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
409system.cpu.icache.fast_writes 0 # number of fast writes performed
410system.cpu.icache.cache_copies 0 # number of cache copies performed

411system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
412system.cpu.icache.writebacks::total 13796 # number of writebacks
413system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
414system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
415system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
416system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
417system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
418system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
419system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
420system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
421system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
422system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
423system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
424system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles

411system.cpu.icache.writebacks::writebacks 13798 # number of writebacks
412system.cpu.icache.writebacks::total 13798 # number of writebacks
413system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15605 # number of ReadReq MSHR misses
414system.cpu.icache.ReadReq_mshr_misses::total 15605 # number of ReadReq MSHR misses
415system.cpu.icache.demand_mshr_misses::cpu.inst 15605 # number of demand (read+write) MSHR misses
416system.cpu.icache.demand_mshr_misses::total 15605 # number of demand (read+write) MSHR misses
417system.cpu.icache.overall_mshr_misses::cpu.inst 15605 # number of overall MSHR misses
418system.cpu.icache.overall_mshr_misses::total 15605 # number of overall MSHR misses
419system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322917000 # number of ReadReq MSHR miss cycles
420system.cpu.icache.ReadReq_mshr_miss_latency::total 322917000 # number of ReadReq MSHR miss cycles
421system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322917000 # number of demand (read+write) MSHR miss cycles
422system.cpu.icache.demand_mshr_miss_latency::total 322917000 # number of demand (read+write) MSHR miss cycles
423system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322917000 # number of overall MSHR miss cycles
424system.cpu.icache.overall_mshr_miss_latency::total 322917000 # number of overall MSHR miss cycles

425system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
426system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
427system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
428system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
429system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
430system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses

431system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
432system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
433system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
434system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
435system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
436system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency

431system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.175264 # average ReadReq mshr miss latency
432system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.175264 # average ReadReq mshr miss latency
433system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency
434system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency
435system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency
436system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency

437system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
438system.cpu.l2cache.tags.replacements 0 # number of replacements

439system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use

439system.cpu.l2cache.tags.tagsinuse 3487.616981 # Cycle average of tags in use

440system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
441system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
442system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
443system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

444system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
445system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
446system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor

444system.cpu.l2cache.tags.occ_blocks::writebacks 341.600605 # Average occupied blocks per requestor
445system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.332701 # Average occupied blocks per requestor
446system.cpu.l2cache.tags.occ_blocks::cpu.data 738.683674 # Average occupied blocks per requestor

447system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
448system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
449system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
450system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy
451system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
452system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
453system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id

454system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
455system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id

454system.cpu.l2cache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
455system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1233 # Occupied blocks per task id

456system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
457system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id

458system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
459system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
460system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
461system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
462system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
463system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits

458system.cpu.l2cache.tags.tag_accesses 228016 # Number of tag accesses
459system.cpu.l2cache.tags.data_accesses 228016 # Number of data accesses
460system.cpu.l2cache.WritebackDirty_hits::writebacks 997 # number of WritebackDirty hits
461system.cpu.l2cache.WritebackDirty_hits::total 997 # number of WritebackDirty hits
462system.cpu.l2cache.WritebackClean_hits::writebacks 6213 # number of WritebackClean hits
463system.cpu.l2cache.WritebackClean_hits::total 6213 # number of WritebackClean hits

464system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
465system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits

466system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
467system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits
468system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits
469system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits
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471system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits
472system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
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474system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits
475system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
476system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
477system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
478system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses
479system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses

466system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12996 # number of ReadCleanReq hits
467system.cpu.l2cache.ReadCleanReq_hits::total 12996 # number of ReadCleanReq hits
468system.cpu.l2cache.ReadSharedReq_hits::cpu.data 239 # number of ReadSharedReq hits
469system.cpu.l2cache.ReadSharedReq_hits::total 239 # number of ReadSharedReq hits
470system.cpu.l2cache.demand_hits::cpu.inst 12996 # number of demand (read+write) hits
471system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
472system.cpu.l2cache.demand_hits::total 13251 # number of demand (read+write) hits
473system.cpu.l2cache.overall_hits::cpu.inst 12996 # number of overall hits
474system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
475system.cpu.l2cache.overall_hits::total 13251 # number of overall hits
476system.cpu.l2cache.ReadExReq_misses::cpu.data 2846 # number of ReadExReq misses
477system.cpu.l2cache.ReadExReq_misses::total 2846 # number of ReadExReq misses
478system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2609 # number of ReadCleanReq misses
479system.cpu.l2cache.ReadCleanReq_misses::total 2609 # number of ReadCleanReq misses

480system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses
481system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses

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486system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses
487system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
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489system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles
490system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles
491system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles

482system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses
483system.cpu.l2cache.demand_misses::cpu.data 4214 # number of demand (read+write) misses
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485system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses
486system.cpu.l2cache.overall_misses::cpu.data 4214 # number of overall misses
487system.cpu.l2cache.overall_misses::total 6823 # number of overall misses
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489system.cpu.l2cache.ReadExReq_miss_latency::total 169475500 # number of ReadExReq miss cycles
490system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155351500 # number of ReadCleanReq miss cycles
491system.cpu.l2cache.ReadCleanReq_miss_latency::total 155351500 # number of ReadCleanReq miss cycles

492system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
493system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles

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496system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles
497system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles
498system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles
499system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles
500system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses)
501system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses)
502system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses)
503system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses)
504system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
505system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
506system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses)
507system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses)
508system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses)
509system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses)
510system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
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514system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
515system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
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517system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
518system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses
519system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses
520system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses
521system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses
522system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses
523system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses
524system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
525system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses
526system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses
527system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
528system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
529system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
530system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
531system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency

494system.cpu.l2cache.demand_miss_latency::cpu.inst 155351500 # number of demand (read+write) miss cycles
495system.cpu.l2cache.demand_miss_latency::cpu.data 251066500 # number of demand (read+write) miss cycles
496system.cpu.l2cache.demand_miss_latency::total 406418000 # number of demand (read+write) miss cycles
497system.cpu.l2cache.overall_miss_latency::cpu.inst 155351500 # number of overall miss cycles
498system.cpu.l2cache.overall_miss_latency::cpu.data 251066500 # number of overall miss cycles
499system.cpu.l2cache.overall_miss_latency::total 406418000 # number of overall miss cycles
500system.cpu.l2cache.WritebackDirty_accesses::writebacks 997 # number of WritebackDirty accesses(hits+misses)
501system.cpu.l2cache.WritebackDirty_accesses::total 997 # number of WritebackDirty accesses(hits+misses)
502system.cpu.l2cache.WritebackClean_accesses::writebacks 6213 # number of WritebackClean accesses(hits+misses)
503system.cpu.l2cache.WritebackClean_accesses::total 6213 # number of WritebackClean accesses(hits+misses)
504system.cpu.l2cache.ReadExReq_accesses::cpu.data 2862 # number of ReadExReq accesses(hits+misses)
505system.cpu.l2cache.ReadExReq_accesses::total 2862 # number of ReadExReq accesses(hits+misses)
506system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15605 # number of ReadCleanReq accesses(hits+misses)
507system.cpu.l2cache.ReadCleanReq_accesses::total 15605 # number of ReadCleanReq accesses(hits+misses)
508system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1607 # number of ReadSharedReq accesses(hits+misses)
509system.cpu.l2cache.ReadSharedReq_accesses::total 1607 # number of ReadSharedReq accesses(hits+misses)
510system.cpu.l2cache.demand_accesses::cpu.inst 15605 # number of demand (read+write) accesses
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513system.cpu.l2cache.overall_accesses::cpu.inst 15605 # number of overall (read+write) accesses
514system.cpu.l2cache.overall_accesses::cpu.data 4469 # number of overall (read+write) accesses
515system.cpu.l2cache.overall_accesses::total 20074 # number of overall (read+write) accesses
516system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994410 # miss rate for ReadExReq accesses
517system.cpu.l2cache.ReadExReq_miss_rate::total 0.994410 # miss rate for ReadExReq accesses
518system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167190 # miss rate for ReadCleanReq accesses
519system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167190 # miss rate for ReadCleanReq accesses
520system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851276 # miss rate for ReadSharedReq accesses
521system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851276 # miss rate for ReadSharedReq accesses
522system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167190 # miss rate for demand accesses
523system.cpu.l2cache.demand_miss_rate::cpu.data 0.942940 # miss rate for demand accesses
524system.cpu.l2cache.demand_miss_rate::total 0.339892 # miss rate for demand accesses
525system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167190 # miss rate for overall accesses
526system.cpu.l2cache.overall_miss_rate::cpu.data 0.942940 # miss rate for overall accesses
527system.cpu.l2cache.overall_miss_rate::total 0.339892 # miss rate for overall accesses
528system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.664793 # average ReadExReq miss latency
529system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.664793 # average ReadExReq miss latency
530system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.461479 # average ReadCleanReq miss latency
531system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.461479 # average ReadCleanReq miss latency

532system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
533system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency

534system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
535system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
536system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
537system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
538system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
539system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency

534system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency
535system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency
536system.cpu.l2cache.demand_avg_miss_latency::total 59565.880111 # average overall miss latency
537system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency
538system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency
539system.cpu.l2cache.overall_avg_miss_latency::total 59565.880111 # average overall miss latency

540system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
541system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
542system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
543system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
544system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
545system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
546system.cpu.l2cache.fast_writes 0 # number of fast writes performed
547system.cpu.l2cache.cache_copies 0 # number of cache copies performed

548system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
549system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
550system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses
551system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses

548system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2846 # number of ReadExReq MSHR misses
549system.cpu.l2cache.ReadExReq_mshr_misses::total 2846 # number of ReadExReq MSHR misses
550system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2609 # number of ReadCleanReq MSHR misses
551system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2609 # number of ReadCleanReq MSHR misses

552system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses
553system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses

554system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses
555system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses
556system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
557system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
558system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
559system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
560system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
561system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
562system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
563system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles

554system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses
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556system.cpu.l2cache.demand_mshr_misses::total 6823 # number of demand (read+write) MSHR misses
557system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
558system.cpu.l2cache.overall_mshr_misses::cpu.data 4214 # number of overall MSHR misses
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560system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141015500 # number of ReadExReq MSHR miss cycles
561system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141015500 # number of ReadExReq MSHR miss cycles
562system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129261500 # number of ReadCleanReq MSHR miss cycles
563system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129261500 # number of ReadCleanReq MSHR miss cycles

564system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
565system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles

566system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
567system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
568system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
569system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
570system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
571system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
572system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
573system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
574system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
575system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses
576system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses
577system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses
578system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
579system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
580system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
581system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
582system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
583system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
584system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
585system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
586system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
587system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency

566system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129261500 # number of demand (read+write) MSHR miss cycles
567system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 208926500 # number of demand (read+write) MSHR miss cycles
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569system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129261500 # number of overall MSHR miss cycles
570system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 208926500 # number of overall MSHR miss cycles
571system.cpu.l2cache.overall_mshr_miss_latency::total 338188000 # number of overall MSHR miss cycles
572system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994410 # mshr miss rate for ReadExReq accesses
573system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994410 # mshr miss rate for ReadExReq accesses
574system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for ReadCleanReq accesses
575system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167190 # mshr miss rate for ReadCleanReq accesses
576system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851276 # mshr miss rate for ReadSharedReq accesses
577system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851276 # mshr miss rate for ReadSharedReq accesses
578system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for demand accesses
579system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for demand accesses
580system.cpu.l2cache.demand_mshr_miss_rate::total 0.339892 # mshr miss rate for demand accesses
581system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for overall accesses
582system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for overall accesses
583system.cpu.l2cache.overall_mshr_miss_rate::total 0.339892 # mshr miss rate for overall accesses
584system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.664793 # average ReadExReq mshr miss latency
585system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.664793 # average ReadExReq mshr miss latency
586system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.461479 # average ReadCleanReq mshr miss latency
587system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.461479 # average ReadCleanReq mshr miss latency

588system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
589system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency

590system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
595system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency

590system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
595system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency

596system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

597system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
598system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
599system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

597system.cpu.toL2Bus.snoop_filter.tot_requests 35198 # Total number of requests made to the snoop filter.
598system.cpu.toL2Bus.snoop_filter.hit_single_requests 15220 # Number of requests hitting in the snoop filter with a single holder of the requested data.
599system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7664 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

600system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
601system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
602system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

603system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
611system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
612system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
613system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
614system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
615system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
616system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)

603system.cpu.toL2Bus.trans_dist::ReadResp 17212 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::WritebackDirty 997 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::WritebackClean 13798 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::CleanEvict 329 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::ReadExReq 2862 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::ReadExResp 2862 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::ReadCleanReq 15605 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::ReadSharedReq 1607 # Transaction distribution
611system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45008 # Packet count per connected master and slave (bytes)
612system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10264 # Packet count per connected master and slave (bytes)
613system.cpu.toL2Bus.pkt_count::total 55272 # Packet count per connected master and slave (bytes)
614system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881792 # Cumulative packet size per connected master and slave (bytes)
615system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 349824 # Cumulative packet size per connected master and slave (bytes)
616system.cpu.toL2Bus.pkt_size::total 2231616 # Cumulative packet size per connected master and slave (bytes)

617system.cpu.toL2Bus.snoops 0 # Total snoops (count)

618system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
619system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
620system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram

618system.cpu.toL2Bus.snoop_fanout::samples 20074 # Request fanout histogram
619system.cpu.toL2Bus.snoop_fanout::mean 0.386570 # Request fanout histogram
620system.cpu.toL2Bus.snoop_fanout::stdev 0.486976 # Request fanout histogram

621system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

622system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
623system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram

622system.cpu.toL2Bus.snoop_fanout::0 12314 61.34% 61.34% # Request fanout histogram
623system.cpu.toL2Bus.snoop_fanout::1 7760 38.66% 100.00% # Request fanout histogram

624system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
625system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
626system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
627system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram

628system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
629system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)

628system.cpu.toL2Bus.snoop_fanout::total 20074 # Request fanout histogram
629system.cpu.toL2Bus.reqLayer0.occupancy 32394000 # Layer occupancy (ticks)

630system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)

631system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)

631system.cpu.toL2Bus.respLayer0.occupancy 23407500 # Layer occupancy (ticks)

632system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)

633system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)

633system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks)

634system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

635system.membus.trans_dist::ReadResp 3976 # Transaction distribution
636system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
637system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
638system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution
639system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
640system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
641system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
642system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)

635system.membus.trans_dist::ReadResp 3977 # Transaction distribution
636system.membus.trans_dist::ReadExReq 2846 # Transaction distribution
637system.membus.trans_dist::ReadExResp 2846 # Transaction distribution
638system.membus.trans_dist::ReadSharedReq 3977 # Transaction distribution
639system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13646 # Packet count per connected master and slave (bytes)
640system.membus.pkt_count::total 13646 # Packet count per connected master and slave (bytes)
641system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 436672 # Cumulative packet size per connected master and slave (bytes)
642system.membus.pkt_size::total 436672 # Cumulative packet size per connected master and slave (bytes)

643system.membus.snoops 0 # Total snoops (count)

644system.membus.snoop_fanout::samples 6833 # Request fanout histogram

644system.membus.snoop_fanout::samples 6824 # Request fanout histogram

645system.membus.snoop_fanout::mean 0 # Request fanout histogram
646system.membus.snoop_fanout::stdev 0 # Request fanout histogram
647system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

648system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram

648system.membus.snoop_fanout::0 6824 100.00% 100.00% # Request fanout histogram

649system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
650system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
651system.membus.snoop_fanout::min_value 0 # Request fanout histogram
652system.membus.snoop_fanout::max_value 0 # Request fanout histogram

653system.membus.snoop_fanout::total 6833 # Request fanout histogram
654system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks)

653system.membus.snoop_fanout::total 6824 # Request fanout histogram
654system.membus.reqLayer0.occupancy 7272500 # Layer occupancy (ticks)

655system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)

656system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks)

656system.membus.respLayer1.occupancy 34115000 # Layer occupancy (ticks)