| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517235 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517235 # Number of seconds simulated |
| 4sim_ticks 517235411000 # Number of ticks simulated 5final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 517235404500 # Number of ticks simulated 5final_tick 517235404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 761441 # Simulator instruction rate (inst/s) 8host_op_rate 914138 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1444030997 # Simulator tick rate (ticks/s) 10host_mem_usage 318052 # Number of bytes of host memory used 11host_seconds 358.19 # Real time elapsed on the host | 7host_inst_rate 693666 # Simulator instruction rate (inst/s) 8host_op_rate 832772 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1315500911 # Simulator tick rate (ticks/s) 10host_mem_usage 318184 # Number of bytes of host memory used 11host_seconds 393.19 # Real time elapsed on the host |
| 12sim_insts 272739285 # Number of instructions simulated 13sim_ops 327433743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory --- 122 unchanged lines hidden (view full) --- 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 191 # Number of system calls | 12sim_insts 272739285 # Number of instructions simulated 13sim_ops 327433743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory --- 122 unchanged lines hidden (view full) --- 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 191 # Number of system calls |
| 150system.cpu.numCycles 1034470822 # number of cpu cycles simulated | 150system.cpu.numCycles 1034470809 # number of cpu cycles simulated |
| 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 272739285 # Number of instructions committed 154system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 157system.cpu.num_func_calls 12448615 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 163system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written 167system.cpu.num_mem_refs 168107847 # number of memory refs 168system.cpu.num_load_insts 85732248 # Number of load instructions 169system.cpu.num_store_insts 82375599 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 272739285 # Number of instructions committed 154system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 157system.cpu.num_func_calls 12448615 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 163system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written 167system.cpu.num_mem_refs 168107847 # number of memory refs 168system.cpu.num_load_insts 85732248 # Number of load instructions 169system.cpu.num_store_insts 82375599 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 171system.cpu.num_busy_cycles 1034470821.998000 # Number of busy cycles | 171system.cpu.num_busy_cycles 1034470808.998000 # Number of busy cycles |
| 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 30563502 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction 177system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 203system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 205system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 206system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 327812213 # Class of executed instruction 210system.cpu.dcache.tags.replacements 1332 # number of replacements | 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 30563502 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction 177system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 203system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 205system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 206system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 327812213 # Class of executed instruction 210system.cpu.dcache.tags.replacements 1332 # number of replacements |
| 211system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use | 211system.cpu.dcache.tags.tagsinuse 3078.445039 # Cycle average of tags in use |
| 212system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 212system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 216system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor | 216system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445039 # Average occupied blocks per requestor |
| 217system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 222system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 223system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 224system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id --- 21 unchanged lines hidden (view full) --- 246system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 247system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 248system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses 249system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses 250system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses 251system.cpu.dcache.overall_misses::total 4479 # number of overall misses 252system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles 253system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles | 217system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 222system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 223system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 224system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id --- 21 unchanged lines hidden (view full) --- 246system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 247system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 248system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses 249system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses 250system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses 251system.cpu.dcache.overall_misses::total 4479 # number of overall misses 252system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles 253system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles |
| 254system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles 255system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles 256system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles 257system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles 258system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles 259system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles | 254system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles 255system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles 256system.cpu.dcache.demand_miss_latency::cpu.data 235776500 # number of demand (read+write) miss cycles 257system.cpu.dcache.demand_miss_latency::total 235776500 # number of demand (read+write) miss cycles 258system.cpu.dcache.overall_miss_latency::cpu.data 235776500 # number of overall miss cycles 259system.cpu.dcache.overall_miss_latency::total 235776500 # number of overall miss cycles |
| 260system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) 261system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) 262system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 263system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 264system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) 265system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) 266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 267system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 278system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses 279system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses 280system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses 281system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 282system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses 283system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 284system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency 285system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency | 260system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) 261system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) 262system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 263system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 264system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) 265system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) 266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 267system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 278system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses 279system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses 280system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses 281system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 282system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses 283system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 284system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency 285system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency |
| 286system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency 287system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency 288system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency 289system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency 290system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency 291system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency | 286system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency 287system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency 288system.cpu.dcache.demand_avg_miss_latency::cpu.data 52675.714924 # average overall miss latency 289system.cpu.dcache.demand_avg_miss_latency::total 52675.714924 # average overall miss latency 290system.cpu.dcache.overall_avg_miss_latency::cpu.data 52640.433132 # average overall miss latency 291system.cpu.dcache.overall_avg_miss_latency::total 52640.433132 # average overall miss latency |
| 292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 298system.cpu.dcache.fast_writes 0 # number of fast writes performed 299system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 310system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 311system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 312system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 313system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 314system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses 315system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses 316system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 317system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses | 292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 298system.cpu.dcache.fast_writes 0 # number of fast writes performed 299system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 310system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 311system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 312system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 313system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 314system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses 315system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses 316system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 317system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses |
| 318system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles 319system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles 320system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles 321system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles 322system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles 323system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles 324system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles 325system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles 326system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles 327system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles | 318system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75909500 # number of ReadReq MSHR miss cycles 319system.cpu.dcache.ReadReq_mshr_miss_latency::total 75909500 # number of ReadReq MSHR miss cycles 320system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles 321system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles 322system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles 323system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles 324system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229024000 # number of demand (read+write) MSHR miss cycles 325system.cpu.dcache.demand_mshr_miss_latency::total 229024000 # number of demand (read+write) MSHR miss cycles 326system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229184500 # number of overall MSHR miss cycles 327system.cpu.dcache.overall_mshr_miss_latency::total 229184500 # number of overall MSHR miss cycles |
| 328system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 329system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 330system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 331system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 332system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses 333system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses 334system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 335system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 336system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 337system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses | 328system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 329system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 330system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 331system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 332system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses 333system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses 334system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 335system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 336system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 337system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
| 338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency 339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency 341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency 343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency 345system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency 347system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency | 338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47354.647536 # average ReadReq mshr miss latency 339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47354.647536 # average ReadReq mshr miss latency 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency 341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency 343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51178.547486 # average overall mshr miss latency 345system.cpu.dcache.demand_avg_mshr_miss_latency::total 51178.547486 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51180.102724 # average overall mshr miss latency 347system.cpu.dcache.overall_avg_mshr_miss_latency::total 51180.102724 # average overall mshr miss latency |
| 348system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 349system.cpu.icache.tags.replacements 13796 # number of replacements | 348system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 349system.cpu.icache.tags.replacements 13796 # number of replacements |
| 350system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use | 350system.cpu.icache.tags.tagsinuse 1766.007658 # Cycle average of tags in use |
| 351system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. 352system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 353system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. 354system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 351system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. 352system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 353system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. 354system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 355system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor | 355system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007658 # Average occupied blocks per requestor |
| 356system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy 357system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy 358system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 362system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 363system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 371system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits 372system.cpu.icache.overall_hits::total 348644749 # number of overall hits 373system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 374system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 375system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 376system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 377system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 378system.cpu.icache.overall_misses::total 15603 # number of overall misses | 356system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy 357system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy 358system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 362system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 363system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 371system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits 372system.cpu.icache.overall_hits::total 348644749 # number of overall hits 373system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 374system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 375system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 376system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 377system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 378system.cpu.icache.overall_misses::total 15603 # number of overall misses |
| 379system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles 380system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles 381system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles 382system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles 383system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles 384system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles | 379system.cpu.icache.ReadReq_miss_latency::cpu.inst 312524000 # number of ReadReq miss cycles 380system.cpu.icache.ReadReq_miss_latency::total 312524000 # number of ReadReq miss cycles 381system.cpu.icache.demand_miss_latency::cpu.inst 312524000 # number of demand (read+write) miss cycles 382system.cpu.icache.demand_miss_latency::total 312524000 # number of demand (read+write) miss cycles 383system.cpu.icache.overall_miss_latency::cpu.inst 312524000 # number of overall miss cycles 384system.cpu.icache.overall_miss_latency::total 312524000 # number of overall miss cycles |
| 385system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) 386system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) 387system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses 388system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses 389system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses 390system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses 391system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 392system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 393system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 394system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 395system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 396system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses | 385system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) 386system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) 387system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses 388system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses 389system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses 390system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses 391system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 392system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 393system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 394system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 395system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 396system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses |
| 397system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency 398system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency 399system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency 400system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency 401system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency 402system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency | 397system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.737871 # average ReadReq miss latency 398system.cpu.icache.ReadReq_avg_miss_latency::total 20029.737871 # average ReadReq miss latency 399system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency 400system.cpu.icache.demand_avg_miss_latency::total 20029.737871 # average overall miss latency 401system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency 402system.cpu.icache.overall_avg_miss_latency::total 20029.737871 # average overall miss latency |
| 403system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 407system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 408system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 409system.cpu.icache.fast_writes 0 # number of fast writes performed 410system.cpu.icache.cache_copies 0 # number of cache copies performed 411system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 412system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 413system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 414system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 415system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 416system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses | 403system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 407system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 408system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 409system.cpu.icache.fast_writes 0 # number of fast writes performed 410system.cpu.icache.cache_copies 0 # number of cache copies performed 411system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 412system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 413system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 414system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 415system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 416system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses |
| 417system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles 418system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles 422system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles | 417system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 289119500 # number of ReadReq MSHR miss cycles 418system.cpu.icache.ReadReq_mshr_miss_latency::total 289119500 # number of ReadReq MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::cpu.inst 289119500 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.demand_mshr_miss_latency::total 289119500 # number of demand (read+write) MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::cpu.inst 289119500 # number of overall MSHR miss cycles 422system.cpu.icache.overall_mshr_miss_latency::total 289119500 # number of overall MSHR miss cycles |
| 423system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 424system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 425system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 426system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 427system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 428system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses | 423system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 424system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 425system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 426system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 427system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 428system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses |
| 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency 431system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency 433system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency | 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18529.737871 # average ReadReq mshr miss latency 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18529.737871 # average ReadReq mshr miss latency 431system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency 433system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency |
| 435system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 436system.cpu.l2cache.tags.replacements 0 # number of replacements | 435system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 436system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 437system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use | 437system.cpu.l2cache.tags.tagsinuse 3487.765017 # Cycle average of tags in use |
| 438system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. 439system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 440system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. 441system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 438system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. 439system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 440system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. 441system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 442system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor 443system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor 444system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor | 442system.cpu.l2cache.tags.occ_blocks::writebacks 341.623060 # Average occupied blocks per requestor 443system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427163 # Average occupied blocks per requestor 444system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714793 # Average occupied blocks per requestor |
| 445system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy 446system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy 447system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy 448system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy 449system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id 450system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id --- 21 unchanged lines hidden (view full) --- 474system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 475system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 476system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses 477system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses 478system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 479system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses 480system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses 481system.cpu.l2cache.overall_misses::total 6832 # number of overall misses | 445system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy 446system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy 447system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy 448system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy 449system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id 450system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id --- 21 unchanged lines hidden (view full) --- 474system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 475system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 476system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses 477system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses 478system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 479system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses 480system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses 481system.cpu.l2cache.overall_misses::total 6832 # number of overall misses |
| 482system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles 483system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles 484system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles 485system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles 486system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles 487system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles 488system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles 489system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles 490system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles 491system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles 492system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles | 482system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137079500 # number of ReadReq miss cycles 483system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71954500 # number of ReadReq miss cycles 484system.cpu.l2cache.ReadReq_miss_latency::total 209034000 # number of ReadReq miss cycles 485system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150074500 # number of ReadExReq miss cycles 486system.cpu.l2cache.ReadExReq_miss_latency::total 150074500 # number of ReadExReq miss cycles 487system.cpu.l2cache.demand_miss_latency::cpu.inst 137079500 # number of demand (read+write) miss cycles 488system.cpu.l2cache.demand_miss_latency::cpu.data 222029000 # number of demand (read+write) miss cycles 489system.cpu.l2cache.demand_miss_latency::total 359108500 # number of demand (read+write) miss cycles 490system.cpu.l2cache.overall_miss_latency::cpu.inst 137079500 # number of overall miss cycles 491system.cpu.l2cache.overall_miss_latency::cpu.data 222029000 # number of overall miss cycles 492system.cpu.l2cache.overall_miss_latency::total 359108500 # number of overall miss cycles |
| 493system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) 494system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) 495system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) 496system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) 497system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) 498system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 499system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 500system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 509system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 510system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 511system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses 512system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses 513system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 514system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses 515system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses 516system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses | 493system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) 494system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) 495system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) 496system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) 497system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) 498system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 499system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 500system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 509system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 510system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 511system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses 512system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses 513system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 514system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses 515system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses 516system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses |
| 517system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency 518system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency 519system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency 520system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency 521system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency 522system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency 523system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency 524system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency 525system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency 526system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency 527system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency | 517system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.011882 # average ReadReq miss latency 518system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.795903 # average ReadReq miss latency 519system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662 # average ReadReq miss latency 520system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838 # average ReadExReq miss latency 521system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838 # average ReadExReq miss latency 522system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency 523system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency 524system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555 # average overall miss latency 525system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency 526system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency 527system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555 # average overall miss latency |
| 528system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 529system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 530system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 531system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 532system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 533system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 534system.cpu.l2cache.fast_writes 0 # number of fast writes performed 535system.cpu.l2cache.cache_copies 0 # number of cache copies performed 536system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses 537system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses 538system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses 539system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 540system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 541system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses 542system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses 543system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 544system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses 545system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses 546system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses | 528system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 529system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 530system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 531system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 532system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 533system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 534system.cpu.l2cache.fast_writes 0 # number of fast writes performed 535system.cpu.l2cache.cache_copies 0 # number of cache copies performed 536system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses 537system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses 538system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses 539system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 540system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 541system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses 542system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses 543system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 544system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses 545system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses 546system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses |
| 547system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles 548system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles 549system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles 550system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles 551system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles 552system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles 553system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles 554system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles 555system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles 556system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles 557system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles | 547system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105665500 # number of ReadReq MSHR miss cycles 548system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55363500 # number of ReadReq MSHR miss cycles 549system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles 550system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles 551system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles 552system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105665500 # number of demand (read+write) MSHR miss cycles 553system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171031500 # number of demand (read+write) MSHR miss cycles 554system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles 555system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105665500 # number of overall MSHR miss cycles 556system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171031500 # number of overall MSHR miss cycles 557system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles |
| 558system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses 559system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses 560system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses 561system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 562system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 563system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses 564system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses 565system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 566system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses 567system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses 568system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses | 558system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses 559system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses 560system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses 561system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 562system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 563system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses 564system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses 565system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 566system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses 567system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses 568system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses |
| 569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency 570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency 572system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency 573system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency 574system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency 575system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency 576system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency 577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency 578system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency 579system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency | 569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383289 # average ReadReq mshr miss latency 570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency 572system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 573system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 574system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency 575system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 576system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency 577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency 578system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 579system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency |
| 580system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 581system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution 582system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 583system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution 584system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 585system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 586system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) 587system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) 588system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) 589system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) 590system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) 591system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) 592system.cpu.toL2Bus.snoops 0 # Total snoops (count) 593system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram | 580system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 581system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution 582system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 583system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution 584system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 585system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 586system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) 587system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) 588system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) 589system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) 590system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) 591system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) 592system.cpu.toL2Bus.snoops 0 # Total snoops (count) 593system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram |
| 594system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram | 594system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram |
| 595system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 596system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 597system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 599system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 595system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 596system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 597system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 599system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 600system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 602system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram | 600system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram |
| 604system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 602system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 605system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram | 603system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram |
| 607system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram 608system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) 609system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 610system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 611system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 612system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 613system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 614system.membus.trans_dist::ReadReq 3976 # Transaction distribution --- 10 unchanged lines hidden (view full) --- 625system.membus.snoop_fanout::stdev 0 # Request fanout histogram 626system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 627system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram 628system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 629system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 630system.membus.snoop_fanout::min_value 0 # Request fanout histogram 631system.membus.snoop_fanout::max_value 0 # Request fanout histogram 632system.membus.snoop_fanout::total 6833 # Request fanout histogram | 605system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram 606system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) 607system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 608system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 609system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 610system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 611system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 612system.membus.trans_dist::ReadReq 3976 # Transaction distribution --- 10 unchanged lines hidden (view full) --- 623system.membus.snoop_fanout::stdev 0 # Request fanout histogram 624system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 625system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram 626system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 627system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 628system.membus.snoop_fanout::min_value 0 # Request fanout histogram 629system.membus.snoop_fanout::max_value 0 # Request fanout histogram 630system.membus.snoop_fanout::total 6833 # Request fanout histogram |
| 633system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) | 631system.membus.reqLayer0.occupancy 7260500 # Layer occupancy (ticks) |
| 634system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 632system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 635system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) | 633system.membus.respLayer1.occupancy 34587500 # Layer occupancy (ticks) |
| 636system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 637 638---------- End Simulation Statistics ---------- | 634system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 635 636---------- End Simulation Statistics ---------- |