| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517235 # Number of seconds simulated 4sim_ticks 517235411000 # Number of ticks simulated 5final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517235 # Number of seconds simulated 4sim_ticks 517235411000 # Number of ticks simulated 5final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 795879 # Simulator instruction rate (inst/s) 8host_op_rate 955482 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1509341441 # Simulator tick rate (ticks/s) 10host_mem_usage 314596 # Number of bytes of host memory used 11host_seconds 342.69 # Real time elapsed on the host | 7host_inst_rate 761441 # Simulator instruction rate (inst/s) 8host_op_rate 914138 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1444030997 # Simulator tick rate (ticks/s) 10host_mem_usage 318052 # Number of bytes of host memory used 11host_seconds 358.19 # Real time elapsed on the host |
| 12sim_insts 272739285 # Number of instructions simulated 13sim_ops 327433743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory --- 4 unchanged lines hidden (view full) --- 24system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 272739285 # Number of instructions simulated 13sim_ops 327433743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory --- 4 unchanged lines hidden (view full) --- 24system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) |
| 32system.membus.trans_dist::ReadReq 3976 # Transaction distribution 33system.membus.trans_dist::ReadResp 3976 # Transaction distribution 34system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 35system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) 38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 39system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) 40system.membus.snoops 0 # Total snoops (count) 41system.membus.snoop_fanout::samples 6833 # Request fanout histogram 42system.membus.snoop_fanout::mean 0 # Request fanout histogram 43system.membus.snoop_fanout::stdev 0 # Request fanout histogram 44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram 46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::min_value 0 # Request fanout histogram 49system.membus.snoop_fanout::max_value 0 # Request fanout histogram 50system.membus.snoop_fanout::total 6833 # Request fanout histogram 51system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 53system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 0.0 # Layer utilization (%) | |
| 55system.cpu_clk_domain.clock 500 # Clock period in ticks | 32system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses | 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses 72system.cpu.dtb.read_hits 0 # DTB read hits 73system.cpu.dtb.read_misses 0 # DTB read misses 74system.cpu.dtb.write_hits 0 # DTB write hits 75system.cpu.dtb.write_misses 0 # DTB write misses 76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses |
| 91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 119system.cpu.itb.inst_hits 0 # ITB inst hits 120system.cpu.itb.inst_misses 0 # ITB inst misses 121system.cpu.itb.read_hits 0 # DTB read hits 122system.cpu.itb.read_misses 0 # DTB read misses 123system.cpu.itb.write_hits 0 # DTB write hits 124system.cpu.itb.write_misses 0 # DTB write misses 125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 66 unchanged lines hidden (view full) --- 193system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction 194system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 195system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 196system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 197system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 198system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 199system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 200system.cpu.op_class::total 327812213 # Class of executed instruction | 128system.cpu.itb.inst_hits 0 # ITB inst hits 129system.cpu.itb.inst_misses 0 # ITB inst misses 130system.cpu.itb.read_hits 0 # DTB read hits 131system.cpu.itb.read_misses 0 # DTB read misses 132system.cpu.itb.write_hits 0 # DTB write hits 133system.cpu.itb.write_misses 0 # DTB write misses 134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 66 unchanged lines hidden (view full) --- 202system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 205system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 206system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 327812213 # Class of executed instruction |
| 210system.cpu.dcache.tags.replacements 1332 # number of replacements 211system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 222system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 223system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 224system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 225system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 226system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses 227system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses 228system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits 229system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits 230system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 231system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 232system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits 233system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits 234system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 235system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 236system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 237system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 238system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits 239system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits 240system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits 241system.cpu.dcache.overall_hits::total 168337827 # number of overall hits 242system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses 243system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses 244system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 245system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 246system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 247system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 248system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses 249system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses 250system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses 251system.cpu.dcache.overall_misses::total 4479 # number of overall misses 252system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles 253system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles 254system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles 255system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles 256system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles 257system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles 258system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles 259system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles 260system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) 261system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) 262system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 263system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 264system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) 265system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) 266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 267system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 268system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 269system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 270system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses 271system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses 272system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses 273system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses 274system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses 275system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses 276system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 277system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 278system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses 279system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses 280system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses 281system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 282system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses 283system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 284system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency 285system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency 286system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency 287system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency 288system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency 289system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency 290system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency 291system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency 292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 298system.cpu.dcache.fast_writes 0 # number of fast writes performed 299system.cpu.dcache.cache_copies 0 # number of cache copies performed 300system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 301system.cpu.dcache.writebacks::total 998 # number of writebacks 302system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 303system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 304system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 305system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 306system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 307system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 308system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses 309system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses 310system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 311system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 312system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 313system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 314system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses 315system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses 316system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 317system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 318system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles 319system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles 320system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles 321system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles 322system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles 323system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles 324system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles 325system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles 326system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles 327system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles 328system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 329system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 330system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 331system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 332system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses 333system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses 334system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 335system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 336system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 337system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency 339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency 341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency 343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency 345system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency 347system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency 348system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 201system.cpu.icache.tags.replacements 13796 # number of replacements 202system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use 203system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. 204system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 205system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. 206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 207system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor 208system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy --- 216 unchanged lines hidden (view full) --- 425system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency 426system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency 427system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency 428system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency 429system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency 430system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency 431system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency 432system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 349system.cpu.icache.tags.replacements 13796 # number of replacements 350system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use 351system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. 352system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 353system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. 354system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 355system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor 356system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy --- 216 unchanged lines hidden (view full) --- 573system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency 574system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency 575system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency 576system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency 577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency 578system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency 579system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency 580system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 433system.cpu.dcache.tags.replacements 1332 # number of replacements 434system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use 435system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 436system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 437system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 438system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 439system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor 440system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy 441system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy 442system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 445system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 446system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 447system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 448system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 449system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses 450system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses 451system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits 452system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits 453system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 454system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 455system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits 456system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits 457system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 458system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 459system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 460system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 461system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits 462system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits 463system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits 464system.cpu.dcache.overall_hits::total 168337827 # number of overall hits 465system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses 466system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses 467system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 468system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 469system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 470system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 471system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses 472system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses 473system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses 474system.cpu.dcache.overall_misses::total 4479 # number of overall misses 475system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles 476system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles 477system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles 478system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles 479system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles 480system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles 481system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles 482system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles 483system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) 484system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) 485system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 486system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 487system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) 488system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) 489system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 490system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 491system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 492system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 493system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses 494system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses 495system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses 496system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses 497system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses 498system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses 499system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 500system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 501system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses 502system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses 503system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses 504system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 505system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses 506system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 507system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency 508system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency 509system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency 510system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency 511system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency 512system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency 513system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency 514system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency 515system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 516system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 517system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 518system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 519system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 520system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 521system.cpu.dcache.fast_writes 0 # number of fast writes performed 522system.cpu.dcache.cache_copies 0 # number of cache copies performed 523system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 524system.cpu.dcache.writebacks::total 998 # number of writebacks 525system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 526system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 527system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 528system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 529system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 530system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 531system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses 532system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses 533system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 534system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 535system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 536system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 537system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses 538system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses 539system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 540system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 541system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles 543system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles 544system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles 545system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles 546system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles 547system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles 548system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles 549system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles 550system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles 551system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 552system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 553system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 554system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 555system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses 556system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses 557system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 558system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 559system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 560system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency 562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency 563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency 564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency 565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency 566system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency 567system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency 568system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency 569system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency 570system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency 571system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 572system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution 573system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 577system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) 578system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) 579system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) --- 17 unchanged lines hidden (view full) --- 597system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram 599system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) 600system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 601system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 602system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 603system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 604system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 581system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution 582system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 583system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution 584system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 585system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 586system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) 587system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) 588system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) --- 17 unchanged lines hidden (view full) --- 606system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 607system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram 608system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) 609system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 610system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 611system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 612system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 613system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 614system.membus.trans_dist::ReadReq 3976 # Transaction distribution 615system.membus.trans_dist::ReadResp 3976 # Transaction distribution 616system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 617system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 618system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 619system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) 620system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 621system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) 622system.membus.snoops 0 # Total snoops (count) 623system.membus.snoop_fanout::samples 6833 # Request fanout histogram 624system.membus.snoop_fanout::mean 0 # Request fanout histogram 625system.membus.snoop_fanout::stdev 0 # Request fanout histogram 626system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 627system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram 628system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 629system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 630system.membus.snoop_fanout::min_value 0 # Request fanout histogram 631system.membus.snoop_fanout::max_value 0 # Request fanout histogram 632system.membus.snoop_fanout::total 6833 # Request fanout histogram 633system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) 634system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 635system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) 636system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
|
| 605 606---------- End Simulation Statistics ---------- | 637 638---------- End Simulation Statistics ---------- |