3,5c3,5
< sim_seconds 0.517291 # Number of seconds simulated
< sim_ticks 517291025500 # Number of ticks simulated
< final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.517298 # Number of seconds simulated
> sim_ticks 517297855500 # Number of ticks simulated
> final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 451771 # Simulator instruction rate (inst/s)
< host_op_rate 542368 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 856851233 # Simulator tick rate (ticks/s)
< host_mem_usage 273716 # Number of bytes of host memory used
< host_seconds 603.71 # Real time elapsed on the host
---
> host_inst_rate 565388 # Simulator instruction rate (inst/s)
> host_op_rate 678769 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1072356714 # Simulator tick rate (ticks/s)
> host_mem_usage 278352 # Number of bytes of host memory used
> host_seconds 482.39 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 322661 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 522593 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 845254 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 322661 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 322661 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 322661 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 522593 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 845254 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
65c65
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
95c95
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
125c125
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
156,157c156,157
< system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1034582051 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 517297855500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1034595711 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1034595710.998000 # Number of busy cycles
217c217
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
219c219
< system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3078.320204 # Cycle average of tags in use
224,226c224,226
< system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3078.320204 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.751543 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.751543 # Average percentage of cache occupancy
236c236
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
261,268c261,268
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 89418000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 89418000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 180278500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 180278500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 269696500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 269696500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 269696500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 269696500 # number of overall miss cycles
293,300c293,300
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55746.882793 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55746.882793 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62771.065460 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62771.065460 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 60253.909741 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 60253.909741 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 60213.552132 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 60213.552132 # average overall miss latency
325,334c325,334
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87767000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 87767000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177406500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 177406500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 186000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 186000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265173500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 265173500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265359500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 265359500 # number of overall MSHR miss cycles
345,355c345,355
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54751.715533 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54751.715533 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61771.065460 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61771.065460 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59256.648045 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 59256.648045 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59258.485931 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 59258.485931 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
357c357
< system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1765.939670 # Cycle average of tags in use
362,364c362,364
< system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1765.939670 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.862275 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.862275 # Average percentage of cache occupancy
374c374
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
387,392c387,392
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 341054000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 341054000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 341054000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 341054000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 341054000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 341054000 # number of overall miss cycles
405,410c405,410
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21858.232391 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 21858.232391 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 21858.232391 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 21858.232391 # average overall miss latency
425,430c425,430
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 325451000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 325451000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 325451000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 325451000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 325451000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 325451000 # number of overall MSHR miss cycles
437,443c437,443
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20858.232391 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
445,448c445,448
< system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 5901.352793 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 20712 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 6832 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 3.031616 # Average number of references to valid blocks.
450,466c450,464
< system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3494.038437 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073465 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.106630 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.180095 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 6832 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 758 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5967 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.208496 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 227184 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 227184 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
495,506c493,504
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172926500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 172926500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 157900000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 157900000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 82959000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 82959000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 157900000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 255885500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 413785500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 157900000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 255885500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 413785500 # number of overall miss cycles
535,546c533,544
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60548.494398 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60548.494398 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60544.478528 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60544.478528 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60642.543860 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60642.543860 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60565.793326 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60565.793326 # average overall miss latency
565,576c563,574
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 144366500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 144366500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 131820000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 131820000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69279000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69279000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131820000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 213645500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 345465500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131820000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 213645500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 345465500 # number of overall MSHR miss cycles
589,600c587,598
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50548.494398 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50548.494398 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50544.478528 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50544.478528 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50642.543860 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50642.543860 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency
607c605
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
641c639,645
< system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 6833 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
< sim_seconds 0.517291 # Number of seconds simulated
< sim_ticks 517291025500 # Number of ticks simulated
< final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.517298 # Number of seconds simulated
> sim_ticks 517297855500 # Number of ticks simulated
> final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 451771 # Simulator instruction rate (inst/s)
< host_op_rate 542368 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 856851233 # Simulator tick rate (ticks/s)
< host_mem_usage 273716 # Number of bytes of host memory used
< host_seconds 603.71 # Real time elapsed on the host
---
> host_inst_rate 565388 # Simulator instruction rate (inst/s)
> host_op_rate 678769 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1072356714 # Simulator tick rate (ticks/s)
> host_mem_usage 278352 # Number of bytes of host memory used
> host_seconds 482.39 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 322661 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 522593 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 845254 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 322661 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 322661 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 322661 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 522593 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 845254 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
65c65
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
95c95
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
125c125
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
156,157c156,157
< system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1034582051 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 517297855500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1034595711 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1034595710.998000 # Number of busy cycles
217c217
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
219c219
< system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3078.320204 # Cycle average of tags in use
224,226c224,226
< system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3078.320204 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.751543 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.751543 # Average percentage of cache occupancy
236c236
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
261,268c261,268
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 89418000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 89418000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 180278500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 180278500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 269696500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 269696500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 269696500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 269696500 # number of overall miss cycles
293,300c293,300
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55746.882793 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55746.882793 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62771.065460 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62771.065460 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 60253.909741 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 60253.909741 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 60213.552132 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 60213.552132 # average overall miss latency
325,334c325,334
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87767000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 87767000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177406500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 177406500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 186000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 186000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265173500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 265173500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265359500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 265359500 # number of overall MSHR miss cycles
345,355c345,355
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54751.715533 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54751.715533 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61771.065460 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61771.065460 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59256.648045 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 59256.648045 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59258.485931 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 59258.485931 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
357c357
< system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1765.939670 # Cycle average of tags in use
362,364c362,364
< system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1765.939670 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.862275 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.862275 # Average percentage of cache occupancy
374c374
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
387,392c387,392
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 341054000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 341054000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 341054000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 341054000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 341054000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 341054000 # number of overall miss cycles
405,410c405,410
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21858.232391 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 21858.232391 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 21858.232391 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 21858.232391 # average overall miss latency
425,430c425,430
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 325451000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 325451000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 325451000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 325451000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 325451000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 325451000 # number of overall MSHR miss cycles
437,443c437,443
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20858.232391 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
445,448c445,448
< system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 5901.352793 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 20712 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 6832 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 3.031616 # Average number of references to valid blocks.
450,466c450,464
< system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3494.038437 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073465 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.106630 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.180095 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 6832 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 758 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5967 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.208496 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 227184 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 227184 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
495,506c493,504
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172926500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 172926500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 157900000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 157900000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 82959000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 82959000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 157900000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 255885500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 413785500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 157900000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 255885500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 413785500 # number of overall miss cycles
535,546c533,544
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60548.494398 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60548.494398 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60544.478528 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60544.478528 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60642.543860 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60642.543860 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60565.793326 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60565.793326 # average overall miss latency
565,576c563,574
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 144366500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 144366500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 131820000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 131820000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69279000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69279000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131820000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 213645500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 345465500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131820000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 213645500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 345465500 # number of overall MSHR miss cycles
589,600c587,598
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50548.494398 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50548.494398 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50544.478528 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50544.478528 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50642.543860 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50642.543860 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency
607c605
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
641c639,645
< system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 6833 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states