3,5c3,5
< sim_seconds 0.517235 # Number of seconds simulated
< sim_ticks 517235407500 # Number of ticks simulated
< final_tick 517235407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.517243 # Number of seconds simulated
> sim_ticks 517243165500 # Number of ticks simulated
> final_tick 517243165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 785915 # Simulator instruction rate (inst/s)
< host_op_rate 943520 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1490444540 # Simulator tick rate (ticks/s)
< host_mem_usage 321320 # Number of bytes of host memory used
< host_seconds 347.03 # Real time elapsed on the host
---
> host_inst_rate 702843 # Simulator instruction rate (inst/s)
> host_op_rate 843789 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1332923086 # Simulator tick rate (ticks/s)
> host_mem_usage 322968 # Number of bytes of host memory used
> host_seconds 388.05 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 322700 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 522656 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 322700 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 322700 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 322700 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 522656 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 322695 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 522648 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 845343 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 322695 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 322695 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 322695 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 522648 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 845343 # Total bandwidth to/from this memory (bytes/s)
150c150
< system.cpu.numCycles 1034470815 # number of cpu cycles simulated
---
> system.cpu.numCycles 1034486331 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 1034470814.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1034486330.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 3078.445031 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3078.444355 # Cycle average of tags in use
216c216
< system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445031 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3078.444355 # Average occupied blocks per requestor
252,253c252,253
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 78396000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 78396000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 78469000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 78469000 # number of ReadReq miss cycles
256,259c256,259
< system.cpu.dcache.demand_miss_latency::cpu.data 235819500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 235819500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 235819500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 235819500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 235892500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 235892500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 235892500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 235892500 # number of overall miss cycles
284,285c284,285
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48920.822943 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 48920.822943 # average ReadReq miss latency
288,291c288,291
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.321716 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 52685.321716 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 52650.033490 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 52650.033490 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 52701.630920 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 52701.630920 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 52666.331770 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 52666.331770 # average overall miss latency
318,319c318,319
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76753000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 76753000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76826000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 76826000 # number of ReadReq MSHR miss cycles
324,327c324,327
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231304500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 231304500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231466500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 231466500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231377500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 231377500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231539500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 231539500 # number of overall MSHR miss cycles
338,339c338,339
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47880.848409 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47880.848409 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47926.388022 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47926.388022 # average ReadReq mshr miss latency
344,347c344,347
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51688.156425 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 51688.156425 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51689.705226 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 51689.705226 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51704.469274 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 51704.469274 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51706.007146 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 51706.007146 # average overall mshr miss latency
350c350
< system.cpu.icache.tags.tagsinuse 1766.007653 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1766.007280 # Cycle average of tags in use
355c355
< system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007653 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007280 # Average occupied blocks per requestor
379,384c379,384
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 312483000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 312483000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 312483000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 312483000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 312483000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 312483000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 320168000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 320168000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 320168000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 320168000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 320168000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 320168000 # number of overall miss cycles
397,402c397,402
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.110171 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20027.110171 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20027.110171 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20027.110171 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20519.643658 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20519.643658 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20519.643658 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20519.643658 # average overall miss latency
417,422c417,422
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296880000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 296880000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296880000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 296880000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296880000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 296880000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304565000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 304565000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304565000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 304565000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304565000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 304565000 # number of overall MSHR miss cycles
429,434c429,434
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19027.110171 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19027.110171 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19519.643658 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19519.643658 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency
437c437
< system.cpu.l2cache.tags.tagsinuse 3487.764994 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 3487.764139 # Cycle average of tags in use
442,444c442,444
< system.cpu.l2cache.tags.occ_blocks::writebacks 341.623058 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427152 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714783 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 341.622938 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.426609 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714591 # Average occupied blocks per requestor
590a591,596
> system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
606,607c612,613
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.438041 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.496153 # Request fanout histogram
609,610c615,616
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 35209 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 19786 56.20% 56.20% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 15423 43.80% 100.00% # Request fanout histogram
613c619
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_seconds 0.517235 # Number of seconds simulated
< sim_ticks 517235407500 # Number of ticks simulated
< final_tick 517235407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.517243 # Number of seconds simulated
> sim_ticks 517243165500 # Number of ticks simulated
> final_tick 517243165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 785915 # Simulator instruction rate (inst/s)
< host_op_rate 943520 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1490444540 # Simulator tick rate (ticks/s)
< host_mem_usage 321320 # Number of bytes of host memory used
< host_seconds 347.03 # Real time elapsed on the host
---
> host_inst_rate 702843 # Simulator instruction rate (inst/s)
> host_op_rate 843789 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1332923086 # Simulator tick rate (ticks/s)
> host_mem_usage 322968 # Number of bytes of host memory used
> host_seconds 388.05 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 322700 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 522656 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 322700 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 322700 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 322700 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 522656 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 322695 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 522648 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 845343 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 322695 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 322695 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 322695 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 522648 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 845343 # Total bandwidth to/from this memory (bytes/s)
150c150
< system.cpu.numCycles 1034470815 # number of cpu cycles simulated
---
> system.cpu.numCycles 1034486331 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 1034470814.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1034486330.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 3078.445031 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3078.444355 # Cycle average of tags in use
216c216
< system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445031 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3078.444355 # Average occupied blocks per requestor
252,253c252,253
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 78396000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 78396000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 78469000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 78469000 # number of ReadReq miss cycles
256,259c256,259
< system.cpu.dcache.demand_miss_latency::cpu.data 235819500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 235819500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 235819500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 235819500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 235892500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 235892500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 235892500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 235892500 # number of overall miss cycles
284,285c284,285
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48920.822943 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 48920.822943 # average ReadReq miss latency
288,291c288,291
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.321716 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 52685.321716 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 52650.033490 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 52650.033490 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 52701.630920 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 52701.630920 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 52666.331770 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 52666.331770 # average overall miss latency
318,319c318,319
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76753000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 76753000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76826000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 76826000 # number of ReadReq MSHR miss cycles
324,327c324,327
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231304500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 231304500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231466500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 231466500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231377500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 231377500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231539500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 231539500 # number of overall MSHR miss cycles
338,339c338,339
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47880.848409 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47880.848409 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47926.388022 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47926.388022 # average ReadReq mshr miss latency
344,347c344,347
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51688.156425 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 51688.156425 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51689.705226 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 51689.705226 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51704.469274 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 51704.469274 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51706.007146 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 51706.007146 # average overall mshr miss latency
350c350
< system.cpu.icache.tags.tagsinuse 1766.007653 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1766.007280 # Cycle average of tags in use
355c355
< system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007653 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007280 # Average occupied blocks per requestor
379,384c379,384
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 312483000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 312483000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 312483000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 312483000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 312483000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 312483000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 320168000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 320168000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 320168000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 320168000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 320168000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 320168000 # number of overall miss cycles
397,402c397,402
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.110171 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20027.110171 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20027.110171 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20027.110171 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20519.643658 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20519.643658 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20519.643658 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20519.643658 # average overall miss latency
417,422c417,422
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296880000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 296880000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296880000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 296880000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296880000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 296880000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304565000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 304565000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304565000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 304565000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304565000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 304565000 # number of overall MSHR miss cycles
429,434c429,434
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19027.110171 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19027.110171 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19519.643658 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19519.643658 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency
437c437
< system.cpu.l2cache.tags.tagsinuse 3487.764994 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 3487.764139 # Cycle average of tags in use
442,444c442,444
< system.cpu.l2cache.tags.occ_blocks::writebacks 341.623058 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427152 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714783 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 341.622938 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.426609 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714591 # Average occupied blocks per requestor
590a591,596
> system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
606,607c612,613
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.438041 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.496153 # Request fanout histogram
609,610c615,616
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 35209 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 19786 56.20% 56.20% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 15423 43.80% 100.00% # Request fanout histogram
613c619
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram