4,5c4,5
< sim_ticks 517235411000 # Number of ticks simulated
< final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 517235404500 # Number of ticks simulated
> final_tick 517235404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 761441 # Simulator instruction rate (inst/s)
< host_op_rate 914138 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1444030997 # Simulator tick rate (ticks/s)
< host_mem_usage 318052 # Number of bytes of host memory used
< host_seconds 358.19 # Real time elapsed on the host
---
> host_inst_rate 693666 # Simulator instruction rate (inst/s)
> host_op_rate 832772 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1315500911 # Simulator tick rate (ticks/s)
> host_mem_usage 318184 # Number of bytes of host memory used
> host_seconds 393.19 # Real time elapsed on the host
150c150
< system.cpu.numCycles 1034470822 # number of cpu cycles simulated
---
> system.cpu.numCycles 1034470809 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 1034470821.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1034470808.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3078.445039 # Cycle average of tags in use
216c216
< system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445039 # Average occupied blocks per requestor
254,259c254,259
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 235776500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 235776500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 235776500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 235776500 # number of overall miss cycles
286,291c286,291
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 52675.714924 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 52675.714924 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 52640.433132 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 52640.433132 # average overall miss latency
318,327c318,327
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75909500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 75909500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229024000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 229024000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229184500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 229184500 # number of overall MSHR miss cycles
338,347c338,347
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47354.647536 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47354.647536 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51178.547486 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 51178.547486 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51180.102724 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 51180.102724 # average overall mshr miss latency
350c350
< system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1766.007658 # Cycle average of tags in use
355c355
< system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007658 # Average occupied blocks per requestor
379,384c379,384
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 312524000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 312524000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 312524000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 312524000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 312524000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 312524000 # number of overall miss cycles
397,402c397,402
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.737871 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20029.737871 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20029.737871 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20029.737871 # average overall miss latency
417,422c417,422
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 289119500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 289119500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 289119500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 289119500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 289119500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 289119500 # number of overall MSHR miss cycles
429,434c429,434
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18529.737871 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18529.737871 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency
437c437
< system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 3487.765017 # Cycle average of tags in use
442,444c442,444
< system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 341.623060 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427163 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714793 # Average occupied blocks per requestor
482,492c482,492
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137079500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71954500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 209034000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150074500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 150074500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 137079500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 222029000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 359108500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 137079500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 222029000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 359108500 # number of overall miss cycles
517,527c517,527
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.011882 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.795903 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555 # average overall miss latency
547,557c547,557
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105665500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55363500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105665500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171031500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105665500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171031500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles
569,579c569,579
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383289 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency
594c594
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
600,603c600,601
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
605,606c603,604
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
633c631
< system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 7260500 # Layer occupancy (ticks)
635c633
< system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 34587500 # Layer occupancy (ticks)
< sim_ticks 517235411000 # Number of ticks simulated
< final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 517235404500 # Number of ticks simulated
> final_tick 517235404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 761441 # Simulator instruction rate (inst/s)
< host_op_rate 914138 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1444030997 # Simulator tick rate (ticks/s)
< host_mem_usage 318052 # Number of bytes of host memory used
< host_seconds 358.19 # Real time elapsed on the host
---
> host_inst_rate 693666 # Simulator instruction rate (inst/s)
> host_op_rate 832772 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1315500911 # Simulator tick rate (ticks/s)
> host_mem_usage 318184 # Number of bytes of host memory used
> host_seconds 393.19 # Real time elapsed on the host
150c150
< system.cpu.numCycles 1034470822 # number of cpu cycles simulated
---
> system.cpu.numCycles 1034470809 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 1034470821.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1034470808.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3078.445039 # Cycle average of tags in use
216c216
< system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445039 # Average occupied blocks per requestor
254,259c254,259
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 235776500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 235776500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 235776500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 235776500 # number of overall miss cycles
286,291c286,291
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 52675.714924 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 52675.714924 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 52640.433132 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 52640.433132 # average overall miss latency
318,327c318,327
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75909500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 75909500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229024000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 229024000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229184500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 229184500 # number of overall MSHR miss cycles
338,347c338,347
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47354.647536 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47354.647536 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51178.547486 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 51178.547486 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51180.102724 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 51180.102724 # average overall mshr miss latency
350c350
< system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1766.007658 # Cycle average of tags in use
355c355
< system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007658 # Average occupied blocks per requestor
379,384c379,384
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 312524000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 312524000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 312524000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 312524000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 312524000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 312524000 # number of overall miss cycles
397,402c397,402
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.737871 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20029.737871 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20029.737871 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20029.737871 # average overall miss latency
417,422c417,422
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 289119500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 289119500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 289119500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 289119500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 289119500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 289119500 # number of overall MSHR miss cycles
429,434c429,434
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18529.737871 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18529.737871 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency
437c437
< system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 3487.765017 # Cycle average of tags in use
442,444c442,444
< system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 341.623060 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427163 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714793 # Average occupied blocks per requestor
482,492c482,492
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137079500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71954500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 209034000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150074500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 150074500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 137079500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 222029000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 359108500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 137079500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 222029000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 359108500 # number of overall miss cycles
517,527c517,527
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.011882 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.795903 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555 # average overall miss latency
547,557c547,557
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105665500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55363500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105665500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171031500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105665500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171031500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles
569,579c569,579
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383289 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency
594c594
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
600,603c600,601
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
605,606c603,604
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
633c631
< system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 7260500 # Layer occupancy (ticks)
635c633
< system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 34587500 # Layer occupancy (ticks)