3,5c3,5
< sim_seconds 0.525834 # Number of seconds simulated
< sim_ticks 525834342000 # Number of ticks simulated
< final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.517235 # Number of seconds simulated
> sim_ticks 517235411000 # Number of ticks simulated
> final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 605985 # Simulator instruction rate (inst/s)
< host_op_rate 774729 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1168322503 # Simulator tick rate (ticks/s)
< host_mem_usage 318808 # Number of bytes of host memory used
< host_seconds 450.08 # Real time elapsed on the host
< sim_insts 272739283 # Number of instructions simulated
< sim_ops 348687122 # Number of ops (including micro ops) simulated
---
> host_inst_rate 749544 # Simulator instruction rate (inst/s)
> host_op_rate 899855 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1421469107 # Simulator tick rate (ticks/s)
> host_mem_usage 324416 # Number of bytes of host memory used
> host_seconds 363.87 # Real time elapsed on the host
> sim_insts 272739285 # Number of instructions simulated
> sim_ops 327433743 # Number of ops (including micro ops) simulated
24,32c24,32
< system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s)
< system.membus.throughput 831532 # Throughput (bytes/s)
---
> system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
> system.membus.throughput 845356 # Throughput (bytes/s)
43c43
< system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
45c45
< system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
133c133
< system.cpu.numCycles 1051668684 # number of cpu cycles simulated
---
> system.cpu.numCycles 1034470822 # number of cpu cycles simulated
136,138c136,138
< system.cpu.committedInsts 272739283 # Number of instructions committed
< system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses
---
> system.cpu.committedInsts 272739285 # Number of instructions committed
> system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
141,142c141,142
< system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls
< system.cpu.num_int_insts 279584917 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
> system.cpu.num_int_insts 258331537 # number of integer instructions
144,145c144,145
< system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read
< system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
> system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
148,149c148,151
< system.cpu.num_mem_refs 177024356 # number of memory refs
< system.cpu.num_load_insts 94648757 # Number of load instructions
---
> system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
> system.cpu.num_mem_refs 168107847 # number of memory refs
> system.cpu.num_load_insts 85732248 # Number of load instructions
152c154
< system.cpu.num_busy_cycles 1051668684 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1034470822 # Number of busy cycles
155c157
< system.cpu.Branches 30563501 # Number of branches fetched
---
> system.cpu.Branches 30563502 # Number of branches fetched
157,187c159,189
< system.cpu.op_class::IntAlu 116649413 33.42% 33.42% # Class of executed instruction
< system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction
< system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction
< system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction
< system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction
< system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction
< system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction
< system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction
< system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction
< system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction
< system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction
< system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction
< system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction
> system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
> system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
> system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
> system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
> system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
> system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
> system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
> system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
> system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
> system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
> system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
190c192
< system.cpu.op_class::total 349065592 # Class of executed instruction
---
> system.cpu.op_class::total 327812213 # Class of executed instruction
192,193c194,195
< system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks.
195c197
< system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks.
197,199c199,201
< system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy
207,214c209,216
< system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits
< system.cpu.icache.overall_hits::total 348644747 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits
> system.cpu.icache.overall_hits::total 348644749 # number of overall hits
221,232c223,234
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses
239,244c241,246
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency
259,264c261,266
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles
271,276c273,278
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
279c281
< system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use
284,287c286,289
< system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy
290c292
< system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy
324,334c326,336
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles
359,369c361,371
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency
389c391
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles
391,399c393,401
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles
411c413
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency
413,421c415,423
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
424,425c426,427
< system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
427c429
< system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
429,431c431,433
< system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy
434,435c436,437
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
439,442c441,444
< system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
444a447,448
> system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
449,454c453,458
< system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits
< system.cpu.dcache.overall_hits::total 176619809 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
> system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
457,470c461,476
< system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
< system.cpu.dcache.overall_misses::total 4478 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
> system.cpu.dcache.overall_misses::total 4479 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
472a479,480
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
477,482c485,490
< system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
485,496c493,506
< system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency
---
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency
507,508c517,524
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
511,512c527,530
< system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses
---
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
515,524c533,544
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
527,538c547,562
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
540c564
< system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s)
< sim_seconds 0.525834 # Number of seconds simulated
< sim_ticks 525834342000 # Number of ticks simulated
< final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.517235 # Number of seconds simulated
> sim_ticks 517235411000 # Number of ticks simulated
> final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 605985 # Simulator instruction rate (inst/s)
< host_op_rate 774729 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1168322503 # Simulator tick rate (ticks/s)
< host_mem_usage 318808 # Number of bytes of host memory used
< host_seconds 450.08 # Real time elapsed on the host
< sim_insts 272739283 # Number of instructions simulated
< sim_ops 348687122 # Number of ops (including micro ops) simulated
---
> host_inst_rate 749544 # Simulator instruction rate (inst/s)
> host_op_rate 899855 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1421469107 # Simulator tick rate (ticks/s)
> host_mem_usage 324416 # Number of bytes of host memory used
> host_seconds 363.87 # Real time elapsed on the host
> sim_insts 272739285 # Number of instructions simulated
> sim_ops 327433743 # Number of ops (including micro ops) simulated
24,32c24,32
< system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s)
< system.membus.throughput 831532 # Throughput (bytes/s)
---
> system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
> system.membus.throughput 845356 # Throughput (bytes/s)
43c43
< system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
45c45
< system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
133c133
< system.cpu.numCycles 1051668684 # number of cpu cycles simulated
---
> system.cpu.numCycles 1034470822 # number of cpu cycles simulated
136,138c136,138
< system.cpu.committedInsts 272739283 # Number of instructions committed
< system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses
---
> system.cpu.committedInsts 272739285 # Number of instructions committed
> system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
141,142c141,142
< system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls
< system.cpu.num_int_insts 279584917 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
> system.cpu.num_int_insts 258331537 # number of integer instructions
144,145c144,145
< system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read
< system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
> system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
148,149c148,151
< system.cpu.num_mem_refs 177024356 # number of memory refs
< system.cpu.num_load_insts 94648757 # Number of load instructions
---
> system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
> system.cpu.num_mem_refs 168107847 # number of memory refs
> system.cpu.num_load_insts 85732248 # Number of load instructions
152c154
< system.cpu.num_busy_cycles 1051668684 # Number of busy cycles
---
> system.cpu.num_busy_cycles 1034470822 # Number of busy cycles
155c157
< system.cpu.Branches 30563501 # Number of branches fetched
---
> system.cpu.Branches 30563502 # Number of branches fetched
157,187c159,189
< system.cpu.op_class::IntAlu 116649413 33.42% 33.42% # Class of executed instruction
< system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction
< system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction
< system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction
< system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction
< system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction
< system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction
< system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction
< system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction
< system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction
< system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction
< system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction
< system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction
< system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction
> system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
> system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
> system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
> system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
> system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
> system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
> system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
> system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
> system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
> system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
> system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
> system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
190c192
< system.cpu.op_class::total 349065592 # Class of executed instruction
---
> system.cpu.op_class::total 327812213 # Class of executed instruction
192,193c194,195
< system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks.
195c197
< system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks.
197,199c199,201
< system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy
207,214c209,216
< system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits
< system.cpu.icache.overall_hits::total 348644747 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits
> system.cpu.icache.overall_hits::total 348644749 # number of overall hits
221,232c223,234
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses
239,244c241,246
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency
259,264c261,266
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles
271,276c273,278
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
279c281
< system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use
284,287c286,289
< system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy
290c292
< system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy
324,334c326,336
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles
359,369c361,371
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency
389c391
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles
391,399c393,401
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles
411c413
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency
413,421c415,423
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
424,425c426,427
< system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
427c429
< system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
429,431c431,433
< system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy
434,435c436,437
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
439,442c441,444
< system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
444a447,448
> system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
449,454c453,458
< system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits
< system.cpu.dcache.overall_hits::total 176619809 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
> system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
457,470c461,476
< system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
< system.cpu.dcache.overall_misses::total 4478 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
> system.cpu.dcache.overall_misses::total 4479 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
472a479,480
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
477,482c485,490
< system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
485,496c493,506
< system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency
---
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency
507,508c517,524
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
511,512c527,530
< system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses
---
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
515,524c533,544
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
527,538c547,562
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
540c564
< system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s)