1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.525854 # Number of seconds simulated
4sim_ticks 525854475000 # Number of ticks simulated
5final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.525854 # Number of seconds simulated
4sim_ticks 525854475000 # Number of ticks simulated
5final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1189484 # Simulator instruction rate (inst/s)
8host_op_rate 1520711 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2293381880 # Simulator tick rate (ticks/s)
10host_mem_usage 230756 # Number of bytes of host memory used
11host_seconds 229.29 # Real time elapsed on the host
| 7host_inst_rate 425859 # Simulator instruction rate (inst/s)
8host_op_rate 544445 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 821076045 # Simulator tick rate (ticks/s)
10host_mem_usage 237820 # Number of bytes of host memory used
11host_seconds 640.45 # Real time elapsed on the host
|
12sim_insts 272739291 # Number of instructions simulated
13sim_ops 348687131 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 437312 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 6833 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 831622 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 317654 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 831622 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.inst_hits 0 # ITB inst hits
24system.cpu.dtb.inst_misses 0 # ITB inst misses
25system.cpu.dtb.read_hits 0 # DTB read hits
26system.cpu.dtb.read_misses 0 # DTB read misses
27system.cpu.dtb.write_hits 0 # DTB write hits
28system.cpu.dtb.write_misses 0 # DTB write misses
29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
31system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
32system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
33system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
34system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
35system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
36system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
37system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
38system.cpu.dtb.read_accesses 0 # DTB read accesses
39system.cpu.dtb.write_accesses 0 # DTB write accesses
40system.cpu.dtb.inst_accesses 0 # ITB inst accesses
41system.cpu.dtb.hits 0 # DTB hits
42system.cpu.dtb.misses 0 # DTB misses
43system.cpu.dtb.accesses 0 # DTB accesses
44system.cpu.itb.inst_hits 0 # ITB inst hits
45system.cpu.itb.inst_misses 0 # ITB inst misses
46system.cpu.itb.read_hits 0 # DTB read hits
47system.cpu.itb.read_misses 0 # DTB read misses
48system.cpu.itb.write_hits 0 # DTB write hits
49system.cpu.itb.write_misses 0 # DTB write misses
50system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
51system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
52system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
53system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
54system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
55system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
56system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
57system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.itb.read_accesses 0 # DTB read accesses
60system.cpu.itb.write_accesses 0 # DTB write accesses
61system.cpu.itb.inst_accesses 0 # ITB inst accesses
62system.cpu.itb.hits 0 # DTB hits
63system.cpu.itb.misses 0 # DTB misses
64system.cpu.itb.accesses 0 # DTB accesses
65system.cpu.workload.num_syscalls 191 # Number of system calls
66system.cpu.numCycles 1051708950 # number of cpu cycles simulated
67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
69system.cpu.committedInsts 272739291 # Number of instructions committed
70system.cpu.committedOps 348687131 # Number of ops (including micro ops) committed
71system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses
72system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
73system.cpu.num_func_calls 12433363 # number of times a function call or return occured
74system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls
75system.cpu.num_int_insts 279584925 # number of integer instructions
76system.cpu.num_fp_insts 114216705 # number of float instructions
77system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read
78system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written
79system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
80system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
81system.cpu.num_mem_refs 177024357 # number of memory refs
82system.cpu.num_load_insts 94648758 # Number of load instructions
83system.cpu.num_store_insts 82375599 # Number of store instructions
84system.cpu.num_idle_cycles 0 # Number of idle cycles
85system.cpu.num_busy_cycles 1051708950 # Number of busy cycles
86system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
87system.cpu.idle_fraction 0 # Percentage of idle cycles
88system.cpu.icache.replacements 13796 # number of replacements
89system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use
90system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks.
91system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
92system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks.
93system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
94system.cpu.icache.occ_blocks::cpu.inst 1765.984158 # Average occupied blocks per requestor
95system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy
96system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy
97system.cpu.icache.ReadReq_hits::cpu.inst 348644756 # number of ReadReq hits
98system.cpu.icache.ReadReq_hits::total 348644756 # number of ReadReq hits
99system.cpu.icache.demand_hits::cpu.inst 348644756 # number of demand (read+write) hits
100system.cpu.icache.demand_hits::total 348644756 # number of demand (read+write) hits
101system.cpu.icache.overall_hits::cpu.inst 348644756 # number of overall hits
102system.cpu.icache.overall_hits::total 348644756 # number of overall hits
103system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
104system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
105system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
106system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
107system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
108system.cpu.icache.overall_misses::total 15603 # number of overall misses
109system.cpu.icache.ReadReq_miss_latency::cpu.inst 328062000 # number of ReadReq miss cycles
110system.cpu.icache.ReadReq_miss_latency::total 328062000 # number of ReadReq miss cycles
111system.cpu.icache.demand_miss_latency::cpu.inst 328062000 # number of demand (read+write) miss cycles
112system.cpu.icache.demand_miss_latency::total 328062000 # number of demand (read+write) miss cycles
113system.cpu.icache.overall_miss_latency::cpu.inst 328062000 # number of overall miss cycles
114system.cpu.icache.overall_miss_latency::total 328062000 # number of overall miss cycles
115system.cpu.icache.ReadReq_accesses::cpu.inst 348660359 # number of ReadReq accesses(hits+misses)
116system.cpu.icache.ReadReq_accesses::total 348660359 # number of ReadReq accesses(hits+misses)
117system.cpu.icache.demand_accesses::cpu.inst 348660359 # number of demand (read+write) accesses
118system.cpu.icache.demand_accesses::total 348660359 # number of demand (read+write) accesses
119system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses
120system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses
121system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
122system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
123system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
124system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency
125system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency
126system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency
127system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
128system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
129system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
130system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
| 12sim_insts 272739291 # Number of instructions simulated
13sim_ops 348687131 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 437312 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 6833 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 831622 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 317654 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 831622 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.inst_hits 0 # ITB inst hits
24system.cpu.dtb.inst_misses 0 # ITB inst misses
25system.cpu.dtb.read_hits 0 # DTB read hits
26system.cpu.dtb.read_misses 0 # DTB read misses
27system.cpu.dtb.write_hits 0 # DTB write hits
28system.cpu.dtb.write_misses 0 # DTB write misses
29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
31system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
32system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
33system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
34system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
35system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
36system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
37system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
38system.cpu.dtb.read_accesses 0 # DTB read accesses
39system.cpu.dtb.write_accesses 0 # DTB write accesses
40system.cpu.dtb.inst_accesses 0 # ITB inst accesses
41system.cpu.dtb.hits 0 # DTB hits
42system.cpu.dtb.misses 0 # DTB misses
43system.cpu.dtb.accesses 0 # DTB accesses
44system.cpu.itb.inst_hits 0 # ITB inst hits
45system.cpu.itb.inst_misses 0 # ITB inst misses
46system.cpu.itb.read_hits 0 # DTB read hits
47system.cpu.itb.read_misses 0 # DTB read misses
48system.cpu.itb.write_hits 0 # DTB write hits
49system.cpu.itb.write_misses 0 # DTB write misses
50system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
51system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
52system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
53system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
54system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
55system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
56system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
57system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.itb.read_accesses 0 # DTB read accesses
60system.cpu.itb.write_accesses 0 # DTB write accesses
61system.cpu.itb.inst_accesses 0 # ITB inst accesses
62system.cpu.itb.hits 0 # DTB hits
63system.cpu.itb.misses 0 # DTB misses
64system.cpu.itb.accesses 0 # DTB accesses
65system.cpu.workload.num_syscalls 191 # Number of system calls
66system.cpu.numCycles 1051708950 # number of cpu cycles simulated
67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
69system.cpu.committedInsts 272739291 # Number of instructions committed
70system.cpu.committedOps 348687131 # Number of ops (including micro ops) committed
71system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses
72system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
73system.cpu.num_func_calls 12433363 # number of times a function call or return occured
74system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls
75system.cpu.num_int_insts 279584925 # number of integer instructions
76system.cpu.num_fp_insts 114216705 # number of float instructions
77system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read
78system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written
79system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
80system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
81system.cpu.num_mem_refs 177024357 # number of memory refs
82system.cpu.num_load_insts 94648758 # Number of load instructions
83system.cpu.num_store_insts 82375599 # Number of store instructions
84system.cpu.num_idle_cycles 0 # Number of idle cycles
85system.cpu.num_busy_cycles 1051708950 # Number of busy cycles
86system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
87system.cpu.idle_fraction 0 # Percentage of idle cycles
88system.cpu.icache.replacements 13796 # number of replacements
89system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use
90system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks.
91system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
92system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks.
93system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
94system.cpu.icache.occ_blocks::cpu.inst 1765.984158 # Average occupied blocks per requestor
95system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy
96system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy
97system.cpu.icache.ReadReq_hits::cpu.inst 348644756 # number of ReadReq hits
98system.cpu.icache.ReadReq_hits::total 348644756 # number of ReadReq hits
99system.cpu.icache.demand_hits::cpu.inst 348644756 # number of demand (read+write) hits
100system.cpu.icache.demand_hits::total 348644756 # number of demand (read+write) hits
101system.cpu.icache.overall_hits::cpu.inst 348644756 # number of overall hits
102system.cpu.icache.overall_hits::total 348644756 # number of overall hits
103system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
104system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
105system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
106system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
107system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
108system.cpu.icache.overall_misses::total 15603 # number of overall misses
109system.cpu.icache.ReadReq_miss_latency::cpu.inst 328062000 # number of ReadReq miss cycles
110system.cpu.icache.ReadReq_miss_latency::total 328062000 # number of ReadReq miss cycles
111system.cpu.icache.demand_miss_latency::cpu.inst 328062000 # number of demand (read+write) miss cycles
112system.cpu.icache.demand_miss_latency::total 328062000 # number of demand (read+write) miss cycles
113system.cpu.icache.overall_miss_latency::cpu.inst 328062000 # number of overall miss cycles
114system.cpu.icache.overall_miss_latency::total 328062000 # number of overall miss cycles
115system.cpu.icache.ReadReq_accesses::cpu.inst 348660359 # number of ReadReq accesses(hits+misses)
116system.cpu.icache.ReadReq_accesses::total 348660359 # number of ReadReq accesses(hits+misses)
117system.cpu.icache.demand_accesses::cpu.inst 348660359 # number of demand (read+write) accesses
118system.cpu.icache.demand_accesses::total 348660359 # number of demand (read+write) accesses
119system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses
120system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses
121system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
122system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
123system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
124system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency
125system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency
126system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency
127system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
128system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
129system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
130system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
131system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
132system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 131system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
132system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
133system.cpu.icache.fast_writes 0 # number of fast writes performed
134system.cpu.icache.cache_copies 0 # number of cache copies performed
135system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
136system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
137system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
138system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
139system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
140system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
141system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281253000 # number of ReadReq MSHR miss cycles
142system.cpu.icache.ReadReq_mshr_miss_latency::total 281253000 # number of ReadReq MSHR miss cycles
143system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281253000 # number of demand (read+write) MSHR miss cycles
144system.cpu.icache.demand_mshr_miss_latency::total 281253000 # number of demand (read+write) MSHR miss cycles
145system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles
146system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles
147system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
148system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
149system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
150system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency
151system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency
152system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency
153system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
154system.cpu.dcache.replacements 1332 # number of replacements
155system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use
156system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks.
157system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
158system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks.
159system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
160system.cpu.dcache.occ_blocks::cpu.data 3078.396238 # Average occupied blocks per requestor
161system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy
162system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy
163system.cpu.dcache.ReadReq_hits::cpu.data 94570005 # number of ReadReq hits
164system.cpu.dcache.ReadReq_hits::total 94570005 # number of ReadReq hits
165system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
166system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
167system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
168system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
169system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
170system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
171system.cpu.dcache.demand_hits::cpu.data 176619810 # number of demand (read+write) hits
172system.cpu.dcache.demand_hits::total 176619810 # number of demand (read+write) hits
173system.cpu.dcache.overall_hits::cpu.data 176619810 # number of overall hits
174system.cpu.dcache.overall_hits::total 176619810 # number of overall hits
175system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses
176system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses
177system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
178system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
179system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses
180system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
181system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
182system.cpu.dcache.overall_misses::total 4478 # number of overall misses
183system.cpu.dcache.ReadReq_miss_latency::cpu.data 79898000 # number of ReadReq miss cycles
184system.cpu.dcache.ReadReq_miss_latency::total 79898000 # number of ReadReq miss cycles
185system.cpu.dcache.WriteReq_miss_latency::cpu.data 160160000 # number of WriteReq miss cycles
186system.cpu.dcache.WriteReq_miss_latency::total 160160000 # number of WriteReq miss cycles
187system.cpu.dcache.demand_miss_latency::cpu.data 240058000 # number of demand (read+write) miss cycles
188system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles
189system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles
190system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles
191system.cpu.dcache.ReadReq_accesses::cpu.data 94571611 # number of ReadReq accesses(hits+misses)
192system.cpu.dcache.ReadReq_accesses::total 94571611 # number of ReadReq accesses(hits+misses)
193system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
194system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
195system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
196system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
197system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
198system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
199system.cpu.dcache.demand_accesses::cpu.data 176624288 # number of demand (read+write) accesses
200system.cpu.dcache.demand_accesses::total 176624288 # number of demand (read+write) accesses
201system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses
202system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses
203system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
204system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
205system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
206system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
207system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency
208system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency
209system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency
210system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency
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212system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
213system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
214system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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134system.cpu.icache.cache_copies 0 # number of cache copies performed
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136system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
137system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
138system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
139system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
140system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
141system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281253000 # number of ReadReq MSHR miss cycles
142system.cpu.icache.ReadReq_mshr_miss_latency::total 281253000 # number of ReadReq MSHR miss cycles
143system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281253000 # number of demand (read+write) MSHR miss cycles
144system.cpu.icache.demand_mshr_miss_latency::total 281253000 # number of demand (read+write) MSHR miss cycles
145system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles
146system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles
147system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
148system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
149system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
150system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency
151system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency
152system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency
153system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
154system.cpu.dcache.replacements 1332 # number of replacements
155system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use
156system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks.
157system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
158system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks.
159system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
160system.cpu.dcache.occ_blocks::cpu.data 3078.396238 # Average occupied blocks per requestor
161system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy
162system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy
163system.cpu.dcache.ReadReq_hits::cpu.data 94570005 # number of ReadReq hits
164system.cpu.dcache.ReadReq_hits::total 94570005 # number of ReadReq hits
165system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
166system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
167system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
168system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
169system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
170system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
171system.cpu.dcache.demand_hits::cpu.data 176619810 # number of demand (read+write) hits
172system.cpu.dcache.demand_hits::total 176619810 # number of demand (read+write) hits
173system.cpu.dcache.overall_hits::cpu.data 176619810 # number of overall hits
174system.cpu.dcache.overall_hits::total 176619810 # number of overall hits
175system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses
176system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses
177system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
178system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
179system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses
180system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
181system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
182system.cpu.dcache.overall_misses::total 4478 # number of overall misses
183system.cpu.dcache.ReadReq_miss_latency::cpu.data 79898000 # number of ReadReq miss cycles
184system.cpu.dcache.ReadReq_miss_latency::total 79898000 # number of ReadReq miss cycles
185system.cpu.dcache.WriteReq_miss_latency::cpu.data 160160000 # number of WriteReq miss cycles
186system.cpu.dcache.WriteReq_miss_latency::total 160160000 # number of WriteReq miss cycles
187system.cpu.dcache.demand_miss_latency::cpu.data 240058000 # number of demand (read+write) miss cycles
188system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles
189system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles
190system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles
191system.cpu.dcache.ReadReq_accesses::cpu.data 94571611 # number of ReadReq accesses(hits+misses)
192system.cpu.dcache.ReadReq_accesses::total 94571611 # number of ReadReq accesses(hits+misses)
193system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
194system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
195system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
196system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
197system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
198system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
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200system.cpu.dcache.demand_accesses::total 176624288 # number of demand (read+write) accesses
201system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses
202system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses
203system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
204system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
205system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
206system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
207system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency
208system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency
209system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency
210system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency
211system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
212system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
213system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
214system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
215system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
216system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 215system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
216system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
217system.cpu.dcache.fast_writes 0 # number of fast writes performed
218system.cpu.dcache.cache_copies 0 # number of cache copies performed
219system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
220system.cpu.dcache.writebacks::total 998 # number of writebacks
221system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses
222system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses
223system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
224system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
225system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses
226system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses
227system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
228system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
229system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles
230system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles
231system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles
232system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles
233system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles
234system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles
235system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles
236system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles
237system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses
238system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
239system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
240system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
241system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
242system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
243system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
244system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
245system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
246system.cpu.l2cache.replacements 48 # number of replacements
247system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use
248system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks.
249system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
250system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks.
251system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
252system.cpu.l2cache.occ_blocks::writebacks 341.613272 # Average occupied blocks per requestor
253system.cpu.l2cache.occ_blocks::cpu.inst 2402.300580 # Average occupied blocks per requestor
254system.cpu.l2cache.occ_blocks::cpu.data 731.759070 # Average occupied blocks per requestor
255system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
256system.cpu.l2cache.occ_percent::cpu.inst 0.073312 # Average percentage of cache occupancy
257system.cpu.l2cache.occ_percent::cpu.data 0.022332 # Average percentage of cache occupancy
258system.cpu.l2cache.occ_percent::total 0.106069 # Average percentage of cache occupancy
259system.cpu.l2cache.ReadReq_hits::cpu.inst 12993 # number of ReadReq hits
260system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
261system.cpu.l2cache.ReadReq_hits::total 13232 # number of ReadReq hits
262system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
263system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
264system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
265system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
266system.cpu.l2cache.demand_hits::cpu.inst 12993 # number of demand (read+write) hits
267system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
268system.cpu.l2cache.demand_hits::total 13248 # number of demand (read+write) hits
269system.cpu.l2cache.overall_hits::cpu.inst 12993 # number of overall hits
270system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
271system.cpu.l2cache.overall_hits::total 13248 # number of overall hits
272system.cpu.l2cache.ReadReq_misses::cpu.inst 2610 # number of ReadReq misses
273system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses
274system.cpu.l2cache.ReadReq_misses::total 3977 # number of ReadReq misses
275system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
276system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
277system.cpu.l2cache.demand_misses::cpu.inst 2610 # number of demand (read+write) misses
278system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses
279system.cpu.l2cache.demand_misses::total 6833 # number of demand (read+write) misses
280system.cpu.l2cache.overall_misses::cpu.inst 2610 # number of overall misses
281system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
282system.cpu.l2cache.overall_misses::total 6833 # number of overall misses
283system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135720000 # number of ReadReq miss cycles
284system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles
285system.cpu.l2cache.ReadReq_miss_latency::total 206804000 # number of ReadReq miss cycles
286system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles
287system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles
288system.cpu.l2cache.demand_miss_latency::cpu.inst 135720000 # number of demand (read+write) miss cycles
289system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles
290system.cpu.l2cache.demand_miss_latency::total 355316000 # number of demand (read+write) miss cycles
291system.cpu.l2cache.overall_miss_latency::cpu.inst 135720000 # number of overall miss cycles
292system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles
293system.cpu.l2cache.overall_miss_latency::total 355316000 # number of overall miss cycles
294system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
295system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
296system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
297system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses)
298system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses)
299system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
300system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
301system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
302system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
303system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
304system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
305system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
306system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
307system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167276 # miss rate for ReadReq accesses
308system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses
309system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
310system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167276 # miss rate for demand accesses
311system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses
312system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167276 # miss rate for overall accesses
313system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
314system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
315system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
316system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
317system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
318system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
319system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
320system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
321system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
322system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
323system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
324system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
| 217system.cpu.dcache.fast_writes 0 # number of fast writes performed
218system.cpu.dcache.cache_copies 0 # number of cache copies performed
219system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
220system.cpu.dcache.writebacks::total 998 # number of writebacks
221system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses
222system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses
223system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
224system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
225system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses
226system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses
227system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
228system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
229system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles
230system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles
231system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles
232system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles
233system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles
234system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles
235system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles
236system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles
237system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses
238system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
239system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
240system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
241system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
242system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
243system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
244system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
245system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
246system.cpu.l2cache.replacements 48 # number of replacements
247system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use
248system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks.
249system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
250system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks.
251system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
252system.cpu.l2cache.occ_blocks::writebacks 341.613272 # Average occupied blocks per requestor
253system.cpu.l2cache.occ_blocks::cpu.inst 2402.300580 # Average occupied blocks per requestor
254system.cpu.l2cache.occ_blocks::cpu.data 731.759070 # Average occupied blocks per requestor
255system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
256system.cpu.l2cache.occ_percent::cpu.inst 0.073312 # Average percentage of cache occupancy
257system.cpu.l2cache.occ_percent::cpu.data 0.022332 # Average percentage of cache occupancy
258system.cpu.l2cache.occ_percent::total 0.106069 # Average percentage of cache occupancy
259system.cpu.l2cache.ReadReq_hits::cpu.inst 12993 # number of ReadReq hits
260system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
261system.cpu.l2cache.ReadReq_hits::total 13232 # number of ReadReq hits
262system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
263system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
264system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
265system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
266system.cpu.l2cache.demand_hits::cpu.inst 12993 # number of demand (read+write) hits
267system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
268system.cpu.l2cache.demand_hits::total 13248 # number of demand (read+write) hits
269system.cpu.l2cache.overall_hits::cpu.inst 12993 # number of overall hits
270system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
271system.cpu.l2cache.overall_hits::total 13248 # number of overall hits
272system.cpu.l2cache.ReadReq_misses::cpu.inst 2610 # number of ReadReq misses
273system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses
274system.cpu.l2cache.ReadReq_misses::total 3977 # number of ReadReq misses
275system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
276system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
277system.cpu.l2cache.demand_misses::cpu.inst 2610 # number of demand (read+write) misses
278system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses
279system.cpu.l2cache.demand_misses::total 6833 # number of demand (read+write) misses
280system.cpu.l2cache.overall_misses::cpu.inst 2610 # number of overall misses
281system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
282system.cpu.l2cache.overall_misses::total 6833 # number of overall misses
283system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135720000 # number of ReadReq miss cycles
284system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles
285system.cpu.l2cache.ReadReq_miss_latency::total 206804000 # number of ReadReq miss cycles
286system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles
287system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles
288system.cpu.l2cache.demand_miss_latency::cpu.inst 135720000 # number of demand (read+write) miss cycles
289system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles
290system.cpu.l2cache.demand_miss_latency::total 355316000 # number of demand (read+write) miss cycles
291system.cpu.l2cache.overall_miss_latency::cpu.inst 135720000 # number of overall miss cycles
292system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles
293system.cpu.l2cache.overall_miss_latency::total 355316000 # number of overall miss cycles
294system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
295system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
296system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
297system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses)
298system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses)
299system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
300system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
301system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
302system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
303system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
304system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
305system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
306system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
307system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167276 # miss rate for ReadReq accesses
308system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses
309system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
310system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167276 # miss rate for demand accesses
311system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses
312system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167276 # miss rate for overall accesses
313system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
314system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
315system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
316system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
317system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
318system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
319system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
320system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
321system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
322system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
323system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
324system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
325system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
326system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 325system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
326system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
327system.cpu.l2cache.fast_writes 0 # number of fast writes performed
328system.cpu.l2cache.cache_copies 0 # number of cache copies performed
329system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses
330system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses
331system.cpu.l2cache.ReadReq_mshr_misses::total 3977 # number of ReadReq MSHR misses
332system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
333system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
334system.cpu.l2cache.demand_mshr_misses::cpu.inst 2610 # number of demand (read+write) MSHR misses
335system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses
336system.cpu.l2cache.demand_mshr_misses::total 6833 # number of demand (read+write) MSHR misses
337system.cpu.l2cache.overall_mshr_misses::cpu.inst 2610 # number of overall MSHR misses
338system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
339system.cpu.l2cache.overall_mshr_misses::total 6833 # number of overall MSHR misses
340system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104400000 # number of ReadReq MSHR miss cycles
341system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
342system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159080000 # number of ReadReq MSHR miss cycles
343system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles
344system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles
345system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104400000 # number of demand (read+write) MSHR miss cycles
346system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles
347system.cpu.l2cache.demand_mshr_miss_latency::total 273320000 # number of demand (read+write) MSHR miss cycles
348system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104400000 # number of overall MSHR miss cycles
349system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles
350system.cpu.l2cache.overall_mshr_miss_latency::total 273320000 # number of overall MSHR miss cycles
351system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for ReadReq accesses
352system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
353system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
354system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for demand accesses
355system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses
356system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for overall accesses
357system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
358system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
359system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
360system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
361system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
362system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
363system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
364system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
365system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
366
367---------- End Simulation Statistics ----------
| 327system.cpu.l2cache.fast_writes 0 # number of fast writes performed
328system.cpu.l2cache.cache_copies 0 # number of cache copies performed
329system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses
330system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses
331system.cpu.l2cache.ReadReq_mshr_misses::total 3977 # number of ReadReq MSHR misses
332system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
333system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
334system.cpu.l2cache.demand_mshr_misses::cpu.inst 2610 # number of demand (read+write) MSHR misses
335system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses
336system.cpu.l2cache.demand_mshr_misses::total 6833 # number of demand (read+write) MSHR misses
337system.cpu.l2cache.overall_mshr_misses::cpu.inst 2610 # number of overall MSHR misses
338system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
339system.cpu.l2cache.overall_mshr_misses::total 6833 # number of overall MSHR misses
340system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104400000 # number of ReadReq MSHR miss cycles
341system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
342system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159080000 # number of ReadReq MSHR miss cycles
343system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles
344system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles
345system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104400000 # number of demand (read+write) MSHR miss cycles
346system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles
347system.cpu.l2cache.demand_mshr_miss_latency::total 273320000 # number of demand (read+write) MSHR miss cycles
348system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104400000 # number of overall MSHR miss cycles
349system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles
350system.cpu.l2cache.overall_mshr_miss_latency::total 273320000 # number of overall MSHR miss cycles
351system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for ReadReq accesses
352system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
353system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
354system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for demand accesses
355system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses
356system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for overall accesses
357system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
358system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
359system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
360system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
361system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
362system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
363system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
364system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
365system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
366
367---------- End Simulation Statistics ----------
|