Cross Reference: /gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt

stats.txt (11515:c48c7cc5a522)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517291 # Number of seconds simulated 4sim_ticks 517291025500 # Number of ticks simulated 5final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517291 # Number of seconds simulated 4sim_ticks 517291025500 # Number of ticks simulated 5final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 977708 # Simulator instruction rate (inst/s) 8host_op_rate 1173775 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1854370201 # Simulator tick rate (ticks/s) 10host_mem_usage 319164 # Number of bytes of host memory used 11host_seconds 278.96 # Real time elapsed on the host	7host_inst_rate 968617 # Simulator instruction rate (inst/s) 8host_op_rate 1162861 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1837127354 # Simulator tick rate (ticks/s) 10host_mem_usage 320856 # Number of bytes of host memory used 11host_seconds 281.58 # Real time elapsed on the host
12sim_insts 272739286 # Number of instructions simulated 13sim_ops 327433744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 272739286 # Number of instructions simulated 13sim_ops 327433744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)	17system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory 19system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
	33system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
32system.cpu_clk_domain.clock 500 # Clock period in ticks	34system.cpu_clk_domain.clock 500 # Clock period in ticks
	35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 45system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 46system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 47system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 54system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 55system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 56system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses 72system.cpu.dtb.read_hits 0 # DTB read hits 73system.cpu.dtb.read_misses 0 # DTB read misses 74system.cpu.dtb.write_hits 0 # DTB write hits 75system.cpu.dtb.write_misses 0 # DTB write misses 76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses	66system.cpu.dtb.walker.walks 0 # Table walker walks requested 67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.inst_hits 0 # ITB inst hits 75system.cpu.dtb.inst_misses 0 # ITB inst misses 76system.cpu.dtb.read_hits 0 # DTB read hits 77system.cpu.dtb.read_misses 0 # DTB read misses 78system.cpu.dtb.write_hits 0 # DTB write hits 79system.cpu.dtb.write_misses 0 # DTB write misses 80system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 81system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 82system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 83system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 84system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 85system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 86system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.dtb.read_accesses 0 # DTB read accesses 90system.cpu.dtb.write_accesses 0 # DTB write accesses 91system.cpu.dtb.inst_accesses 0 # ITB inst accesses 92system.cpu.dtb.hits 0 # DTB hits 93system.cpu.dtb.misses 0 # DTB misses 94system.cpu.dtb.accesses 0 # DTB accesses
	95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 109system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 110system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 111system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 105system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 106system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 107system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 108system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 109system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 110system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 111system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 114system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 115system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 116system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.inst_hits 0 # ITB inst hits 129system.cpu.itb.inst_misses 0 # ITB inst misses 130system.cpu.itb.read_hits 0 # DTB read hits 131system.cpu.itb.read_misses 0 # DTB read misses 132system.cpu.itb.write_hits 0 # DTB write hits 133system.cpu.itb.write_misses 0 # DTB write misses 134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 136system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 137system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 139system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 140system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 141system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 191 # Number of system calls	126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.inst_hits 0 # ITB inst hits 135system.cpu.itb.inst_misses 0 # ITB inst misses 136system.cpu.itb.read_hits 0 # DTB read hits 137system.cpu.itb.read_misses 0 # DTB read misses 138system.cpu.itb.write_hits 0 # DTB write hits 139system.cpu.itb.write_misses 0 # DTB write misses 140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 143system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 145system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 146system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 191 # Number of system calls
	156system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states
150system.cpu.numCycles 1034582051 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 272739286 # Number of instructions committed 154system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 157system.cpu.num_func_calls 12448615 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls 159system.cpu.num_int_insts 258331537 # number of integer instructions 160system.cpu.num_fp_insts 114216705 # number of float instructions 161system.cpu.num_int_register_reads 979511506 # number of times the integer registers were read 162system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written 163system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written 167system.cpu.num_mem_refs 168107847 # number of memory refs 168system.cpu.num_load_insts 85732248 # Number of load instructions 169system.cpu.num_store_insts 82375599 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 171system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 30563503 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction 177system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction 180system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction 181system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction 182system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction 183system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction 184system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction 185system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction 186system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction 187system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction 188system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction 189system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction 190system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction 191system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction 192system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction 193system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction 194system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction 195system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction 196system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction 197system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction 198system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction 199system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction 200system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction 201system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction 202system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 205system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 206system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 327812214 # Class of executed instruction	157system.cpu.numCycles 1034582051 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 272739286 # Number of instructions committed 161system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 164system.cpu.num_func_calls 12448615 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls 166system.cpu.num_int_insts 258331537 # number of integer instructions 167system.cpu.num_fp_insts 114216705 # number of float instructions 168system.cpu.num_int_register_reads 979511506 # number of times the integer registers were read 169system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written 170system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written 174system.cpu.num_mem_refs 168107847 # number of memory refs 175system.cpu.num_load_insts 85732248 # Number of load instructions 176system.cpu.num_store_insts 82375599 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 178system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 30563503 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction 184system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction 192system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction 193system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction 194system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction 195system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction 196system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction 197system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction 198system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction 199system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction 200system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction 201system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction 202system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction 203system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction 204system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction 205system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction 206system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction 207system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction 208system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 212system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 213system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 327812214 # Class of executed instruction
	217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
210system.cpu.dcache.tags.replacements 1332 # number of replacements 211system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 222system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 223system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 224system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 225system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 226system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses 227system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses	218system.cpu.dcache.tags.replacements 1332 # number of replacements 219system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use 220system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 221system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 222system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 224system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor 225system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy 227system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 232system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 233system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 234system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses 235system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
	236system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
228system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits 229system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits 230system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 231system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 232system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits 233system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits 234system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 235system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 236system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 237system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 238system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits 239system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits 240system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits 241system.cpu.dcache.overall_hits::total 168337827 # number of overall hits 242system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses 243system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses 244system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 245system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 246system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 247system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 248system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses 249system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses 250system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses 251system.cpu.dcache.overall_misses::total 4479 # number of overall misses 252system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles 253system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles 254system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles 255system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles 256system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles 257system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles 258system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles 259system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles 260system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) 261system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) 262system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 263system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 264system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) 265system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) 266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 267system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 268system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 269system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 270system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses 271system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses 272system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses 273system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses 274system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses 275system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses 276system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 277system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 278system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses 279system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses 280system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses 281system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 282system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses 283system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 284system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency 285system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency 286system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency 287system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency 288system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency 289system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency 290system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency 291system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency 292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 298system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 299system.cpu.dcache.writebacks::total 998 # number of writebacks 300system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 301system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 302system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 303system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 304system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 305system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 306system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses 307system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses 308system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 309system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 310system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 311system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 312system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses 313system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses 314system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 315system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 316system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles 317system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles 318system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles 319system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles 320system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles 321system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles 322system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles 323system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles 324system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles 325system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles 326system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 327system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 328system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 329system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 330system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses 331system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses 332system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 333system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 334system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 335system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 336system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency 337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency 338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency 339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency 340system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 342system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency 343system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency 344system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency 345system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency	237system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits 238system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits 239system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 240system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 241system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits 242system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits 243system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 244system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 245system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 246system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 247system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits 248system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits 249system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits 250system.cpu.dcache.overall_hits::total 168337827 # number of overall hits 251system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses 252system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses 253system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 254system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 255system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 256system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 257system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses 258system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses 259system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses 260system.cpu.dcache.overall_misses::total 4479 # number of overall misses 261system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles 262system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles 263system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles 264system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles 265system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles 266system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles 267system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles 268system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles 269system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) 270system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) 271system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 272system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 273system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) 274system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) 275system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 276system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 277system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 278system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 279system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses 280system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses 281system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses 282system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses 283system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses 284system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses 285system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 286system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 287system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses 288system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses 289system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses 290system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 291system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses 292system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 293system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency 294system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency 295system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency 296system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency 297system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency 298system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency 299system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency 300system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency 301system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 304system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 305system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 306system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 307system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 308system.cpu.dcache.writebacks::total 998 # number of writebacks 309system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 310system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 311system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 312system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 313system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 314system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 315system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses 316system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses 317system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 318system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 319system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 320system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 321system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses 322system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses 323system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 324system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 325system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles 326system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles 327system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles 328system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles 329system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles 330system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles 331system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles 332system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles 333system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles 334system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles 335system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 336system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 337system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 338system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 339system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses 340system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses 341system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 342system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 343system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 344system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency 346system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency 347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency 348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency 349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 350system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 351system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency 352system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency 353system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency 354system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
	355system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
346system.cpu.icache.tags.replacements 13796 # number of replacements 347system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use 348system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. 349system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 350system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. 351system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 352system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor 353system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy 354system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy 355system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 356system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id 361system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id 362system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses 363system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses	356system.cpu.icache.tags.replacements 13796 # number of replacements 357system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use 358system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. 359system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 360system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. 361system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 362system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor 363system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy 364system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy 365system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 368system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 369system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 370system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id 371system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id 372system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses 373system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
	374system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
364system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits 365system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits 366system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits 367system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits 368system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits 369system.cpu.icache.overall_hits::total 348644750 # number of overall hits 370system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 371system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 372system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 373system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 374system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 375system.cpu.icache.overall_misses::total 15603 # number of overall misses 376system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles 377system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles 378system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles 379system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles 380system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles 381system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles 382system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) 383system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) 384system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses 385system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses 386system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses 387system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses 388system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 389system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 390system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 391system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 392system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 393system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 394system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency 395system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency 396system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency 397system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency 398system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency 399system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency 400system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 401system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 402system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 404system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 405system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 406system.cpu.icache.writebacks::writebacks 13796 # number of writebacks 407system.cpu.icache.writebacks::total 13796 # number of writebacks 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses 414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles 420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 423system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency	375system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits 376system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits 377system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits 378system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits 379system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits 380system.cpu.icache.overall_hits::total 348644750 # number of overall hits 381system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 382system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 383system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 384system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 385system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 386system.cpu.icache.overall_misses::total 15603 # number of overall misses 387system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles 388system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles 389system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles 390system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles 391system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles 392system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles 393system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) 394system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) 395system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses 396system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses 397system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses 398system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses 399system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 400system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 401system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 402system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 403system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 404system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 405system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency 406system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency 407system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency 408system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency 409system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency 410system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency 411system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 412system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 413system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 414system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 415system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 416system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 417system.cpu.icache.writebacks::writebacks 13796 # number of writebacks 418system.cpu.icache.writebacks::total 13796 # number of writebacks 419system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 420system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 421system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 422system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 423system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 424system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses 425system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles 426system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles 427system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles 428system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles 429system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles 430system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles 431system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 432system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 433system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 434system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 435system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 436system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 437system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency 438system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency 439system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 440system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency 441system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 442system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
	443system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
432system.cpu.l2cache.tags.replacements 0 # number of replacements 433system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use 434system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. 435system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 436system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. 437system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 438system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor 439system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor 440system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor 441system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy 442system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy 443system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy 444system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy 445system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id 446system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 447system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 448system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 449system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id 450system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id 451system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id 452system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses 453system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses	444system.cpu.l2cache.tags.replacements 0 # number of replacements 445system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use 446system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. 447system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 448system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. 449system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 450system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor 451system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor 452system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor 453system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy 454system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy 455system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy 456system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy 457system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id 458system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 459system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 460system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 461system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id 462system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id 463system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id 464system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses 465system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
	466system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
454system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits 455system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits 456system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits 457system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits 458system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 459system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 460system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits 461system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits 462system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits 463system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits 464system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits 465system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits 466system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits 467system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits 468system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits 469system.cpu.l2cache.overall_hits::total 13249 # number of overall hits 470system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 471system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 472system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses 473system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses 474system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses 475system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses 476system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses 477system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses 478system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 479system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses 480system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses 481system.cpu.l2cache.overall_misses::total 6832 # number of overall misses 482system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles 483system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles 484system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles 485system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles 486system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles 487system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles 488system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles 489system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles 490system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles 491system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles 492system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles 493system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles 494system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) 495system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) 496system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) 497system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses) 498system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 499system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 500system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) 501system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses) 502system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses) 503system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses) 504system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses 505system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses 506system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses 507system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses 508system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses 509system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses 510system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 511system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 512system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses 513system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses 514system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses 515system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses 516system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses 517system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses 518system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 519system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses 520system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses 521system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses 522system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency 523system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency 524system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency 525system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency 526system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency 527system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency 528system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency 529system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency 530system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency 531system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency 532system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency 534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 540system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 541system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 542system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses 543system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses 544system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses 545system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses 546system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses 547system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses 548system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 549system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses 550system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses 551system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses 552system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles 553system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles 554system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles 555system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles 556system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles 557system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles 558system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles 559system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles 560system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles 561system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles 562system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles 563system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles 564system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 565system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 566system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses 567system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses 568system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses 569system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses 570system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses 571system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses 572system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 573system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses 574system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses 575system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses 576system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency 577system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency 578system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency 579system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency 580system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency 581system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency 582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency 583system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 584system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency 586system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 587system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency 588system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. 589system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 590system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 591system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 592system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 593system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	467system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits 468system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits 469system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits 470system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits 471system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 472system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 473system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits 474system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits 475system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits 476system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits 477system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits 478system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits 479system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits 480system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits 481system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits 482system.cpu.l2cache.overall_hits::total 13249 # number of overall hits 483system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 484system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 485system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses 486system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses 487system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses 488system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses 489system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses 490system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses 491system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 492system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses 493system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses 494system.cpu.l2cache.overall_misses::total 6832 # number of overall misses 495system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles 496system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles 497system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles 498system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles 499system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles 500system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles 501system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles 502system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles 503system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles 504system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles 505system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles 506system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles 507system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) 508system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) 509system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) 510system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses) 511system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 512system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 513system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) 514system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses) 515system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses) 516system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses) 517system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses 518system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses 519system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses 520system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses 521system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses 522system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses 523system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 524system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 525system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses 526system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses 527system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses 528system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses 529system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses 530system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses 531system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 532system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses 533system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses 534system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses 535system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency 536system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency 537system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency 538system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency 539system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency 540system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency 541system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency 542system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency 543system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency 544system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency 545system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency 546system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency 547system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 554system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 555system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses 556system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses 557system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses 558system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses 559system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses 560system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses 561system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 562system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses 563system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses 564system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses 565system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles 566system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles 567system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles 568system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles 569system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles 570system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles 571system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles 572system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles 573system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles 574system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles 575system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles 576system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles 577system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 578system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 579system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses 580system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses 581system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses 582system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses 583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses 584system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses 585system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 586system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses 587system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses 588system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses 589system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency 590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency 591system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency 592system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency 593system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency 594system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency 595system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency 596system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 597system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency 598system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency 599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 600system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency 601system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. 602system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 603system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 604system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 605system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 606system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	607system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
594system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 595system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution 596system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution 597system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution 598system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 599system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 600system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution 602system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes) 603system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes) 604system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes) 605system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes) 606system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) 607system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes) 608system.cpu.toL2Bus.snoops 0 # Total snoops (count) 609system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram 610system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram 611system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram 612system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 613system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram 614system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram 615system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 616system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 617system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 618system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 619system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram 620system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks) 621system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 622system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 623system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 624system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 625system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)	608system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 613system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 614system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution 615system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution 616system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes) 617system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes) 618system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes) 619system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes) 620system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) 621system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes) 622system.cpu.toL2Bus.snoops 0 # Total snoops (count) 623system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram 624system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 627system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram 628system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram 629system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 630system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 631system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 632system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 633system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram 634system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks) 635system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 636system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 637system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 638system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 639system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
	640system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
626system.membus.trans_dist::ReadResp 3976 # Transaction distribution 627system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 628system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 629system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution 630system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 631system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) 632system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 633system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) 634system.membus.snoops 0 # Total snoops (count) 635system.membus.snoop_fanout::samples 6833 # Request fanout histogram 636system.membus.snoop_fanout::mean 0 # Request fanout histogram 637system.membus.snoop_fanout::stdev 0 # Request fanout histogram 638system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 639system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram 640system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 641system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 642system.membus.snoop_fanout::min_value 0 # Request fanout histogram 643system.membus.snoop_fanout::max_value 0 # Request fanout histogram 644system.membus.snoop_fanout::total 6833 # Request fanout histogram 645system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks) 646system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 647system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks) 648system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 649 650---------- End Simulation Statistics ----------	641system.membus.trans_dist::ReadResp 3976 # Transaction distribution 642system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 643system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 644system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution 645system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 646system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) 647system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 648system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) 649system.membus.snoops 0 # Total snoops (count) 650system.membus.snoop_fanout::samples 6833 # Request fanout histogram 651system.membus.snoop_fanout::mean 0 # Request fanout histogram 652system.membus.snoop_fanout::stdev 0 # Request fanout histogram 653system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 654system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram 655system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 656system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 657system.membus.snoop_fanout::min_value 0 # Request fanout histogram 658system.membus.snoop_fanout::max_value 0 # Request fanout histogram 659system.membus.snoop_fanout::total 6833 # Request fanout histogram 660system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks) 661system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 662system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks) 663system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 664 665---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.517291 # Number of seconds simulated
4sim_ticks 517291025500 # Number of ticks simulated
5final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 977708 # Simulator instruction rate (inst/s)
8host_op_rate 1173775 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1854370201 # Simulator tick rate (ticks/s)
10host_mem_usage 319164 # Number of bytes of host memory used
11host_seconds 278.96 # Real time elapsed on the host

7host_inst_rate 968617 # Simulator instruction rate (inst/s)
8host_op_rate 1162861 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1837127354 # Simulator tick rate (ticks/s)
10host_mem_usage 320856 # Number of bytes of host memory used
11host_seconds 281.58 # Real time elapsed on the host

12sim_insts 272739286 # Number of instructions simulated
13sim_ops 327433744 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)

17system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
19system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)

33system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

32system.cpu_clk_domain.clock 500 # Clock period in ticks

34system.cpu_clk_domain.clock 500 # Clock period in ticks

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
51system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
52system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
53system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
45system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
46system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
47system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
48system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
49system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
52system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
54system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
55system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
56system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

62system.cpu.dtb.walker.walks 0 # Table walker walks requested
63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.inst_hits 0 # ITB inst hits
71system.cpu.dtb.inst_misses 0 # ITB inst misses
72system.cpu.dtb.read_hits 0 # DTB read hits
73system.cpu.dtb.read_misses 0 # DTB read misses
74system.cpu.dtb.write_hits 0 # DTB write hits
75system.cpu.dtb.write_misses 0 # DTB write misses
76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
85system.cpu.dtb.read_accesses 0 # DTB read accesses
86system.cpu.dtb.write_accesses 0 # DTB write accesses
87system.cpu.dtb.inst_accesses 0 # ITB inst accesses
88system.cpu.dtb.hits 0 # DTB hits
89system.cpu.dtb.misses 0 # DTB misses
90system.cpu.dtb.accesses 0 # DTB accesses

66system.cpu.dtb.walker.walks 0 # Table walker walks requested
67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
74system.cpu.dtb.inst_hits 0 # ITB inst hits
75system.cpu.dtb.inst_misses 0 # ITB inst misses
76system.cpu.dtb.read_hits 0 # DTB read hits
77system.cpu.dtb.read_misses 0 # DTB read misses
78system.cpu.dtb.write_hits 0 # DTB write hits
79system.cpu.dtb.write_misses 0 # DTB write misses
80system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
81system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
82system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
83system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
84system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
85system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
86system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
89system.cpu.dtb.read_accesses 0 # DTB read accesses
90system.cpu.dtb.write_accesses 0 # DTB write accesses
91system.cpu.dtb.inst_accesses 0 # ITB inst accesses
92system.cpu.dtb.hits 0 # DTB hits
93system.cpu.dtb.misses 0 # DTB misses
94system.cpu.dtb.accesses 0 # DTB accesses

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
108system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
109system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
110system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
111system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
104system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
105system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
106system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
107system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
108system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
109system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
110system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
111system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
114system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
115system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
116system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

120system.cpu.itb.walker.walks 0 # Table walker walks requested
121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.inst_hits 0 # ITB inst hits
129system.cpu.itb.inst_misses 0 # ITB inst misses
130system.cpu.itb.read_hits 0 # DTB read hits
131system.cpu.itb.read_misses 0 # DTB read misses
132system.cpu.itb.write_hits 0 # DTB write hits
133system.cpu.itb.write_misses 0 # DTB write misses
134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
136system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
137system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
138system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
139system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
140system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
141system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
143system.cpu.itb.read_accesses 0 # DTB read accesses
144system.cpu.itb.write_accesses 0 # DTB write accesses
145system.cpu.itb.inst_accesses 0 # ITB inst accesses
146system.cpu.itb.hits 0 # DTB hits
147system.cpu.itb.misses 0 # DTB misses
148system.cpu.itb.accesses 0 # DTB accesses
149system.cpu.workload.num_syscalls 191 # Number of system calls

126system.cpu.itb.walker.walks 0 # Table walker walks requested
127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
134system.cpu.itb.inst_hits 0 # ITB inst hits
135system.cpu.itb.inst_misses 0 # ITB inst misses
136system.cpu.itb.read_hits 0 # DTB read hits
137system.cpu.itb.read_misses 0 # DTB read misses
138system.cpu.itb.write_hits 0 # DTB write hits
139system.cpu.itb.write_misses 0 # DTB write misses
140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
142system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
143system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
144system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
145system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
146system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149system.cpu.itb.read_accesses 0 # DTB read accesses
150system.cpu.itb.write_accesses 0 # DTB write accesses
151system.cpu.itb.inst_accesses 0 # ITB inst accesses
152system.cpu.itb.hits 0 # DTB hits
153system.cpu.itb.misses 0 # DTB misses
154system.cpu.itb.accesses 0 # DTB accesses
155system.cpu.workload.num_syscalls 191 # Number of system calls

156system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states

150system.cpu.numCycles 1034582051 # number of cpu cycles simulated
151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
153system.cpu.committedInsts 272739286 # Number of instructions committed
154system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
155system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
156system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
157system.cpu.num_func_calls 12448615 # number of times a function call or return occured
158system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
159system.cpu.num_int_insts 258331537 # number of integer instructions
160system.cpu.num_fp_insts 114216705 # number of float instructions
161system.cpu.num_int_register_reads 979511506 # number of times the integer registers were read
162system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
163system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
164system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
165system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
166system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
167system.cpu.num_mem_refs 168107847 # number of memory refs
168system.cpu.num_load_insts 85732248 # Number of load instructions
169system.cpu.num_store_insts 82375599 # Number of store instructions
170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
171system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
174system.cpu.Branches 30563503 # Number of branches fetched
175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
176system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
177system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
178system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
179system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
180system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
181system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
182system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
183system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
184system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
185system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
186system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
187system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
188system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
189system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
190system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
191system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
192system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
193system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
194system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
195system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
196system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
197system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
198system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
199system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
200system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
201system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
202system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
203system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
204system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
205system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
206system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
209system.cpu.op_class::total 327812214 # Class of executed instruction

157system.cpu.numCycles 1034582051 # number of cpu cycles simulated
158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 272739286 # Number of instructions committed
161system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
164system.cpu.num_func_calls 12448615 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
166system.cpu.num_int_insts 258331537 # number of integer instructions
167system.cpu.num_fp_insts 114216705 # number of float instructions
168system.cpu.num_int_register_reads 979511506 # number of times the integer registers were read
169system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
170system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
174system.cpu.num_mem_refs 168107847 # number of memory refs
175system.cpu.num_load_insts 85732248 # Number of load instructions
176system.cpu.num_store_insts 82375599 # Number of store instructions
177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
178system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 30563503 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
184system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
187system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
188system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
189system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
190system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
191system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
192system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
193system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
194system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
195system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
196system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
197system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
198system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
199system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
200system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
201system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
202system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
203system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
204system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
205system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
206system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
207system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
208system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
209system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
212system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
213system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 327812214 # Class of executed instruction

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

210system.cpu.dcache.tags.replacements 1332 # number of replacements
211system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
212system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
213system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
214system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
216system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
217system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
218system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
219system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
220system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
221system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
222system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
223system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
224system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
225system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
226system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
227system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses

218system.cpu.dcache.tags.replacements 1332 # number of replacements
219system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
220system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
221system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
222system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
224system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
227system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
232system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
233system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
234system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
235system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses

236system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

228system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
229system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
230system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
231system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
232system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
233system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
234system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
235system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
236system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
237system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
238system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
239system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
240system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
241system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
242system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
243system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
244system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
245system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
246system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
247system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
248system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
249system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
250system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
251system.cpu.dcache.overall_misses::total 4479 # number of overall misses
252system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
253system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
254system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
255system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
256system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
257system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
258system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
259system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
260system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
261system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
262system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
263system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
264system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
265system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
267system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
268system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
269system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
270system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
271system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
272system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
273system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
274system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
275system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
276system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
277system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
278system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
279system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
280system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
281system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
282system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
283system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
284system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
285system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
286system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
287system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
288system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
289system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
290system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
291system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
298system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
299system.cpu.dcache.writebacks::total 998 # number of writebacks
300system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
301system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
302system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
303system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
304system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
305system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
306system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
307system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
308system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
309system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
310system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
311system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
312system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
313system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
314system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
315system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
316system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
317system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
318system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
319system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
320system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
321system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
322system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
323system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
324system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
325system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
326system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
327system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
328system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
329system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
330system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
331system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
332system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
333system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
334system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
335system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
336system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
340system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
342system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
343system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
344system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
345system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency

237system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
238system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
239system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
240system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
241system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
242system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
243system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
244system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
245system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
246system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
247system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
248system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
249system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
250system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
251system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
252system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
253system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
254system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
255system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
256system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
257system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
258system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
259system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
260system.cpu.dcache.overall_misses::total 4479 # number of overall misses
261system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
262system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
263system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
264system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
265system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
266system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
267system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
268system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
269system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
270system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
271system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
272system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
273system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
274system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
275system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
276system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
277system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
278system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
279system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
280system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
281system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
282system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
283system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
284system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
285system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
286system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
287system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
288system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
289system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
290system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
291system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
292system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
293system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
294system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
295system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
296system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
297system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
298system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
299system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
300system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
301system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
302system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
303system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
304system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
305system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
306system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
307system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
308system.cpu.dcache.writebacks::total 998 # number of writebacks
309system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
310system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
311system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
312system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
313system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
314system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
315system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
316system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
317system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
318system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
319system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
320system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
321system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
322system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
323system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
324system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
325system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
326system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
327system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
328system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
329system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
330system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
331system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
332system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
333system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
334system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
335system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
336system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
337system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
338system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
339system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
340system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
341system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
342system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
343system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
344system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
346system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
350system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
351system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
352system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
353system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
354system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency

355system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

346system.cpu.icache.tags.replacements 13796 # number of replacements
347system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
348system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
349system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
350system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
351system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
352system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
353system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
354system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
355system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
356system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
357system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
358system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
359system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
361system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
362system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
363system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses

356system.cpu.icache.tags.replacements 13796 # number of replacements
357system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
358system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
359system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
360system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
361system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
362system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
363system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
364system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
365system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
366system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
367system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
368system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
369system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
370system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
371system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
372system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
373system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses

374system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

364system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
365system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
366system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
367system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
368system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
369system.cpu.icache.overall_hits::total 348644750 # number of overall hits
370system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
371system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
372system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
373system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
374system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
375system.cpu.icache.overall_misses::total 15603 # number of overall misses
376system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
377system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
378system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
379system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
380system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
381system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
382system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
383system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
384system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
385system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses
386system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses
387system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses
388system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
389system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
390system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
391system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
392system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
393system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
394system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
395system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
396system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
397system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
398system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
399system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
400system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
401system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
402system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
403system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
404system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
405system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
406system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
407system.cpu.icache.writebacks::total 13796 # number of writebacks
408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
409system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
410system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
411system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
412system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
413system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
415system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
417system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
419system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
423system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
425system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
429system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
431system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency

375system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
376system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
377system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
378system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
379system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
380system.cpu.icache.overall_hits::total 348644750 # number of overall hits
381system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
382system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
383system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
384system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
385system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
386system.cpu.icache.overall_misses::total 15603 # number of overall misses
387system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
388system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
389system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
390system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
391system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
392system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
393system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
394system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
395system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
396system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses
397system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses
398system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses
399system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
400system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
401system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
402system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
403system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
404system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
405system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
406system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
407system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
408system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
409system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
410system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
411system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
412system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
413system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
414system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
415system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
416system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
417system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
418system.cpu.icache.writebacks::total 13796 # number of writebacks
419system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
420system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
421system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
422system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
423system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
424system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
425system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
426system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
427system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
428system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
429system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
430system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
431system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
432system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
433system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
434system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
435system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
436system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
437system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
438system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
439system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
440system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
441system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
442system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency

443system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

432system.cpu.l2cache.tags.replacements 0 # number of replacements
433system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
434system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
435system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
436system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
437system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
438system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
439system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
440system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor
441system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
442system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
443system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
444system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy
445system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
446system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
447system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
448system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
449system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
450system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
451system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
452system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
453system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses

444system.cpu.l2cache.tags.replacements 0 # number of replacements
445system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
446system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
447system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
448system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
449system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
450system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
451system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
452system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor
453system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
454system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
455system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
456system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy
457system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
458system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
459system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
460system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
461system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
462system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
463system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
464system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
465system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses

466system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

454system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
455system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
456system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
457system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
458system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
459system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
460system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
461system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits
462system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits
463system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits
464system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits
465system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits
466system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
467system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits
468system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits
469system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
470system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
471system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
472system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses
473system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses
474system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses
475system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses
476system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses
477system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses
478system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
479system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses
480system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses
481system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
482system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles
483system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles
484system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles
485system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles
486system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
487system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles
488system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles
489system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles
490system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles
491system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles
492system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles
493system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles
494system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses)
495system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses)
496system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses)
497system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses)
498system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
499system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
500system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses)
501system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses)
502system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses)
503system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses)
504system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
505system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
506system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
507system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
508system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
509system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
510system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
511system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
512system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses
513system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses
514system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses
515system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses
516system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses
517system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses
518system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
519system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses
520system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses
521system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
522system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
523system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
524system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
525system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency
526system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
527system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
528system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
529system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
530system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
531system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
532system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
533system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency
534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
540system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
541system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
542system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses
543system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses
544system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses
545system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses
546system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses
547system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses
548system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
549system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
550system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
551system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
552system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
553system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
554system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
555system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles
556system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
557system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
558system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
559system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
560system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
561system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
562system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
563system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
564system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
565system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
566system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
567system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses
568system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses
569system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses
570system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
571system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
572system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
573system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
574system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
575system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
576system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
577system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
578system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
579system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
580system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
581system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
583system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
584system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
586system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
587system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
588system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
589system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
590system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
591system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
592system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
593system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

467system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
468system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
469system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
470system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
471system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
472system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
473system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
474system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits
475system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits
476system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits
477system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits
478system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits
479system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
480system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits
481system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits
482system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
483system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
484system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
485system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses
486system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses
487system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses
488system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses
489system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses
490system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses
491system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
492system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses
493system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses
494system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
495system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles
496system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles
497system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles
498system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles
499system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
500system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles
501system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles
502system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles
503system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles
504system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles
505system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles
506system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles
507system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses)
508system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses)
509system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses)
510system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses)
511system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
512system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
513system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses)
514system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses)
515system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses)
516system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses)
517system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
518system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
519system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
520system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
521system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
522system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
523system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
524system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
525system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses
526system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses
527system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses
528system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses
529system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses
530system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses
531system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
532system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses
533system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses
534system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
535system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
536system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
537system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
538system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency
539system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
540system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
541system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
542system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
543system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
544system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
545system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
546system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency
547system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
548system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
549system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
550system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
551system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
552system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
553system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
554system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
555system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses
556system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses
557system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses
558system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses
559system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses
560system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses
561system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
562system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
563system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
564system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
565system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
566system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
567system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
568system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles
569system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
570system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
571system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
572system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
573system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
574system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
575system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
576system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
577system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
578system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
579system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
580system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses
581system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses
582system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses
583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
584system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
585system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
586system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
587system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
588system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
589system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
591system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
592system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
593system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
594system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
595system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
596system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
597system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
598system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
600system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
601system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
602system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
603system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
604system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
605system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
606system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

607system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states

594system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
595system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
596system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
597system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
598system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
599system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
600system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
601system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
602system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
603system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
604system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
605system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
606system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
607system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)
608system.cpu.toL2Bus.snoops 0 # Total snoops (count)
609system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
610system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
611system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram
612system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
613system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
614system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram
615system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
616system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
617system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
618system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
619system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
620system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
621system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
622system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
623system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
624system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
625system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

608system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
611system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
612system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
613system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
614system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
615system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
616system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
617system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
618system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
619system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
620system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
621system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)
622system.cpu.toL2Bus.snoops 0 # Total snoops (count)
623system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
624system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
625system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram
626system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
627system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
628system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram
629system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
630system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
631system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
632system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
633system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
634system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
635system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
636system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
637system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
638system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
639system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

640system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states