Cross Reference: /gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt

stats.txt (10352:5f1f92bf76ee)	stats.txt (10409:8c80b91944c5)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517235 # Number of seconds simulated 4sim_ticks 517235411000 # Number of ticks simulated 5final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.517235 # Number of seconds simulated 4sim_ticks 517235411000 # Number of ticks simulated 5final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 749544 # Simulator instruction rate (inst/s) 8host_op_rate 899855 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1421469107 # Simulator tick rate (ticks/s) 10host_mem_usage 324416 # Number of bytes of host memory used 11host_seconds 363.87 # Real time elapsed on the host	7host_inst_rate 795879 # Simulator instruction rate (inst/s) 8host_op_rate 955482 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1509341441 # Simulator tick rate (ticks/s) 10host_mem_usage 314596 # Number of bytes of host memory used 11host_seconds 342.69 # Real time elapsed on the host
12sim_insts 272739285 # Number of instructions simulated 13sim_ops 327433743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)	12sim_insts 272739285 # Number of instructions simulated 13sim_ops 327433743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
32system.membus.throughput 845356 # Throughput (bytes/s)
33system.membus.trans_dist::ReadReq 3976 # Transaction distribution 34system.membus.trans_dist::ReadResp 3976 # Transaction distribution 35system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 36system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)	32system.membus.trans_dist::ReadReq 3976 # Transaction distribution 33system.membus.trans_dist::ReadResp 3976 # Transaction distribution 34system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 35system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 437248 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)	38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 39system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) 40system.membus.snoops 0 # Total snoops (count) 41system.membus.snoop_fanout::samples 6833 # Request fanout histogram 42system.membus.snoop_fanout::mean 0 # Request fanout histogram 43system.membus.snoop_fanout::stdev 0 # Request fanout histogram 44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram 46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::min_value 0 # Request fanout histogram 49system.membus.snoop_fanout::max_value 0 # Request fanout histogram 50system.membus.snoop_fanout::total 6833 # Request fanout histogram
43system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 45system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.inst_hits 0 # ITB inst hits 70system.cpu.dtb.inst_misses 0 # ITB inst misses 71system.cpu.dtb.read_hits 0 # DTB read hits 72system.cpu.dtb.read_misses 0 # DTB read misses 73system.cpu.dtb.write_hits 0 # DTB write hits 74system.cpu.dtb.write_misses 0 # DTB write misses 75system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 76system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 77system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 78system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 79system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 80system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 81system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 82system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 83system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 84system.cpu.dtb.read_accesses 0 # DTB read accesses 85system.cpu.dtb.write_accesses 0 # DTB write accesses 86system.cpu.dtb.inst_accesses 0 # ITB inst accesses 87system.cpu.dtb.hits 0 # DTB hits 88system.cpu.dtb.misses 0 # DTB misses 89system.cpu.dtb.accesses 0 # DTB accesses 90system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 91system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 92system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 93system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 94system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 95system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 96system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 97system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 98system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 99system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 100system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 101system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 102system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 103system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 104system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 105system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 106system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 107system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 108system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 109system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 110system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 111system.cpu.itb.inst_hits 0 # ITB inst hits 112system.cpu.itb.inst_misses 0 # ITB inst misses 113system.cpu.itb.read_hits 0 # DTB read hits 114system.cpu.itb.read_misses 0 # DTB read misses 115system.cpu.itb.write_hits 0 # DTB write hits 116system.cpu.itb.write_misses 0 # DTB write misses 117system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.itb.read_accesses 0 # DTB read accesses 127system.cpu.itb.write_accesses 0 # DTB write accesses 128system.cpu.itb.inst_accesses 0 # ITB inst accesses 129system.cpu.itb.hits 0 # DTB hits 130system.cpu.itb.misses 0 # DTB misses 131system.cpu.itb.accesses 0 # DTB accesses 132system.cpu.workload.num_syscalls 191 # Number of system calls 133system.cpu.numCycles 1034470822 # number of cpu cycles simulated 134system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 135system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 136system.cpu.committedInsts 272739285 # Number of instructions committed 137system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed 138system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses 139system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 140system.cpu.num_func_calls 12448615 # number of times a function call or return occured 141system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls 142system.cpu.num_int_insts 258331537 # number of integer instructions 143system.cpu.num_fp_insts 114216705 # number of float instructions 144system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read 145system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written 146system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 147system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 148system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read 149system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written 150system.cpu.num_mem_refs 168107847 # number of memory refs 151system.cpu.num_load_insts 85732248 # Number of load instructions 152system.cpu.num_store_insts 82375599 # Number of store instructions 153system.cpu.num_idle_cycles 0 # Number of idle cycles 154system.cpu.num_busy_cycles 1034470822 # Number of busy cycles 155system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 156system.cpu.idle_fraction 0 # Percentage of idle cycles 157system.cpu.Branches 30563502 # Number of branches fetched 158system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 159system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction 160system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction 161system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction 162system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction 163system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction 164system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction 165system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction 166system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction 167system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction 168system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction 169system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction 170system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction 171system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction 172system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction 173system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction 174system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction 175system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction 176system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction 177system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction 178system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction 179system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction 180system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction 181system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction 182system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction 183system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction 184system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction 185system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction 186system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 187system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 188system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 189system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 190system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 191system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 192system.cpu.op_class::total 327812213 # Class of executed instruction 193system.cpu.icache.tags.replacements 13796 # number of replacements 194system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use 195system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. 196system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 197system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. 198system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 199system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor 200system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy 201system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy 202system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 203system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 204system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 205system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 206system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 207system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id 208system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id 209system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses 210system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses 211system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits 212system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits 213system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits 214system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits 215system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits 216system.cpu.icache.overall_hits::total 348644749 # number of overall hits 217system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 218system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 219system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 220system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 221system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 222system.cpu.icache.overall_misses::total 15603 # number of overall misses 223system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles 224system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles 225system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles 226system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles 227system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles 228system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles 229system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) 230system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) 231system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses 232system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses 233system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses 234system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses 235system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 236system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 237system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 238system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 239system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 240system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 241system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency 242system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency 243system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency 244system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency 245system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency 246system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency 247system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 248system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 249system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 250system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 251system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 252system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 253system.cpu.icache.fast_writes 0 # number of fast writes performed 254system.cpu.icache.cache_copies 0 # number of cache copies performed 255system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 256system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 257system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 258system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 259system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 260system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses 261system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles 262system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles 263system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles 264system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles 265system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles 266system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles 267system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 268system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 269system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 270system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 271system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 272system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 273system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency 274system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency 275system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency 276system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency 277system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency 278system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency 279system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 280system.cpu.l2cache.tags.replacements 0 # number of replacements 281system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use 282system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. 283system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 284system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. 285system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 286system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor 287system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor 288system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor 289system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy 290system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy 291system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy 292system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy 293system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id 294system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 295system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 296system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 297system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id 298system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id 299system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id 300system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses 301system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses 302system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits 303system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits 304system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits 305system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits 306system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits 307system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 308system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 309system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits 310system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits 311system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits 312system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits 313system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits 314system.cpu.l2cache.overall_hits::total 13249 # number of overall hits 315system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses 316system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses 317system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses 318system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 319system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 320system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses 321system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses 322system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 323system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses 324system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses 325system.cpu.l2cache.overall_misses::total 6832 # number of overall misses 326system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles 327system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles 328system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles 329system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles 330system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles 331system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles 332system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles 333system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles 334system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles 335system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles 336system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles 337system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) 338system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) 339system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) 340system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) 341system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) 342system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 343system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 344system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses 345system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses 346system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses 347system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses 348system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses 349system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses 350system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses 351system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses 352system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses 353system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 354system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 355system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses 356system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses 357system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 358system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses 359system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses 360system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses 361system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency 362system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency 363system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency 364system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency 365system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency 366system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency 367system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency 368system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency 370system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency 371system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency 372system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 375system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 376system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 377system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 378system.cpu.l2cache.fast_writes 0 # number of fast writes performed 379system.cpu.l2cache.cache_copies 0 # number of cache copies performed 380system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses 381system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses 382system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses 383system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 384system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 385system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses 386system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses 387system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 388system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses 389system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses 390system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses 391system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles 392system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles 393system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles 394system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles 395system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles 397system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles 398system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles 399system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles 400system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles 401system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles 402system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses 403system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses 404system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses 405system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 406system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 407system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses 408system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses 409system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 410system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses 411system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses 412system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses 413system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency 414system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 415system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency 416system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency 417system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency 420system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency 424system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 425system.cpu.dcache.tags.replacements 1332 # number of replacements 426system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use 427system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 428system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 429system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 430system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 431system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor 432system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy 433system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy 434system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 435system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 436system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 437system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 438system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 439system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 440system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 441system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses 442system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses 443system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits 444system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits 445system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 446system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 447system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits 448system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits 449system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 450system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 451system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 452system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 453system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits 454system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits 455system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits 456system.cpu.dcache.overall_hits::total 168337827 # number of overall hits 457system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses 458system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses 459system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 460system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 461system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 462system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 463system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses 464system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses 465system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses 466system.cpu.dcache.overall_misses::total 4479 # number of overall misses 467system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles 468system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles 469system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles 470system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles 471system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles 472system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles 473system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles 474system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles 475system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) 476system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) 477system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 478system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 479system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) 480system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) 481system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 485system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses 486system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses 487system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses 488system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses 489system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses 490system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses 491system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 492system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 493system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses 494system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses 495system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses 496system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 497system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses 498system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 499system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency 500system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency 501system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency 502system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency 503system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency 504system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency 506system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency 507system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 508system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 509system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 510system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 511system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 512system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 513system.cpu.dcache.fast_writes 0 # number of fast writes performed 514system.cpu.dcache.cache_copies 0 # number of cache copies performed 515system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 516system.cpu.dcache.writebacks::total 998 # number of writebacks 517system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 518system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 519system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 520system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 521system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 522system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 523system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses 524system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses 525system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 526system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 527system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 528system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 529system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses 530system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses 531system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 532system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 533system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles 534system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles 538system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles 539system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles 540system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles 541system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles 542system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles 543system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 544system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 545system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 546system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 547system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses 548system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses 549system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 550system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 551system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 552system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency 554system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency 555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency 556system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency 557system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency 558system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency 559system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency 560system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency 561system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency 562system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency 563system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate	51system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 53system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 67system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 68system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 109system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 110system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 119system.cpu.itb.inst_hits 0 # ITB inst hits 120system.cpu.itb.inst_misses 0 # ITB inst misses 121system.cpu.itb.read_hits 0 # DTB read hits 122system.cpu.itb.read_misses 0 # DTB read misses 123system.cpu.itb.write_hits 0 # DTB write hits 124system.cpu.itb.write_misses 0 # DTB write misses 125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 127system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 128system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 129system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 130system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 131system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 132system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 133system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 134system.cpu.itb.read_accesses 0 # DTB read accesses 135system.cpu.itb.write_accesses 0 # DTB write accesses 136system.cpu.itb.inst_accesses 0 # ITB inst accesses 137system.cpu.itb.hits 0 # DTB hits 138system.cpu.itb.misses 0 # DTB misses 139system.cpu.itb.accesses 0 # DTB accesses 140system.cpu.workload.num_syscalls 191 # Number of system calls 141system.cpu.numCycles 1034470822 # number of cpu cycles simulated 142system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 143system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 144system.cpu.committedInsts 272739285 # Number of instructions committed 145system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed 146system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses 147system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 148system.cpu.num_func_calls 12448615 # number of times a function call or return occured 149system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls 150system.cpu.num_int_insts 258331537 # number of integer instructions 151system.cpu.num_fp_insts 114216705 # number of float instructions 152system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read 153system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written 154system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 155system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 156system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read 157system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written 158system.cpu.num_mem_refs 168107847 # number of memory refs 159system.cpu.num_load_insts 85732248 # Number of load instructions 160system.cpu.num_store_insts 82375599 # Number of store instructions 161system.cpu.num_idle_cycles 0 # Number of idle cycles 162system.cpu.num_busy_cycles 1034470822 # Number of busy cycles 163system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 164system.cpu.idle_fraction 0 # Percentage of idle cycles 165system.cpu.Branches 30563502 # Number of branches fetched 166system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 167system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction 168system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction 169system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction 170system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction 171system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction 172system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction 173system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction 174system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction 175system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction 176system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction 177system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction 178system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction 179system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction 180system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction 181system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction 182system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction 183system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction 184system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction 185system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction 186system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction 187system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction 188system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction 189system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction 190system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction 191system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction 192system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction 193system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction 194system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 195system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 196system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 197system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 198system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 199system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 200system.cpu.op_class::total 327812213 # Class of executed instruction 201system.cpu.icache.tags.replacements 13796 # number of replacements 202system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use 203system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. 204system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 205system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. 206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 207system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor 208system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy 209system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy 210system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 211system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 212system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 213system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 214system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 215system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id 216system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id 217system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses 218system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses 219system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits 220system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits 221system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits 222system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits 223system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits 224system.cpu.icache.overall_hits::total 348644749 # number of overall hits 225system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 226system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 227system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 228system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 229system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 230system.cpu.icache.overall_misses::total 15603 # number of overall misses 231system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles 232system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles 233system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles 234system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles 235system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles 236system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles 237system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) 238system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) 239system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses 240system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses 241system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses 242system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses 243system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 244system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 245system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 246system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 247system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 248system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 249system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency 250system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency 251system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency 252system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency 253system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency 254system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency 255system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 256system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 257system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 258system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 259system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 260system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 261system.cpu.icache.fast_writes 0 # number of fast writes performed 262system.cpu.icache.cache_copies 0 # number of cache copies performed 263system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 264system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 265system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 266system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 267system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 268system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses 269system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles 270system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles 271system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles 272system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles 273system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles 274system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles 275system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 276system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 277system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 278system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 279system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 280system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 281system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency 282system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency 283system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency 284system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency 285system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency 286system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency 287system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 288system.cpu.l2cache.tags.replacements 0 # number of replacements 289system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use 290system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. 291system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 292system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. 293system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 294system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor 295system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor 296system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor 297system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy 298system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy 299system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy 300system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy 301system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id 302system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 303system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 304system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 305system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id 306system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id 307system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id 308system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses 309system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses 310system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits 311system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits 312system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits 313system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits 314system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits 315system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 316system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 317system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits 318system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits 319system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits 320system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits 321system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits 322system.cpu.l2cache.overall_hits::total 13249 # number of overall hits 323system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses 324system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses 325system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses 326system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 327system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 328system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses 329system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses 330system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 331system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses 332system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses 333system.cpu.l2cache.overall_misses::total 6832 # number of overall misses 334system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles 335system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles 336system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles 337system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles 338system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles 339system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles 340system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles 341system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles 342system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles 343system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles 344system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles 345system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) 346system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) 347system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) 348system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) 349system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) 350system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 351system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 352system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses 353system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses 354system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses 355system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses 356system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses 357system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses 358system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses 359system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses 360system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses 361system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 362system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 363system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses 364system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses 365system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 366system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses 367system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses 368system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses 369system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency 370system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency 371system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency 372system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency 373system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency 374system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency 375system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency 376system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency 377system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency 378system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency 379system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency 380system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 381system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 382system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 383system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 384system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 385system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 386system.cpu.l2cache.fast_writes 0 # number of fast writes performed 387system.cpu.l2cache.cache_copies 0 # number of cache copies performed 388system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses 389system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses 390system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses 391system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 392system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 393system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses 394system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses 395system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 396system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses 397system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses 398system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses 399system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles 400system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles 401system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles 402system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles 403system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles 404system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles 405system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles 406system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles 407system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles 408system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles 409system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles 410system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses 411system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses 412system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses 413system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 414system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 415system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses 416system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses 417system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 418system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses 419system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses 420system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses 421system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency 422system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 423system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency 424system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency 425system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency 426system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency 427system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency 428system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency 429system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency 430system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency 431system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency 432system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 433system.cpu.dcache.tags.replacements 1332 # number of replacements 434system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use 435system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 436system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 437system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 438system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 439system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor 440system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy 441system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy 442system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 445system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 446system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 447system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 448system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 449system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses 450system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses 451system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits 452system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits 453system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 454system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 455system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits 456system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits 457system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 458system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 459system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 460system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 461system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits 462system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits 463system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits 464system.cpu.dcache.overall_hits::total 168337827 # number of overall hits 465system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses 466system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses 467system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 468system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 469system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 470system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 471system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses 472system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses 473system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses 474system.cpu.dcache.overall_misses::total 4479 # number of overall misses 475system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles 476system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles 477system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles 478system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles 479system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles 480system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles 481system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles 482system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles 483system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) 484system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) 485system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 486system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 487system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) 488system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) 489system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 490system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 491system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 492system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 493system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses 494system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses 495system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses 496system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses 497system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses 498system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses 499system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 500system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 501system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses 502system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses 503system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses 504system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 505system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses 506system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 507system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency 508system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency 509system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency 510system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency 511system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency 512system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency 513system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency 514system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency 515system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 516system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 517system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 518system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 519system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 520system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 521system.cpu.dcache.fast_writes 0 # number of fast writes performed 522system.cpu.dcache.cache_copies 0 # number of cache copies performed 523system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 524system.cpu.dcache.writebacks::total 998 # number of writebacks 525system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 526system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 527system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 528system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 529system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 530system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 531system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses 532system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses 533system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 534system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 535system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 536system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 537system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses 538system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses 539system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 540system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 541system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles 543system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles 544system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles 545system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles 546system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles 547system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles 548system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles 549system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles 550system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles 551system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 552system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 553system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 554system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 555system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses 556system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses 557system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 558system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 559system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 560system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency 562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency 563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency 564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency 565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency 566system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency 567system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency 568system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency 569system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency 570system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency 571system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
564system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s)
565system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution 566system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 567system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution 568system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 569system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 570system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) 571system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) 572system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes)	572system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution 573system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 577system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) 578system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) 579system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes)
573system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) 574system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) 575system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) 576system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes) 577system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)	580system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) 582system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) 583system.cpu.toL2Bus.snoops 0 # Total snoops (count) 584system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram 585system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 586system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 587system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 588system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 589system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 590system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 591system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 592system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 593system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram 594system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 595system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 596system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 597system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram
578system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) 579system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 580system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 581system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 582system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 583system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 584 585---------- End Simulation Statistics ----------	599system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) 600system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 601system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 602system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 603system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 604system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 605 606---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.517235 # Number of seconds simulated
4sim_ticks 517235411000 # Number of ticks simulated
5final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 749544 # Simulator instruction rate (inst/s)
8host_op_rate 899855 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1421469107 # Simulator tick rate (ticks/s)
10host_mem_usage 324416 # Number of bytes of host memory used
11host_seconds 363.87 # Real time elapsed on the host

7host_inst_rate 795879 # Simulator instruction rate (inst/s)
8host_op_rate 955482 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1509341441 # Simulator tick rate (ticks/s)
10host_mem_usage 314596 # Number of bytes of host memory used
11host_seconds 342.69 # Real time elapsed on the host

12sim_insts 272739285 # Number of instructions simulated
13sim_ops 327433743 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory
18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)

32system.membus.throughput 845356 # Throughput (bytes/s)

33system.membus.trans_dist::ReadReq 3976 # Transaction distribution
34system.membus.trans_dist::ReadResp 3976 # Transaction distribution
35system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
36system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
38system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)

32system.membus.trans_dist::ReadReq 3976 # Transaction distribution
33system.membus.trans_dist::ReadResp 3976 # Transaction distribution
34system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
35system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
37system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)

39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
40system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
41system.membus.data_through_bus 437248 # Total data (bytes)
42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)

38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
39system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
40system.membus.snoops 0 # Total snoops (count)
41system.membus.snoop_fanout::samples 6833 # Request fanout histogram
42system.membus.snoop_fanout::mean 0 # Request fanout histogram
43system.membus.snoop_fanout::stdev 0 # Request fanout histogram
44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
45system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
48system.membus.snoop_fanout::min_value 0 # Request fanout histogram
49system.membus.snoop_fanout::max_value 0 # Request fanout histogram
50system.membus.snoop_fanout::total 6833 # Request fanout histogram

43system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
44system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
45system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
46system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
47system.cpu_clk_domain.clock 500 # Clock period in ticks
48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
69system.cpu.dtb.inst_hits 0 # ITB inst hits
70system.cpu.dtb.inst_misses 0 # ITB inst misses
71system.cpu.dtb.read_hits 0 # DTB read hits
72system.cpu.dtb.read_misses 0 # DTB read misses
73system.cpu.dtb.write_hits 0 # DTB write hits
74system.cpu.dtb.write_misses 0 # DTB write misses
75system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
76system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
77system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
78system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
79system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
80system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
81system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
82system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
83system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
84system.cpu.dtb.read_accesses 0 # DTB read accesses
85system.cpu.dtb.write_accesses 0 # DTB write accesses
86system.cpu.dtb.inst_accesses 0 # ITB inst accesses
87system.cpu.dtb.hits 0 # DTB hits
88system.cpu.dtb.misses 0 # DTB misses
89system.cpu.dtb.accesses 0 # DTB accesses
90system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
91system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
92system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
93system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
94system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
95system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
96system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
97system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
98system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
99system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
100system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
101system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
102system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
103system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
104system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
105system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
106system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
107system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
108system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
109system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
110system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
111system.cpu.itb.inst_hits 0 # ITB inst hits
112system.cpu.itb.inst_misses 0 # ITB inst misses
113system.cpu.itb.read_hits 0 # DTB read hits
114system.cpu.itb.read_misses 0 # DTB read misses
115system.cpu.itb.write_hits 0 # DTB write hits
116system.cpu.itb.write_misses 0 # DTB write misses
117system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
118system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
119system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
120system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
121system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
122system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
123system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
124system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
125system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
126system.cpu.itb.read_accesses 0 # DTB read accesses
127system.cpu.itb.write_accesses 0 # DTB write accesses
128system.cpu.itb.inst_accesses 0 # ITB inst accesses
129system.cpu.itb.hits 0 # DTB hits
130system.cpu.itb.misses 0 # DTB misses
131system.cpu.itb.accesses 0 # DTB accesses
132system.cpu.workload.num_syscalls 191 # Number of system calls
133system.cpu.numCycles 1034470822 # number of cpu cycles simulated
134system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
135system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
136system.cpu.committedInsts 272739285 # Number of instructions committed
137system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed
138system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
139system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
140system.cpu.num_func_calls 12448615 # number of times a function call or return occured
141system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
142system.cpu.num_int_insts 258331537 # number of integer instructions
143system.cpu.num_fp_insts 114216705 # number of float instructions
144system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
145system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
146system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
147system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
148system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read
149system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
150system.cpu.num_mem_refs 168107847 # number of memory refs
151system.cpu.num_load_insts 85732248 # Number of load instructions
152system.cpu.num_store_insts 82375599 # Number of store instructions
153system.cpu.num_idle_cycles 0 # Number of idle cycles
154system.cpu.num_busy_cycles 1034470822 # Number of busy cycles
155system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
156system.cpu.idle_fraction 0 # Percentage of idle cycles
157system.cpu.Branches 30563502 # Number of branches fetched
158system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
159system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction
160system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
161system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
162system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
163system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
164system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
165system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
166system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
167system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
168system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
169system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
170system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
171system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
172system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
173system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
174system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
175system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
176system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
177system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
178system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
179system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
180system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
181system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
182system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
183system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
184system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
185system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
186system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
187system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
188system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
189system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
190system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
191system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
192system.cpu.op_class::total 327812213 # Class of executed instruction
193system.cpu.icache.tags.replacements 13796 # number of replacements
194system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use
195system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks.
196system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
197system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks.
198system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
199system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor
200system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy
201system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy
202system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
203system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
204system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
205system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
206system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
207system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
208system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
209system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses
210system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses
211system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits
212system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits
213system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits
214system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits
215system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits
216system.cpu.icache.overall_hits::total 348644749 # number of overall hits
217system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
218system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
219system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
220system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
221system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
222system.cpu.icache.overall_misses::total 15603 # number of overall misses
223system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles
224system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles
225system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles
226system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles
227system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles
228system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles
229system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses)
230system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses)
231system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses
232system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses
233system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses
234system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses
235system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
236system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
237system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
238system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
239system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
240system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
241system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency
242system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency
243system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
244system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency
245system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
246system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency
247system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
248system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
249system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
250system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
251system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
252system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
253system.cpu.icache.fast_writes 0 # number of fast writes performed
254system.cpu.icache.cache_copies 0 # number of cache copies performed
255system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
256system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
257system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
258system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
259system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
260system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
261system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles
262system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles
263system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles
264system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles
265system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles
266system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles
267system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
268system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
269system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
270system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
271system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
272system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
273system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency
274system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency
275system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
276system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
277system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
278system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
279system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
280system.cpu.l2cache.tags.replacements 0 # number of replacements
281system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use
282system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks.
283system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
284system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks.
285system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
286system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor
287system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor
288system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor
289system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy
290system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy
291system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
292system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy
293system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
294system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
295system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
296system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
297system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
298system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
299system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
300system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses
301system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses
302system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits
303system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
304system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits
305system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
306system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
307system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
308system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
309system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits
310system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
311system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
312system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits
313system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
314system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
315system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses
316system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses
317system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses
318system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
319system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
320system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses
321system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses
322system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
323system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses
324system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
325system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
326system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles
327system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles
328system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles
329system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles
330system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles
331system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles
332system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles
333system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles
334system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles
335system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles
336system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles
337system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
338system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
339system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
340system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses)
341system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses)
342system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
343system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
344system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
345system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
346system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
347system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
348system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
349system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
350system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses
351system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses
352system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses
353system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
354system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
355system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses
356system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses
357system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
358system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses
359system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
360system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
361system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency
362system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency
363system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency
364system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency
365system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency
366system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
367system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
368system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency
369system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
370system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
371system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency
372system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
373system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
374system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
375system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
376system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
377system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
378system.cpu.l2cache.fast_writes 0 # number of fast writes performed
379system.cpu.l2cache.cache_copies 0 # number of cache copies performed
380system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses
381system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses
382system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses
383system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
384system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
385system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses
386system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses
387system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
388system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
389system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
390system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
391system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles
392system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
393system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles
394system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles
395system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles
396system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles
397system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles
398system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles
399system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles
400system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles
401system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles
402system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses
403system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
404system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses
405system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
406system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
407system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses
408system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses
409system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
410system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses
411system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
412system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
413system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency
414system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
415system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency
416system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency
417system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency
418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
419system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
420system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
422system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
423system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
424system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
425system.cpu.dcache.tags.replacements 1332 # number of replacements
426system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use
427system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
428system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
429system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
430system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
431system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor
432system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy
433system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy
434system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
435system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
436system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
437system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
438system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
439system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
440system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
441system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
442system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
443system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
444system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
445system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
446system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
447system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
448system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
449system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
450system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
451system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
452system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
453system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
454system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
455system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
456system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
457system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
458system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
459system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
460system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
461system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
462system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
463system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
464system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
465system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
466system.cpu.dcache.overall_misses::total 4479 # number of overall misses
467system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles
468system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles
469system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles
470system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles
471system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles
472system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles
473system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles
474system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles
475system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
476system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
477system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
478system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
479system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
480system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
481system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
482system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
483system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
484system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
485system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
486system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
487system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
488system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
489system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
490system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
491system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
492system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
493system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
494system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
495system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
496system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
497system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
498system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
499system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency
500system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency
501system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency
502system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency
503system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency
504system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency
505system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency
506system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency
507system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
508system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
509system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
510system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
511system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
512system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
513system.cpu.dcache.fast_writes 0 # number of fast writes performed
514system.cpu.dcache.cache_copies 0 # number of cache copies performed
515system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
516system.cpu.dcache.writebacks::total 998 # number of writebacks
517system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
518system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
519system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
520system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
521system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
522system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
523system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
524system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
525system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
526system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
527system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
528system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
529system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
530system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
531system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
532system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
533system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles
534system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles
535system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles
536system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles
537system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles
538system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles
539system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles
540system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles
541system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles
542system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles
543system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
544system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
545system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
546system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
547system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
548system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
549system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
550system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
551system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
552system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency
554system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency
555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency
556system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency
557system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
558system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
559system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency
560system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency
561system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
562system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
563system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

51system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
52system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
53system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
54system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
55system.cpu_clk_domain.clock 500 # Clock period in ticks
56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
64system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
65system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
66system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
67system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
68system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
77system.cpu.dtb.inst_hits 0 # ITB inst hits
78system.cpu.dtb.inst_misses 0 # ITB inst misses
79system.cpu.dtb.read_hits 0 # DTB read hits
80system.cpu.dtb.read_misses 0 # DTB read misses
81system.cpu.dtb.write_hits 0 # DTB write hits
82system.cpu.dtb.write_misses 0 # DTB write misses
83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
92system.cpu.dtb.read_accesses 0 # DTB read accesses
93system.cpu.dtb.write_accesses 0 # DTB write accesses
94system.cpu.dtb.inst_accesses 0 # ITB inst accesses
95system.cpu.dtb.hits 0 # DTB hits
96system.cpu.dtb.misses 0 # DTB misses
97system.cpu.dtb.accesses 0 # DTB accesses
98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
108system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
109system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
110system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
119system.cpu.itb.inst_hits 0 # ITB inst hits
120system.cpu.itb.inst_misses 0 # ITB inst misses
121system.cpu.itb.read_hits 0 # DTB read hits
122system.cpu.itb.read_misses 0 # DTB read misses
123system.cpu.itb.write_hits 0 # DTB write hits
124system.cpu.itb.write_misses 0 # DTB write misses
125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
127system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
128system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
129system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
130system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
131system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
132system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
133system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
134system.cpu.itb.read_accesses 0 # DTB read accesses
135system.cpu.itb.write_accesses 0 # DTB write accesses
136system.cpu.itb.inst_accesses 0 # ITB inst accesses
137system.cpu.itb.hits 0 # DTB hits
138system.cpu.itb.misses 0 # DTB misses
139system.cpu.itb.accesses 0 # DTB accesses
140system.cpu.workload.num_syscalls 191 # Number of system calls
141system.cpu.numCycles 1034470822 # number of cpu cycles simulated
142system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
143system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
144system.cpu.committedInsts 272739285 # Number of instructions committed
145system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed
146system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
147system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
148system.cpu.num_func_calls 12448615 # number of times a function call or return occured
149system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
150system.cpu.num_int_insts 258331537 # number of integer instructions
151system.cpu.num_fp_insts 114216705 # number of float instructions
152system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
153system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
154system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
155system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
156system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read
157system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
158system.cpu.num_mem_refs 168107847 # number of memory refs
159system.cpu.num_load_insts 85732248 # Number of load instructions
160system.cpu.num_store_insts 82375599 # Number of store instructions
161system.cpu.num_idle_cycles 0 # Number of idle cycles
162system.cpu.num_busy_cycles 1034470822 # Number of busy cycles
163system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
164system.cpu.idle_fraction 0 # Percentage of idle cycles
165system.cpu.Branches 30563502 # Number of branches fetched
166system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
167system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction
168system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
169system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
170system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
171system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
172system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
173system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
174system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
175system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
176system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
177system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
178system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
179system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
180system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
181system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
182system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
183system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
184system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
185system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
186system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
187system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
188system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
189system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
190system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
191system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
192system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
193system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
194system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
195system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
196system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
197system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
198system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
199system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
200system.cpu.op_class::total 327812213 # Class of executed instruction
201system.cpu.icache.tags.replacements 13796 # number of replacements
202system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use
203system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks.
204system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
205system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks.
206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
207system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor
208system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy
209system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy
210system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
211system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
212system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
213system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
214system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
215system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
216system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
217system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses
218system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses
219system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits
220system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits
221system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits
222system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits
223system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits
224system.cpu.icache.overall_hits::total 348644749 # number of overall hits
225system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
226system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
227system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
228system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
229system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
230system.cpu.icache.overall_misses::total 15603 # number of overall misses
231system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles
232system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles
233system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles
234system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles
235system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles
236system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles
237system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses)
238system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses)
239system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses
240system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses
241system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses
242system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses
243system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
244system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
245system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
246system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
247system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
248system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
249system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency
250system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency
251system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
252system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency
253system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
254system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency
255system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
256system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
257system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
258system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
259system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
260system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
261system.cpu.icache.fast_writes 0 # number of fast writes performed
262system.cpu.icache.cache_copies 0 # number of cache copies performed
263system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
264system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
265system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
266system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
267system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
268system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
269system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles
270system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles
271system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles
272system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles
273system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles
274system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles
275system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
276system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
277system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
278system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
279system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
280system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
281system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency
282system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency
283system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
284system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
285system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
286system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
287system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
288system.cpu.l2cache.tags.replacements 0 # number of replacements
289system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use
290system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks.
291system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
292system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks.
293system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
294system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor
295system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor
296system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor
297system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy
298system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy
299system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
300system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy
301system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
302system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
303system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
304system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
305system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
306system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
307system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
308system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses
309system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses
310system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits
311system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
312system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits
313system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
314system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
315system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
316system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
317system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits
318system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
319system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
320system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits
321system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
322system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
323system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses
324system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses
325system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses
326system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
327system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
328system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses
329system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses
330system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
331system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses
332system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
333system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
334system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles
335system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles
336system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles
337system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles
338system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles
339system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles
340system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles
341system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles
342system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles
343system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles
344system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles
345system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
346system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
347system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
348system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses)
349system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses)
350system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
351system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
352system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
353system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
354system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
355system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
356system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
357system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
358system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses
359system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses
360system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses
361system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
362system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
363system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses
364system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses
365system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
366system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses
367system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
368system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
369system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency
370system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency
371system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency
372system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency
373system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency
374system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
375system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
376system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency
377system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
378system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
379system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency
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381system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
382system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
383system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
384system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
385system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
386system.cpu.l2cache.fast_writes 0 # number of fast writes performed
387system.cpu.l2cache.cache_copies 0 # number of cache copies performed
388system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses
389system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses
390system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses
391system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
392system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
393system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses
394system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses
395system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
396system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
397system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
398system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
399system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles
400system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
401system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles
402system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles
403system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles
404system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles
405system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles
406system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles
407system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles
408system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles
409system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles
410system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses
411system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
412system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses
413system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
414system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
415system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses
416system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses
417system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
418system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses
419system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
420system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
421system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency
422system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
423system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency
424system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency
425system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency
426system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
427system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
428system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
429system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
430system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
431system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
432system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
433system.cpu.dcache.tags.replacements 1332 # number of replacements
434system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use
435system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
436system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
437system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
438system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
439system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor
440system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy
441system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy
442system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
443system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
444system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
445system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
446system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
447system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
448system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
449system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
450system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
451system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
452system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
453system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
454system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
455system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
456system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
457system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
458system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
459system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
460system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
461system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
462system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
463system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
464system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
465system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
466system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
467system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
468system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
469system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
470system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
471system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
472system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
473system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
474system.cpu.dcache.overall_misses::total 4479 # number of overall misses
475system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles
476system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles
477system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles
478system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles
479system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles
480system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles
481system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles
482system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles
483system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
484system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
485system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
486system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
487system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
488system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
489system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
490system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
491system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
492system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
493system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
494system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
495system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
496system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
497system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
498system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
499system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
500system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
501system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
502system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
503system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
504system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
505system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
506system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
507system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency
508system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency
509system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency
510system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency
511system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency
512system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency
513system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency
514system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency
515system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
516system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
517system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
518system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
519system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
520system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
521system.cpu.dcache.fast_writes 0 # number of fast writes performed
522system.cpu.dcache.cache_copies 0 # number of cache copies performed
523system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
524system.cpu.dcache.writebacks::total 998 # number of writebacks
525system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
526system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
527system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
528system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
529system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
530system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
531system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
532system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
533system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
534system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
535system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
536system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
537system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
538system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
539system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
540system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
541system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles
542system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles
543system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles
544system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles
545system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles
546system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles
547system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles
548system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles
549system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles
550system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles
551system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
552system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
553system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
554system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
555system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
556system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
557system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
558system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
559system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
560system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency
562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency
563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency
564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency
565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
566system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
567system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency
568system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency
569system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
570system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
571system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

564system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s)

565system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution
566system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
567system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
568system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
569system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
570system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes)
571system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes)
572system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes)

572system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution
573system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
574system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
575system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
576system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
577system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes)
578system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes)
579system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes)

573system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
574system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
575system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
576system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes)
577system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)

580system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
581system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
582system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
583system.cpu.toL2Bus.snoops 0 # Total snoops (count)
584system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram
585system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
586system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
587system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
588system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
589system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
590system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
591system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
592system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
593system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram
594system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
595system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
596system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
597system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
598system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram