Cross Reference: /gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt

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1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.525834 # Number of seconds simulated 4sim_ticks 525834342000 # Number of ticks simulated 5final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.525834 # Number of seconds simulated 4sim_ticks 525834342000 # Number of ticks simulated 5final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 485432 # Simulator instruction rate (inst/s) 8host_op_rate 620607 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 935900071 # Simulator tick rate (ticks/s) 10host_mem_usage 332908 # Number of bytes of host memory used 11host_seconds 561.85 # Real time elapsed on the host	7host_inst_rate 605985 # Simulator instruction rate (inst/s) 8host_op_rate 774729 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1168322503 # Simulator tick rate (ticks/s) 10host_mem_usage 318808 # Number of bytes of host memory used 11host_seconds 450.08 # Real time elapsed on the host
12sim_insts 272739283 # Number of instructions simulated 13sim_ops 348687122 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) 32system.membus.throughput 831532 # Throughput (bytes/s) 33system.membus.trans_dist::ReadReq 3976 # Transaction distribution 34system.membus.trans_dist::ReadResp 3976 # Transaction distribution 35system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 36system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 437248 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 43system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 45system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.inst_hits 0 # ITB inst hits 70system.cpu.dtb.inst_misses 0 # ITB inst misses 71system.cpu.dtb.read_hits 0 # DTB read hits 72system.cpu.dtb.read_misses 0 # DTB read misses 73system.cpu.dtb.write_hits 0 # DTB write hits 74system.cpu.dtb.write_misses 0 # DTB write misses 75system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 76system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 77system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 78system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 79system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 80system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 81system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 82system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 83system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 84system.cpu.dtb.read_accesses 0 # DTB read accesses 85system.cpu.dtb.write_accesses 0 # DTB write accesses 86system.cpu.dtb.inst_accesses 0 # ITB inst accesses 87system.cpu.dtb.hits 0 # DTB hits 88system.cpu.dtb.misses 0 # DTB misses 89system.cpu.dtb.accesses 0 # DTB accesses 90system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 91system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 92system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 93system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 94system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 95system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 96system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 97system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 98system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 99system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 100system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 101system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 102system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 103system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 104system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 105system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 106system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 107system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 108system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 109system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 110system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 111system.cpu.itb.inst_hits 0 # ITB inst hits 112system.cpu.itb.inst_misses 0 # ITB inst misses 113system.cpu.itb.read_hits 0 # DTB read hits 114system.cpu.itb.read_misses 0 # DTB read misses 115system.cpu.itb.write_hits 0 # DTB write hits 116system.cpu.itb.write_misses 0 # DTB write misses 117system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.itb.read_accesses 0 # DTB read accesses 127system.cpu.itb.write_accesses 0 # DTB write accesses 128system.cpu.itb.inst_accesses 0 # ITB inst accesses 129system.cpu.itb.hits 0 # DTB hits 130system.cpu.itb.misses 0 # DTB misses 131system.cpu.itb.accesses 0 # DTB accesses 132system.cpu.workload.num_syscalls 191 # Number of system calls 133system.cpu.numCycles 1051668684 # number of cpu cycles simulated 134system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 135system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 136system.cpu.committedInsts 272739283 # Number of instructions committed 137system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed 138system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses 139system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 140system.cpu.num_func_calls 12448615 # number of times a function call or return occured 141system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls 142system.cpu.num_int_insts 279584917 # number of integer instructions 143system.cpu.num_fp_insts 114216705 # number of float instructions 144system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read 145system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written 146system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 147system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 148system.cpu.num_mem_refs 177024356 # number of memory refs 149system.cpu.num_load_insts 94648757 # Number of load instructions 150system.cpu.num_store_insts 82375599 # Number of store instructions 151system.cpu.num_idle_cycles 0 # Number of idle cycles 152system.cpu.num_busy_cycles 1051668684 # Number of busy cycles 153system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 154system.cpu.idle_fraction 0 # Percentage of idle cycles 155system.cpu.Branches 30563501 # Number of branches fetched	12sim_insts 272739283 # Number of instructions simulated 13sim_ops 348687122 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) 32system.membus.throughput 831532 # Throughput (bytes/s) 33system.membus.trans_dist::ReadReq 3976 # Transaction distribution 34system.membus.trans_dist::ReadResp 3976 # Transaction distribution 35system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 36system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 437248 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 43system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 45system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.inst_hits 0 # ITB inst hits 70system.cpu.dtb.inst_misses 0 # ITB inst misses 71system.cpu.dtb.read_hits 0 # DTB read hits 72system.cpu.dtb.read_misses 0 # DTB read misses 73system.cpu.dtb.write_hits 0 # DTB write hits 74system.cpu.dtb.write_misses 0 # DTB write misses 75system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 76system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 77system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 78system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 79system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 80system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 81system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 82system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 83system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 84system.cpu.dtb.read_accesses 0 # DTB read accesses 85system.cpu.dtb.write_accesses 0 # DTB write accesses 86system.cpu.dtb.inst_accesses 0 # ITB inst accesses 87system.cpu.dtb.hits 0 # DTB hits 88system.cpu.dtb.misses 0 # DTB misses 89system.cpu.dtb.accesses 0 # DTB accesses 90system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 91system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 92system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 93system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 94system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 95system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 96system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 97system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 98system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 99system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 100system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 101system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 102system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 103system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 104system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 105system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 106system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 107system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 108system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 109system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 110system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 111system.cpu.itb.inst_hits 0 # ITB inst hits 112system.cpu.itb.inst_misses 0 # ITB inst misses 113system.cpu.itb.read_hits 0 # DTB read hits 114system.cpu.itb.read_misses 0 # DTB read misses 115system.cpu.itb.write_hits 0 # DTB write hits 116system.cpu.itb.write_misses 0 # DTB write misses 117system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.itb.read_accesses 0 # DTB read accesses 127system.cpu.itb.write_accesses 0 # DTB write accesses 128system.cpu.itb.inst_accesses 0 # ITB inst accesses 129system.cpu.itb.hits 0 # DTB hits 130system.cpu.itb.misses 0 # DTB misses 131system.cpu.itb.accesses 0 # DTB accesses 132system.cpu.workload.num_syscalls 191 # Number of system calls 133system.cpu.numCycles 1051668684 # number of cpu cycles simulated 134system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 135system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 136system.cpu.committedInsts 272739283 # Number of instructions committed 137system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed 138system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses 139system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 140system.cpu.num_func_calls 12448615 # number of times a function call or return occured 141system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls 142system.cpu.num_int_insts 279584917 # number of integer instructions 143system.cpu.num_fp_insts 114216705 # number of float instructions 144system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read 145system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written 146system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 147system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 148system.cpu.num_mem_refs 177024356 # number of memory refs 149system.cpu.num_load_insts 94648757 # Number of load instructions 150system.cpu.num_store_insts 82375599 # Number of store instructions 151system.cpu.num_idle_cycles 0 # Number of idle cycles 152system.cpu.num_busy_cycles 1051668684 # Number of busy cycles 153system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 154system.cpu.idle_fraction 0 # Percentage of idle cycles 155system.cpu.Branches 30563501 # Number of branches fetched
	156system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 157system.cpu.op_class::IntAlu 116649413 33.42% 33.42% # Class of executed instruction 158system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction 159system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction 160system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction 161system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction 162system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction 163system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction 164system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction 165system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction 166system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction 167system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction 168system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction 169system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction 170system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction 171system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction 172system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction 173system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction 174system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction 175system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction 176system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction 177system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction 178system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction 179system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction 180system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction 181system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction 182system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction 183system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction 184system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction 185system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction 186system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction 187system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction 188system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 189system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 190system.cpu.op_class::total 349065592 # Class of executed instruction
156system.cpu.icache.tags.replacements 13796 # number of replacements 157system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use 158system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. 159system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 160system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. 161system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 162system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor 163system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy 164system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy 165system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 166system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 167system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 168system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 169system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 170system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id 171system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id 172system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses 173system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses 174system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits 175system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits 176system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits 177system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits 178system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits 179system.cpu.icache.overall_hits::total 348644747 # number of overall hits 180system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 181system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 182system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 183system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 184system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 185system.cpu.icache.overall_misses::total 15603 # number of overall misses 186system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles 187system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles 188system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles 189system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles 190system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles 191system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles 192system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) 193system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) 194system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses 195system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses 196system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses 197system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses 198system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 199system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 200system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 201system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 202system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 203system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 204system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency 205system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency 206system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency 207system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency 208system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency 209system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency 210system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 211system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 212system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 213system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 214system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 215system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 216system.cpu.icache.fast_writes 0 # number of fast writes performed 217system.cpu.icache.cache_copies 0 # number of cache copies performed 218system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 219system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 220system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 221system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 222system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 223system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses 224system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles 225system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles 226system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles 227system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles 228system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles 229system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles 230system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 231system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 232system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 233system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 234system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 235system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 236system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency 237system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency 238system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency 239system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency 240system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency 241system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency 242system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 243system.cpu.l2cache.tags.replacements 0 # number of replacements 244system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use 245system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. 246system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 247system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. 248system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 249system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor 250system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor 251system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor 252system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy 253system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy 254system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy 255system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy 256system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id 257system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 258system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 259system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 260system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id 261system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id 262system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id 263system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses 264system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses 265system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits 266system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits 267system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits 268system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits 269system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits 270system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 271system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 272system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits 273system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits 274system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits 275system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits 276system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits 277system.cpu.l2cache.overall_hits::total 13249 # number of overall hits 278system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses 279system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses 280system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses 281system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 282system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 283system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses 284system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses 285system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 286system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses 287system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses 288system.cpu.l2cache.overall_misses::total 6832 # number of overall misses 289system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles 290system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles 291system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles 292system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles 293system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles 294system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles 295system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles 296system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles 297system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles 298system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles 299system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles 300system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) 301system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) 302system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) 303system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) 304system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) 305system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 306system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 307system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses 308system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses 309system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses 310system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses 311system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses 312system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses 313system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses 314system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses 315system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses 316system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 317system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 318system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses 319system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses 320system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 321system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses 322system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses 323system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses 324system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 325system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 326system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 327system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 328system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 329system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 330system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 331system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 332system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 333system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 334system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 335system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 336system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 337system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 338system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 339system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 340system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 341system.cpu.l2cache.fast_writes 0 # number of fast writes performed 342system.cpu.l2cache.cache_copies 0 # number of cache copies performed 343system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses 344system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses 345system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses 346system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 347system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 348system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses 349system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses 350system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 351system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses 352system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses 353system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses 354system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles 355system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles 356system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles 357system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles 358system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles 359system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles 360system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles 361system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles 362system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles 363system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles 364system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles 365system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses 366system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses 367system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses 368system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 369system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 370system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses 371system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses 372system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 373system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses 374system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses 375system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses 376system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 377system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 378system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 379system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 380system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 381system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 382system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 383system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 384system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 385system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 386system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 387system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 388system.cpu.dcache.tags.replacements 1332 # number of replacements 389system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use 390system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. 391system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 392system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. 393system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 394system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor 395system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy 396system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy 397system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 398system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 399system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 400system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 403system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 404system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses 405system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses 406system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits 407system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits 408system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 409system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 410system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 411system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 412system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 413system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 414system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits 415system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits 416system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits 417system.cpu.dcache.overall_hits::total 176619809 # number of overall hits 418system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses 419system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses 420system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 421system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 422system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses 423system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses 424system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses 425system.cpu.dcache.overall_misses::total 4478 # number of overall misses 426system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles 427system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles 428system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles 429system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles 430system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles 431system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles 432system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles 433system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles 434system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) 435system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) 436system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 437system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 438system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 439system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 440system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 441system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 442system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses 443system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses 444system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses 445system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses 446system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 447system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 449system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 450system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses 451system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses 452system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses 453system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses 454system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency 455system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency 456system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency 457system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency 458system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency 459system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency 460system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency 461system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency 462system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 463system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 464system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 465system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 466system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 467system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 468system.cpu.dcache.fast_writes 0 # number of fast writes performed 469system.cpu.dcache.cache_copies 0 # number of cache copies performed 470system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 471system.cpu.dcache.writebacks::total 998 # number of writebacks 472system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses 473system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses 474system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 475system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 476system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses 477system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses 478system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 479system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 480system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles 481system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles 482system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles 483system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles 484system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles 485system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles 486system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles 487system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles 488system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses 489system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses 490system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 491system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 492system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses 493system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses 494system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses 495system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses 496system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency 497system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency 498system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency 499system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency 500system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency 501system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency 502system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency 503system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency 504system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 505system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s) 506system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution 507system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 508system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution 509system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 510system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 511system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) 512system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) 513system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) 514system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) 515system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) 516system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) 517system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes) 518system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 519system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) 520system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 521system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 522system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 523system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 524system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 525 526---------- End Simulation Statistics ----------	191system.cpu.icache.tags.replacements 13796 # number of replacements 192system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use 193system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. 194system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 195system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. 196system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 197system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor 198system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy 199system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy 200system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 201system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 202system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 203system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 204system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 205system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id 206system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id 207system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses 208system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses 209system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits 210system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits 211system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits 212system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits 213system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits 214system.cpu.icache.overall_hits::total 348644747 # number of overall hits 215system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 216system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 217system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 218system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 219system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 220system.cpu.icache.overall_misses::total 15603 # number of overall misses 221system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles 222system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles 223system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles 224system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles 225system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles 226system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles 227system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) 228system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) 229system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses 230system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses 231system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses 232system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses 233system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 234system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 235system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 236system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 237system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 238system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 239system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency 240system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency 241system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency 242system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency 243system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency 244system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency 245system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 246system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 248system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 249system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 250system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 251system.cpu.icache.fast_writes 0 # number of fast writes performed 252system.cpu.icache.cache_copies 0 # number of cache copies performed 253system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 254system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 255system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 256system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 257system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 258system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses 259system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles 260system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles 261system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles 262system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles 263system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles 264system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles 265system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 266system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 267system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 268system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 269system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 270system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 271system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency 272system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency 273system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency 274system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency 275system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency 276system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency 277system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 278system.cpu.l2cache.tags.replacements 0 # number of replacements 279system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use 280system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. 281system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 282system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. 283system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 284system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor 285system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor 286system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor 287system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy 288system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy 289system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy 290system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy 291system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id 292system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 293system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 294system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 295system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id 296system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id 297system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id 298system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses 299system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses 300system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits 301system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits 302system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits 303system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits 304system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits 305system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 306system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 307system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits 308system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits 309system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits 310system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits 311system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits 312system.cpu.l2cache.overall_hits::total 13249 # number of overall hits 313system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses 314system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses 315system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses 316system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 317system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 318system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses 319system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses 320system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 321system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses 322system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses 323system.cpu.l2cache.overall_misses::total 6832 # number of overall misses 324system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles 325system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles 326system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles 327system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles 328system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles 329system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles 330system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles 331system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles 332system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles 333system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles 334system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles 335system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) 336system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) 337system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) 338system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) 339system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) 340system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 341system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 342system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses 343system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses 344system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses 345system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses 346system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses 347system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses 348system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses 349system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses 350system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses 351system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 352system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 353system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses 354system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses 355system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 356system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses 357system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses 358system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses 359system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 360system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 361system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 362system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 363system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 364system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 365system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 366system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 367system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 368system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 370system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 371system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 374system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 375system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 376system.cpu.l2cache.fast_writes 0 # number of fast writes performed 377system.cpu.l2cache.cache_copies 0 # number of cache copies performed 378system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses 379system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses 380system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses 381system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 382system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 383system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses 384system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses 385system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 386system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses 387system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses 388system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses 389system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles 390system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles 391system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles 392system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles 393system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles 394system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles 395system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles 397system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles 398system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles 399system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles 400system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses 401system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses 402system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses 403system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 404system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 405system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses 406system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses 407system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 408system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses 409system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses 410system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses 411system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 412system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 413system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 414system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 415system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 416system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 417system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 419system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 420system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 422system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 423system.cpu.dcache.tags.replacements 1332 # number of replacements 424system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use 425system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. 426system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 427system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. 428system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 429system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor 430system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy 431system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy 432system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 433system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 434system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 435system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id 436system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 437system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 438system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 439system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses 440system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses 441system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits 442system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits 443system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 444system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 445system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 446system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 447system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 448system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 449system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits 450system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits 451system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits 452system.cpu.dcache.overall_hits::total 176619809 # number of overall hits 453system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses 454system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses 455system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 456system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 457system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses 458system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses 459system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses 460system.cpu.dcache.overall_misses::total 4478 # number of overall misses 461system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles 462system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles 463system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles 464system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles 465system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles 466system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles 467system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles 468system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles 469system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) 470system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) 471system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 472system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 473system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 476system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 477system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses 478system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses 479system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses 480system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses 481system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 482system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 483system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 484system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 485system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses 486system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses 487system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses 488system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses 489system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency 490system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency 491system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency 493system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency 494system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency 495system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency 496system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency 497system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 498system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 499system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 500system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 501system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 502system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 503system.cpu.dcache.fast_writes 0 # number of fast writes performed 504system.cpu.dcache.cache_copies 0 # number of cache copies performed 505system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 506system.cpu.dcache.writebacks::total 998 # number of writebacks 507system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses 508system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses 509system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 510system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 511system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses 512system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses 513system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 514system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 515system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles 516system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles 517system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles 518system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles 519system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles 520system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles 521system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles 522system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles 523system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses 524system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses 525system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 526system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 527system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses 528system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses 529system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses 530system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses 531system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency 532system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency 533system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency 534system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency 535system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency 536system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency 537system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency 538system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency 539system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 540system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s) 541system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution 542system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 543system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution 544system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 545system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 546system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) 547system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) 548system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) 549system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) 550system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) 551system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) 552system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes) 553system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 554system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) 555system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 556system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 557system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 558system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 559system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 560 561---------- End Simulation Statistics ----------