25a26
> mmap_using_noreserve=false
86a88
> demand_mshr_reserve=1
90c92
< is_top_level=true
---
> is_read_only=false
101d102
< two_queue=false
120a122
> sys=system
138d139
< port=system.cpu.toL2Bus.slave[5]
162a164
> demand_mshr_reserve=1
166c168
< is_top_level=true
---
> is_read_only=true
177d178
< two_queue=false
222a224
> pmu=Null
229a232
> sys=system
247d249
< port=system.cpu.toL2Bus.slave[4]
271a274
> demand_mshr_reserve=1
275c278
< is_top_level=false
---
> is_read_only=false
286d288
< two_queue=false
305c307,309
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
306a311
> snoop_response_latency=1
311c316
< slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
320a326
> drivers=
328a335
> kvmInSE=false
358c365,367
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
359a369
> snoop_response_latency=4
362c372
< width=8
---
> width=16