1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
--- 147 unchanged lines hidden (view full) ---
156tgts_per_mshr=5
157trace_addr=0
158two_queue=false
159write_buffers=8
160cpu_side=system.cpu.toL2Bus.master[0]
161mem_side=system.membus.slave[1]
162
163[system.cpu.toL2Bus]
164type=Bus
165block_size=64
166bus_id=0
167clock=1000
168header_cycles=1
169use_default_range=false
170width=64
171master=system.cpu.l2cache.cpu_side
172slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
173
174[system.cpu.tracer]
--- 14 unchanged lines hidden (view full) ---
189output=cout
190pid=100
191ppid=99
192simpoint=0
193system=system
194uid=100
195
196[system.membus]
197type=Bus
198block_size=64
199bus_id=0
200clock=1000
201header_cycles=1
202use_default_range=false
203width=64
204master=system.physmem.port[0]
205slave=system.system_port system.cpu.l2cache.mem_side
206
207[system.physmem]
208type=SimpleMemory
209conf_table_reported=false
210file=
211in_addr_map=true
212latency=30000
213latency_var=0
214null=false
215range=0:134217727
216zero=false
217port=system.membus.master[0]
218
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
--- 147 unchanged lines hidden (view full) ---
156tgts_per_mshr=5
157trace_addr=0
158two_queue=false
159write_buffers=8
160cpu_side=system.cpu.toL2Bus.master[0]
161mem_side=system.membus.slave[1]
162
163[system.cpu.toL2Bus]
164type=Bus
165block_size=64
166bus_id=0
167clock=1000
168header_cycles=1
169use_default_range=false
170width=64
171master=system.cpu.l2cache.cpu_side
172slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
173
174[system.cpu.tracer]
--- 14 unchanged lines hidden (view full) ---
189output=cout
190pid=100
191ppid=99
192simpoint=0
193system=system
194uid=100
195
196[system.membus]
197type=Bus
198block_size=64
199bus_id=0
200clock=1000
201header_cycles=1
202use_default_range=false
203width=64
204master=system.physmem.port[0]
205slave=system.system_port system.cpu.l2cache.mem_side
206
207[system.physmem]
208type=SimpleMemory
209conf_table_reported=false
210file=
211in_addr_map=true
212latency=30000
213latency_var=0
214null=false
215range=0:134217727
216zero=false
217port=system.membus.master[0]
218