| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.068258 # Number of seconds simulated 4sim_ticks 68258363000 # Number of ticks simulated 5final_tick 68258363000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.068340 # Number of seconds simulated 4sim_ticks 68340072000 # Number of ticks simulated 5final_tick 68340072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 73419 # Simulator instruction rate (inst/s) 8host_op_rate 93863 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18354583 # Simulator tick rate (ticks/s) 10host_mem_usage 296524 # Number of bytes of host memory used 11host_seconds 3718.87 # Real time elapsed on the host | 7host_inst_rate 97727 # Simulator instruction rate (inst/s) 8host_op_rate 124939 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24460648 # Simulator tick rate (ticks/s) 10host_mem_usage 254748 # Number of bytes of host memory used 11host_seconds 2793.88 # Real time elapsed on the host |
| 12sim_insts 273036725 # Number of instructions simulated 13sim_ops 349064449 # Number of ops (including micro ops) simulated | 12sim_insts 273036725 # Number of instructions simulated 13sim_ops 349064449 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 272192 # Number of bytes read from this memory 16system.physmem.bytes_read::total 465984 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4253 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 7281 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2839095 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 3987673 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 6826768 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2839095 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2839095 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2839095 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 3987673 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 6826768 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 7281 # Total number of read requests seen | 14system.physmem.bytes_read::cpu.inst 193856 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 272320 # Number of bytes read from this memory 16system.physmem.bytes_read::total 466176 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 193856 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 193856 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3029 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4255 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 7284 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2836637 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 3984778 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 6821415 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2836637 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2836637 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2836637 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 3984778 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 6821415 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 7284 # Total number of read requests seen |
| 31system.physmem.writeReqs 0 # Total number of write requests seen | 31system.physmem.writeReqs 0 # Total number of write requests seen |
| 32system.physmem.cpureqs 7284 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 465984 # Total number of bytes read from memory | 32system.physmem.cpureqs 7289 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 466176 # Total number of bytes read from memory |
| 34system.physmem.bytesWritten 0 # Total number of bytes written to memory | 34system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 35system.physmem.bytesConsumedRd 465984 # bytesRead derated as per pkt->getSize() | 35system.physmem.bytesConsumedRd 466176 # bytesRead derated as per pkt->getSize() |
| 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q | 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q |
| 38system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 412 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 408 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 483 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 476 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 509 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 487 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 544 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 590 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 400 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 432 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 455 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 417 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 381 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 421 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 450 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 416 # Track reads on a per bank basis | 38system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 803 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 607 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 525 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 354 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 161 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 210 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 325 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 414 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 530 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 686 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 611 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 68258164000 # Total gap between requests | 73system.physmem.totGap 68339875000 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 80system.physmem.readPktSize::6 7281 # Categorize read packet sizes | 80system.physmem.readPktSize::6 7284 # Categorize read packet sizes |
| 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes | 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 88system.physmem.rdQLenPdf::0 4267 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 2163 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 187 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see | 88system.physmem.rdQLenPdf::0 4420 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 2077 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 561 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see |
| 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 42 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 42 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 152system.physmem.totQLat 45271500 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 191126500 # Sum of mem lat for all requests 154system.physmem.totBusLat 36405000 # Total cycles spent in databus access 155system.physmem.totBankLat 109450000 # Total cycles spent in bank access 156system.physmem.avgQLat 6217.76 # Average queueing delay per request 157system.physmem.avgBankLat 15032.28 # Average bank access latency per request | 152system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation 153system.physmem.bytesPerActivate::mean 639.642957 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::gmean 236.501213 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::stdev 1328.325684 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::64-65 231 32.22% 32.22% # Bytes accessed per row activation 157system.physmem.bytesPerActivate::128-129 96 13.39% 45.61% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::192-193 63 8.79% 54.39% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::256-257 56 7.81% 62.20% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::320-321 30 4.18% 66.39% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::384-385 30 4.18% 70.57% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::448-449 16 2.23% 72.80% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::512-513 21 2.93% 75.73% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::576-577 13 1.81% 77.55% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::640-641 17 2.37% 79.92% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::704-705 8 1.12% 81.03% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::768-769 12 1.67% 82.71% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::832-833 3 0.42% 83.12% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::896-897 9 1.26% 84.38% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::960-961 5 0.70% 85.08% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::1024-1025 7 0.98% 86.05% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1088-1089 5 0.70% 86.75% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1152-1153 5 0.70% 87.45% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1216-1217 4 0.56% 88.01% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.56% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1344-1345 2 0.28% 88.84% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1408-1409 4 0.56% 89.40% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1472-1473 3 0.42% 89.82% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1600-1601 4 0.56% 90.38% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1664-1665 4 0.56% 90.93% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.21% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.49% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.77% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1920-1921 2 0.28% 92.05% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.33% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.61% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.03% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.44% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::2240-2241 1 0.14% 93.58% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::2304-2305 2 0.28% 93.86% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.14% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.28% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.70% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.98% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.09% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.23% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.37% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.51% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.65% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.79% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.93% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.07% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::5952-5953 1 0.14% 97.77% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::6080-6081 1 0.14% 97.91% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation 218system.physmem.totQLat 39275000 # Total cycles spent in queuing delays 219system.physmem.totMemAccLat 171092500 # Sum of mem lat for all requests 220system.physmem.totBusLat 36420000 # Total cycles spent in databus access 221system.physmem.totBankLat 95397500 # Total cycles spent in bank access 222system.physmem.avgQLat 5391.95 # Average queueing delay per request 223system.physmem.avgBankLat 13096.86 # Average bank access latency per request |
| 158system.physmem.avgBusLat 5000.00 # Average bus latency per request | 224system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 159system.physmem.avgMemAccLat 26250.03 # Average memory access latency 160system.physmem.avgRdBW 6.83 # Average achieved read bandwidth in MB/s | 225system.physmem.avgMemAccLat 23488.81 # Average memory access latency 226system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s |
| 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 227system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 162system.physmem.avgConsumedRdBW 6.83 # Average consumed read bandwidth in MB/s | 228system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s |
| 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 0.05 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.00 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time | 229system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 230system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 231system.physmem.busUtil 0.05 # Data bus utilization in percentage 232system.physmem.avgRdQLen 0.00 # Average read queue length over time 233system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 168system.physmem.readRowHits 6071 # Number of row buffer hits during reads | 234system.physmem.readRowHits 6567 # Number of row buffer hits during reads |
| 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 235system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 170system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads | 236system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads |
| 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 237system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 172system.physmem.avgGap 9374833.68 # Average gap between requests 173system.cpu.branchPred.lookups 35375534 # Number of BP lookups 174system.cpu.branchPred.condPredicted 21203624 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 1636565 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 18693932 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 16765511 # Number of BTB hits | 238system.physmem.avgGap 9382190.42 # Average gap between requests 239system.membus.throughput 6821415 # Throughput (bytes/s) 240system.membus.trans_dist::ReadReq 4461 # Transaction distribution 241system.membus.trans_dist::ReadResp 4461 # Transaction distribution 242system.membus.trans_dist::UpgradeReq 5 # Transaction distribution 243system.membus.trans_dist::UpgradeResp 5 # Transaction distribution 244system.membus.trans_dist::ReadExReq 2823 # Transaction distribution 245system.membus.trans_dist::ReadExResp 2823 # Transaction distribution 246system.membus.pkt_count_system.cpu.l2cache.mem_side 14578 # Packet count per connected master and slave (bytes) 247system.membus.pkt_count 14578 # Packet count per connected master and slave (bytes) 248system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466176 # Cumulative packet size per connected master and slave (bytes) 249system.membus.tot_pkt_size 466176 # Cumulative packet size per connected master and slave (bytes) 250system.membus.data_through_bus 466176 # Total data (bytes) 251system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 252system.membus.reqLayer0.occupancy 8863500 # Layer occupancy (ticks) 253system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 254system.membus.respLayer1.occupancy 67994996 # Layer occupancy (ticks) 255system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 256system.cpu.branchPred.lookups 35386289 # Number of BP lookups 257system.cpu.branchPred.condPredicted 21204879 # Number of conditional branches predicted 258system.cpu.branchPred.condIncorrect 1638532 # Number of conditional branches incorrect 259system.cpu.branchPred.BTBLookups 19153921 # Number of BTB lookups 260system.cpu.branchPred.BTBHits 16759106 # Number of BTB hits |
| 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 261system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 179system.cpu.branchPred.BTBHitPct 89.684241 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 6786649 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 8328 # Number of incorrect RAS predictions. | 262system.cpu.branchPred.BTBHitPct 87.496999 # BTB Hit Percentage 263system.cpu.branchPred.usedRAS 6781793 # Number of times the RAS was used to get a target. 264system.cpu.branchPred.RASInCorrect 8488 # Number of incorrect RAS predictions. |
| 182system.cpu.dtb.inst_hits 0 # ITB inst hits 183system.cpu.dtb.inst_misses 0 # ITB inst misses 184system.cpu.dtb.read_hits 0 # DTB read hits 185system.cpu.dtb.read_misses 0 # DTB read misses 186system.cpu.dtb.write_hits 0 # DTB write hits 187system.cpu.dtb.write_misses 0 # DTB write misses 188system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 189system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 217system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 218system.cpu.itb.read_accesses 0 # DTB read accesses 219system.cpu.itb.write_accesses 0 # DTB write accesses 220system.cpu.itb.inst_accesses 0 # ITB inst accesses 221system.cpu.itb.hits 0 # DTB hits 222system.cpu.itb.misses 0 # DTB misses 223system.cpu.itb.accesses 0 # DTB accesses 224system.cpu.workload.num_syscalls 191 # Number of system calls | 265system.cpu.dtb.inst_hits 0 # ITB inst hits 266system.cpu.dtb.inst_misses 0 # ITB inst misses 267system.cpu.dtb.read_hits 0 # DTB read hits 268system.cpu.dtb.read_misses 0 # DTB read misses 269system.cpu.dtb.write_hits 0 # DTB write hits 270system.cpu.dtb.write_misses 0 # DTB write misses 271system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 272system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 300system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 301system.cpu.itb.read_accesses 0 # DTB read accesses 302system.cpu.itb.write_accesses 0 # DTB write accesses 303system.cpu.itb.inst_accesses 0 # ITB inst accesses 304system.cpu.itb.hits 0 # DTB hits 305system.cpu.itb.misses 0 # DTB misses 306system.cpu.itb.accesses 0 # DTB accesses 307system.cpu.workload.num_syscalls 191 # Number of system calls |
| 225system.cpu.numCycles 136516727 # number of cpu cycles simulated | 308system.cpu.numCycles 136680145 # number of cpu cycles simulated |
| 226system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 227system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 309system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 310system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 228system.cpu.fetch.icacheStallCycles 38896982 # Number of cycles fetch is stalled on an Icache miss 229system.cpu.fetch.Insts 317376259 # Number of instructions fetch has processed 230system.cpu.fetch.Branches 35375534 # Number of branches that fetch encountered 231system.cpu.fetch.predictedBranches 23552160 # Number of branches that fetch has predicted taken 232system.cpu.fetch.Cycles 70779245 # Number of cycles fetch has run and was not squashing or blocked 233system.cpu.fetch.SquashCycles 6771648 # Number of cycles fetch has spent squashing 234system.cpu.fetch.BlockedCycles 21491054 # Number of cycles fetch has spent blocked 235system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 236system.cpu.fetch.PendingTrapStallCycles 1891 # Number of stall cycles due to pending traps 237system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR 238system.cpu.fetch.CacheLines 37519444 # Number of cache lines fetched 239system.cpu.fetch.IcacheSquashes 509386 # Number of outstanding Icache misses that were squashed 240system.cpu.fetch.rateDist::samples 136293047 # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::mean 2.985311 # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::stdev 3.454516 # Number of instructions fetched each cycle (Total) | 311system.cpu.fetch.icacheStallCycles 38911514 # Number of cycles fetch is stalled on an Icache miss 312system.cpu.fetch.Insts 317585001 # Number of instructions fetch has processed 313system.cpu.fetch.Branches 35386289 # Number of branches that fetch encountered 314system.cpu.fetch.predictedBranches 23540899 # Number of branches that fetch has predicted taken 315system.cpu.fetch.Cycles 70801219 # Number of cycles fetch has run and was not squashing or blocked 316system.cpu.fetch.SquashCycles 6795871 # Number of cycles fetch has spent squashing 317system.cpu.fetch.BlockedCycles 21500027 # Number of cycles fetch has spent blocked 318system.cpu.fetch.MiscStallCycles 100 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 319system.cpu.fetch.PendingTrapStallCycles 1484 # Number of stall cycles due to pending traps 320system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR 321system.cpu.fetch.CacheLines 37522622 # Number of cache lines fetched 322system.cpu.fetch.IcacheSquashes 503492 # Number of outstanding Icache misses that were squashed 323system.cpu.fetch.rateDist::samples 136360129 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::mean 2.984944 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::stdev 3.454705 # Number of instructions fetched each cycle (Total) |
| 243system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 326system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 244system.cpu.fetch.rateDist::0 66138904 48.53% 48.53% # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::1 6767660 4.97% 53.49% # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::2 5699163 4.18% 57.67% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::3 6081886 4.46% 62.14% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::4 4905828 3.60% 65.74% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::5 4088301 3.00% 68.74% # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::6 3176914 2.33% 71.07% # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::7 4135950 3.03% 74.10% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::8 35298441 25.90% 100.00% # Number of instructions fetched each cycle (Total) | 327system.cpu.fetch.rateDist::0 66188924 48.54% 48.54% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::1 6771554 4.97% 53.51% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::2 5692762 4.17% 57.68% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::3 6083969 4.46% 62.14% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::4 4907326 3.60% 65.74% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::5 4077145 2.99% 68.73% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::6 3184432 2.34% 71.07% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::7 4135342 3.03% 74.10% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::8 35318675 25.90% 100.00% # Number of instructions fetched each cycle (Total) |
| 253system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 336system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 256system.cpu.fetch.rateDist::total 136293047 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.branchRate 0.259130 # Number of branch fetches per cycle 258system.cpu.fetch.rate 2.324816 # Number of inst fetches per cycle 259system.cpu.decode.IdleCycles 45396979 # Number of cycles decode is idle 260system.cpu.decode.BlockedCycles 16650013 # Number of cycles decode is blocked 261system.cpu.decode.RunCycles 66644263 # Number of cycles decode is running 262system.cpu.decode.UnblockCycles 2546649 # Number of cycles decode is unblocking 263system.cpu.decode.SquashCycles 5055143 # Number of cycles decode is squashing 264system.cpu.decode.BranchResolved 7329146 # Number of times decode resolved a branch 265system.cpu.decode.BranchMispred 69002 # Number of times decode detected a branch misprediction 266system.cpu.decode.DecodedInsts 400901285 # Number of instructions handled by decode 267system.cpu.decode.SquashedInsts 213083 # Number of squashed instructions handled by decode 268system.cpu.rename.SquashCycles 5055143 # Number of cycles rename is squashing 269system.cpu.rename.IdleCycles 50932623 # Number of cycles rename is idle 270system.cpu.rename.BlockCycles 1928706 # Number of cycles rename is blocking 271system.cpu.rename.serializeStallCycles 309700 # count of cycles rename stalled for serializing inst 272system.cpu.rename.RunCycles 63595700 # Number of cycles rename is running 273system.cpu.rename.UnblockCycles 14471175 # Number of cycles rename is unblocking 274system.cpu.rename.RenamedInsts 393334802 # Number of instructions processed by rename 275system.cpu.rename.ROBFullEvents 54 # Number of times rename has blocked due to ROB full 276system.cpu.rename.IQFullEvents 1658050 # Number of times rename has blocked due to IQ full 277system.cpu.rename.LSQFullEvents 10199893 # Number of times rename has blocked due to LSQ full 278system.cpu.rename.FullRegisterEvents 1072 # Number of times there has been no free registers 279system.cpu.rename.RenamedOperands 431829381 # Number of destination operands rename has renamed 280system.cpu.rename.RenameLookups 2328856465 # Number of register rename lookups that rename has made 281system.cpu.rename.int_rename_lookups 1256465206 # Number of integer rename lookups 282system.cpu.rename.fp_rename_lookups 1072391259 # Number of floating rename lookups | 339system.cpu.fetch.rateDist::total 136360129 # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.branchRate 0.258899 # Number of branch fetches per cycle 341system.cpu.fetch.rate 2.323564 # Number of inst fetches per cycle 342system.cpu.decode.IdleCycles 45414780 # Number of cycles decode is idle 343system.cpu.decode.BlockedCycles 16659439 # Number of cycles decode is blocked 344system.cpu.decode.RunCycles 66663560 # Number of cycles decode is running 345system.cpu.decode.UnblockCycles 2545187 # Number of cycles decode is unblocking 346system.cpu.decode.SquashCycles 5077163 # Number of cycles decode is squashing 347system.cpu.decode.BranchResolved 7331349 # Number of times decode resolved a branch 348system.cpu.decode.BranchMispred 68935 # Number of times decode detected a branch misprediction 349system.cpu.decode.DecodedInsts 401047467 # Number of instructions handled by decode 350system.cpu.decode.SquashedInsts 212517 # Number of squashed instructions handled by decode 351system.cpu.rename.SquashCycles 5077163 # Number of cycles rename is squashing 352system.cpu.rename.IdleCycles 50947779 # Number of cycles rename is idle 353system.cpu.rename.BlockCycles 1931381 # Number of cycles rename is blocking 354system.cpu.rename.serializeStallCycles 327570 # count of cycles rename stalled for serializing inst 355system.cpu.rename.RunCycles 63615860 # Number of cycles rename is running 356system.cpu.rename.UnblockCycles 14460376 # Number of cycles rename is unblocking 357system.cpu.rename.RenamedInsts 393522571 # Number of instructions processed by rename 358system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full 359system.cpu.rename.IQFullEvents 1660698 # Number of times rename has blocked due to IQ full 360system.cpu.rename.LSQFullEvents 10177766 # Number of times rename has blocked due to LSQ full 361system.cpu.rename.FullRegisterEvents 1066 # Number of times there has been no free registers 362system.cpu.rename.RenamedOperands 432139045 # Number of destination operands rename has renamed 363system.cpu.rename.RenameLookups 2330040462 # Number of register rename lookups that rename has made 364system.cpu.rename.int_rename_lookups 1257112117 # Number of integer rename lookups 365system.cpu.rename.fp_rename_lookups 1072928345 # Number of floating rename lookups |
| 283system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed | 366system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed |
| 284system.cpu.rename.UndoneMaps 47263188 # Number of HB maps that are undone due to squashing 285system.cpu.rename.serializingInsts 11836 # count of serializing insts renamed 286system.cpu.rename.tempSerializingInsts 11835 # count of temporary serializing insts renamed 287system.cpu.rename.skidInsts 36477776 # count of insts added to the skid buffer 288system.cpu.memDep0.insertedLoads 103434690 # Number of loads inserted to the mem dependence unit. 289system.cpu.memDep0.insertedStores 91236939 # Number of stores inserted to the mem dependence unit. 290system.cpu.memDep0.conflictingLoads 4267637 # Number of conflicting loads. 291system.cpu.memDep0.conflictingStores 5260584 # Number of conflicting stores. 292system.cpu.iq.iqInstsAdded 383959282 # Number of instructions added to the IQ (excludes non-spec) 293system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ 294system.cpu.iq.iqInstsIssued 373920129 # Number of instructions issued 295system.cpu.iq.iqSquashedInstsIssued 1206190 # Number of squashed instructions issued 296system.cpu.iq.iqSquashedInstsExamined 34165918 # Number of squashed instructions iterated over during squash; mainly for profiling 297system.cpu.iq.iqSquashedOperandsExamined 85628063 # Number of squashed operands that are examined and possibly removed from graph 298system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed 299system.cpu.iq.issued_per_cycle::samples 136293047 # Number of insts issued each cycle 300system.cpu.iq.issued_per_cycle::mean 2.743501 # Number of insts issued each cycle 301system.cpu.iq.issued_per_cycle::stdev 2.023111 # Number of insts issued each cycle | 367system.cpu.rename.UndoneMaps 47572852 # Number of HB maps that are undone due to squashing 368system.cpu.rename.serializingInsts 11802 # count of serializing insts renamed 369system.cpu.rename.tempSerializingInsts 11801 # count of temporary serializing insts renamed 370system.cpu.rename.skidInsts 36468583 # count of insts added to the skid buffer 371system.cpu.memDep0.insertedLoads 103474945 # Number of loads inserted to the mem dependence unit. 372system.cpu.memDep0.insertedStores 91276854 # Number of stores inserted to the mem dependence unit. 373system.cpu.memDep0.conflictingLoads 4259608 # Number of conflicting loads. 374system.cpu.memDep0.conflictingStores 5261316 # Number of conflicting stores. 375system.cpu.iq.iqInstsAdded 384098955 # Number of instructions added to the IQ (excludes non-spec) 376system.cpu.iq.iqNonSpecInstsAdded 22768 # Number of non-speculative instructions added to the IQ 377system.cpu.iq.iqInstsIssued 373971213 # Number of instructions issued 378system.cpu.iq.iqSquashedInstsIssued 1208914 # Number of squashed instructions issued 379system.cpu.iq.iqSquashedInstsExamined 34303040 # Number of squashed instructions iterated over during squash; mainly for profiling 380system.cpu.iq.iqSquashedOperandsExamined 86231470 # Number of squashed operands that are examined and possibly removed from graph 381system.cpu.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed 382system.cpu.iq.issued_per_cycle::samples 136360129 # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::mean 2.742526 # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::stdev 2.023578 # Number of insts issued each cycle |
| 302system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 385system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 303system.cpu.iq.issued_per_cycle::0 24835944 18.22% 18.22% # Number of insts issued each cycle 304system.cpu.iq.issued_per_cycle::1 19923821 14.62% 32.84% # Number of insts issued each cycle 305system.cpu.iq.issued_per_cycle::2 20538519 15.07% 47.91% # Number of insts issued each cycle 306system.cpu.iq.issued_per_cycle::3 18169219 13.33% 61.24% # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::4 24028277 17.63% 78.87% # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::5 15701712 11.52% 90.39% # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::6 8800214 6.46% 96.85% # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::7 3374067 2.48% 99.32% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::8 921274 0.68% 100.00% # Number of insts issued each cycle | 386system.cpu.iq.issued_per_cycle::0 24894566 18.26% 18.26% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::1 19912259 14.60% 32.86% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::2 20562905 15.08% 47.94% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::3 18156426 13.32% 61.25% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::4 24028186 17.62% 78.88% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::5 15708589 11.52% 90.40% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::6 8792760 6.45% 96.84% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::7 3383887 2.48% 99.32% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::8 920551 0.68% 100.00% # Number of insts issued each cycle |
| 312system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 395system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 315system.cpu.iq.issued_per_cycle::total 136293047 # Number of insts issued each cycle | 398system.cpu.iq.issued_per_cycle::total 136360129 # Number of insts issued each cycle |
| 316system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 399system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 317system.cpu.iq.fu_full::IntAlu 8902 0.05% 0.05% # attempts to use FU when none available 318system.cpu.iq.fu_full::IntMult 4689 0.03% 0.08% # attempts to use FU when none available | 400system.cpu.iq.fu_full::IntAlu 8941 0.05% 0.05% # attempts to use FU when none available 401system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available |
| 319system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available 320system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available 321system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available 322system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available 323system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available 324system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available 325system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available 326system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available 327system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available | 402system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available |
| 337system.cpu.iq.fu_full::SimdFloatAdd 46241 0.26% 0.34% # attempts to use FU when none available | 420system.cpu.iq.fu_full::SimdFloatAdd 46063 0.26% 0.34% # attempts to use FU when none available |
| 338system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available | 421system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available |
| 339system.cpu.iq.fu_full::SimdFloatCmp 7650 0.04% 0.38% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdFloatCvt 432 0.00% 0.38% # attempts to use FU when none available | 422system.cpu.iq.fu_full::SimdFloatCmp 7630 0.04% 0.38% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.38% # attempts to use FU when none available |
| 341system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available | 424system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available |
| 342system.cpu.iq.fu_full::SimdFloatMisc 190629 1.08% 1.46% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdFloatMult 3972 0.02% 1.48% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatMultAcc 241372 1.36% 2.84% # attempts to use FU when none available | 425system.cpu.iq.fu_full::SimdFloatMisc 190949 1.08% 1.46% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatMult 4204 0.02% 1.48% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatMultAcc 241086 1.36% 2.84% # attempts to use FU when none available |
| 345system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available | 428system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available |
| 346system.cpu.iq.fu_full::MemRead 9278872 52.34% 55.18% # attempts to use FU when none available 347system.cpu.iq.fu_full::MemWrite 7944742 44.82% 100.00% # attempts to use FU when none available | 429system.cpu.iq.fu_full::MemRead 9286535 52.36% 55.20% # attempts to use FU when none available 430system.cpu.iq.fu_full::MemWrite 7946359 44.80% 100.00% # attempts to use FU when none available |
| 348system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 349system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 350system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 431system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 432system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 433system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 351system.cpu.iq.FU_type_0::IntAlu 126315653 33.78% 33.78% # Type of FU issued 352system.cpu.iq.FU_type_0::IntMult 2175866 0.58% 34.36% # Type of FU issued 353system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.36% # Type of FU issued 354system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.36% # Type of FU issued 355system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.36% # Type of FU issued 356system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.36% # Type of FU issued 357system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.36% # Type of FU issued 358system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.36% # Type of FU issued 359system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.36% # Type of FU issued 360system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.36% # Type of FU issued 361system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.36% # Type of FU issued 362system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.36% # Type of FU issued 363system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.36% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.36% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.36% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.36% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.36% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.36% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.36% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.36% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdFloatAdd 6776888 1.81% 36.18% # Type of FU issued | 434system.cpu.iq.FU_type_0::IntAlu 126344065 33.78% 33.78% # Type of FU issued 435system.cpu.iq.FU_type_0::IntMult 2175771 0.58% 34.37% # Type of FU issued 436system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.37% # Type of FU issued 440system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.37% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.37% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.37% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.37% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.37% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.37% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.37% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.37% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.37% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.37% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatAdd 6778681 1.81% 36.18% # Type of FU issued |
| 372system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued | 455system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued |
| 373system.cpu.iq.FU_type_0::SimdFloatCmp 8468895 2.26% 38.44% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdFloatCvt 3427953 0.92% 39.36% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdFloatDiv 1595639 0.43% 39.78% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdFloatMisc 20851093 5.58% 45.36% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdFloatMult 7171347 1.92% 47.28% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdFloatMultAcc 7126740 1.91% 49.18% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.23% # Type of FU issued 380system.cpu.iq.FU_type_0::MemRead 101555976 27.16% 76.39% # Type of FU issued 381system.cpu.iq.FU_type_0::MemWrite 88278790 23.61% 100.00% # Type of FU issued | 456system.cpu.iq.FU_type_0::SimdFloatCmp 8473226 2.27% 38.44% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatCvt 3428816 0.92% 39.36% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatDiv 1595959 0.43% 39.79% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatMisc 20861053 5.58% 45.37% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatMult 7172627 1.92% 47.28% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127553 1.91% 49.19% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued 463system.cpu.iq.FU_type_0::MemRead 101561380 27.16% 76.39% # Type of FU issued 464system.cpu.iq.FU_type_0::MemWrite 88276793 23.61% 100.00% # Type of FU issued |
| 382system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 383system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 465system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 466system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 384system.cpu.iq.FU_type_0::total 373920129 # Type of FU issued 385system.cpu.iq.rate 2.739006 # Inst issue rate 386system.cpu.iq.fu_busy_cnt 17727503 # FU busy when requested 387system.cpu.iq.fu_busy_rate 0.047410 # FU busy rate (busy events/executed inst) 388system.cpu.iq.int_inst_queue_reads 653684952 # Number of integer instruction queue reads 389system.cpu.iq.int_inst_queue_writes 287885544 # Number of integer instruction queue writes 390system.cpu.iq.int_inst_queue_wakeup_accesses 249920404 # Number of integer instruction queue wakeup accesses 391system.cpu.iq.fp_inst_queue_reads 249382046 # Number of floating instruction queue reads 392system.cpu.iq.fp_inst_queue_writes 130276634 # Number of floating instruction queue writes 393system.cpu.iq.fp_inst_queue_wakeup_accesses 118031995 # Number of floating instruction queue wakeup accesses 394system.cpu.iq.int_alu_accesses 263048449 # Number of integer alu accesses 395system.cpu.iq.fp_alu_accesses 128599183 # Number of floating point alu accesses 396system.cpu.iew.lsq.thread0.forwLoads 11100195 # Number of loads that had data forwarded from stores | 467system.cpu.iq.FU_type_0::total 373971213 # Type of FU issued 468system.cpu.iq.rate 2.736105 # Inst issue rate 469system.cpu.iq.fu_busy_cnt 17736902 # FU busy when requested 470system.cpu.iq.fu_busy_rate 0.047429 # FU busy rate (busy events/executed inst) 471system.cpu.iq.int_inst_queue_reads 653872242 # Number of integer instruction queue reads 472system.cpu.iq.int_inst_queue_writes 288125780 # Number of integer instruction queue writes 473system.cpu.iq.int_inst_queue_wakeup_accesses 249960786 # Number of integer instruction queue wakeup accesses 474system.cpu.iq.fp_inst_queue_reads 249376129 # Number of floating instruction queue reads 475system.cpu.iq.fp_inst_queue_writes 130313231 # Number of floating instruction queue writes 476system.cpu.iq.fp_inst_queue_wakeup_accesses 118044740 # Number of floating instruction queue wakeup accesses 477system.cpu.iq.int_alu_accesses 263109864 # Number of integer alu accesses 478system.cpu.iq.fp_alu_accesses 128598251 # Number of floating point alu accesses 479system.cpu.iew.lsq.thread0.forwLoads 11095244 # Number of loads that had data forwarded from stores |
| 397system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 480system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 398system.cpu.iew.lsq.thread0.squashedLoads 8785942 # Number of loads squashed 399system.cpu.iew.lsq.thread0.ignoredResponses 109607 # Number of memory responses ignored because the instruction is squashed 400system.cpu.iew.lsq.thread0.memOrderViolation 14276 # Number of memory ordering violations 401system.cpu.iew.lsq.thread0.squashedStores 8861356 # Number of stores squashed | 481system.cpu.iew.lsq.thread0.squashedLoads 8826197 # Number of loads squashed 482system.cpu.iew.lsq.thread0.ignoredResponses 108953 # Number of memory responses ignored because the instruction is squashed 483system.cpu.iew.lsq.thread0.memOrderViolation 14410 # Number of memory ordering violations 484system.cpu.iew.lsq.thread0.squashedStores 8901271 # Number of stores squashed |
| 402system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 403system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 485system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 486system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 404system.cpu.iew.lsq.thread0.rescheduledLoads 182774 # Number of loads that were rescheduled 405system.cpu.iew.lsq.thread0.cacheBlocked 1441 # Number of times an access to memory failed due to the cache being blocked | 487system.cpu.iew.lsq.thread0.rescheduledLoads 178209 # Number of loads that were rescheduled 488system.cpu.iew.lsq.thread0.cacheBlocked 1806 # Number of times an access to memory failed due to the cache being blocked |
| 406system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 489system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 407system.cpu.iew.iewSquashCycles 5055143 # Number of cycles IEW is squashing 408system.cpu.iew.iewBlockCycles 284926 # Number of cycles IEW is blocking 409system.cpu.iew.iewUnblockCycles 36749 # Number of cycles IEW is unblocking 410system.cpu.iew.iewDispatchedInsts 383983637 # Number of instructions dispatched to IQ 411system.cpu.iew.iewDispSquashedInsts 873190 # Number of squashed instructions skipped by dispatch 412system.cpu.iew.iewDispLoadInsts 103434690 # Number of dispatched load instructions 413system.cpu.iew.iewDispStoreInsts 91236939 # Number of dispatched store instructions 414system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions 415system.cpu.iew.iewIQFullEvents 337 # Number of times the IQ has become full, causing a stall 416system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall 417system.cpu.iew.memOrderViolationEvents 14276 # Number of memory order violations 418system.cpu.iew.predictedTakenIncorrect 1271835 # Number of branches that were predicted taken incorrectly 419system.cpu.iew.predictedNotTakenIncorrect 367005 # Number of branches that were predicted not taken incorrectly 420system.cpu.iew.branchMispredicts 1638840 # Number of branch mispredicts detected at execute 421system.cpu.iew.iewExecutedInsts 369984044 # Number of executed instructions 422system.cpu.iew.iewExecLoadInsts 100253903 # Number of load instructions executed 423system.cpu.iew.iewExecSquashedInsts 3936085 # Number of squashed instructions skipped in execute | 490system.cpu.iew.iewSquashCycles 5077163 # Number of cycles IEW is squashing 491system.cpu.iew.iewBlockCycles 281172 # Number of cycles IEW is blocking 492system.cpu.iew.iewUnblockCycles 37033 # Number of cycles IEW is unblocking 493system.cpu.iew.iewDispatchedInsts 384123288 # Number of instructions dispatched to IQ 494system.cpu.iew.iewDispSquashedInsts 853132 # Number of squashed instructions skipped by dispatch 495system.cpu.iew.iewDispLoadInsts 103474945 # Number of dispatched load instructions 496system.cpu.iew.iewDispStoreInsts 91276854 # Number of dispatched store instructions 497system.cpu.iew.iewDispNonSpecInsts 11734 # Number of dispatched non-speculative instructions 498system.cpu.iew.iewIQFullEvents 343 # Number of times the IQ has become full, causing a stall 499system.cpu.iew.iewLSQFullEvents 352 # Number of times the LSQ has become full, causing a stall 500system.cpu.iew.memOrderViolationEvents 14410 # Number of memory order violations 501system.cpu.iew.predictedTakenIncorrect 1275078 # Number of branches that were predicted taken incorrectly 502system.cpu.iew.predictedNotTakenIncorrect 370888 # Number of branches that were predicted not taken incorrectly 503system.cpu.iew.branchMispredicts 1645966 # Number of branch mispredicts detected at execute 504system.cpu.iew.iewExecutedInsts 370028321 # Number of executed instructions 505system.cpu.iew.iewExecLoadInsts 100269572 # Number of load instructions executed 506system.cpu.iew.iewExecSquashedInsts 3942892 # Number of squashed instructions skipped in execute |
| 424system.cpu.iew.exec_swp 0 # number of swp insts executed | 507system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 425system.cpu.iew.exec_nop 1567 # number of nop insts executed 426system.cpu.iew.exec_refs 187478745 # number of memory reference insts executed 427system.cpu.iew.exec_branches 32002404 # Number of branches executed 428system.cpu.iew.exec_stores 87224842 # Number of stores executed 429system.cpu.iew.exec_rate 2.710174 # Inst execution rate 430system.cpu.iew.wb_sent 368608393 # cumulative count of insts sent to commit 431system.cpu.iew.wb_count 367952399 # cumulative count of insts written-back 432system.cpu.iew.wb_producers 182920147 # num instructions producing a value 433system.cpu.iew.wb_consumers 363541669 # num instructions consuming a value | 508system.cpu.iew.exec_nop 1565 # number of nop insts executed 509system.cpu.iew.exec_refs 187470029 # number of memory reference insts executed 510system.cpu.iew.exec_branches 32001457 # Number of branches executed 511system.cpu.iew.exec_stores 87200457 # Number of stores executed 512system.cpu.iew.exec_rate 2.707257 # Inst execution rate 513system.cpu.iew.wb_sent 368660932 # cumulative count of insts sent to commit 514system.cpu.iew.wb_count 368005526 # cumulative count of insts written-back 515system.cpu.iew.wb_producers 182984682 # num instructions producing a value 516system.cpu.iew.wb_consumers 363667286 # num instructions consuming a value |
| 434system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 517system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 435system.cpu.iew.wb_rate 2.695292 # insts written-back per cycle 436system.cpu.iew.wb_fanout 0.503161 # average fanout of values written-back | 518system.cpu.iew.wb_rate 2.692458 # insts written-back per cycle 519system.cpu.iew.wb_fanout 0.503165 # average fanout of values written-back |
| 437system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 520system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 438system.cpu.commit.commitSquashedInsts 34918645 # The number of squashed insts skipped by commit | 521system.cpu.commit.commitSquashedInsts 35058333 # The number of squashed insts skipped by commit |
| 439system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards | 522system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards |
| 440system.cpu.commit.branchMispredicts 1567905 # The number of times a branch was mispredicted 441system.cpu.commit.committed_per_cycle::samples 131237904 # Number of insts commited each cycle 442system.cpu.commit.committed_per_cycle::mean 2.659788 # Number of insts commited each cycle 443system.cpu.commit.committed_per_cycle::stdev 2.659697 # Number of insts commited each cycle | 523system.cpu.commit.branchMispredicts 1569963 # The number of times a branch was mispredicted 524system.cpu.commit.committed_per_cycle::samples 131282966 # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::mean 2.658875 # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::stdev 2.659705 # Number of insts commited each cycle |
| 444system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 527system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 445system.cpu.commit.committed_per_cycle::0 34480622 26.27% 26.27% # Number of insts commited each cycle 446system.cpu.commit.committed_per_cycle::1 28416799 21.65% 47.93% # Number of insts commited each cycle 447system.cpu.commit.committed_per_cycle::2 13301568 10.14% 58.06% # Number of insts commited each cycle 448system.cpu.commit.committed_per_cycle::3 11461353 8.73% 66.79% # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::4 13768973 10.49% 77.29% # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::5 7415781 5.65% 82.94% # Number of insts commited each cycle 451system.cpu.commit.committed_per_cycle::6 3872079 2.95% 85.89% # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::7 3892036 2.97% 88.85% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::8 14628693 11.15% 100.00% # Number of insts commited each cycle | 528system.cpu.commit.committed_per_cycle::0 34515611 26.29% 26.29% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::1 28430867 21.66% 47.95% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::2 13310132 10.14% 58.09% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::3 11454615 8.73% 66.81% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::4 13758236 10.48% 77.29% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::5 7411224 5.65% 82.94% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::6 3878786 2.95% 85.89% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::7 3899655 2.97% 88.86% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::8 14623840 11.14% 100.00% # Number of insts commited each cycle |
| 454system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 537system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 457system.cpu.commit.committed_per_cycle::total 131237904 # Number of insts commited each cycle | 540system.cpu.commit.committed_per_cycle::total 131282966 # Number of insts commited each cycle |
| 458system.cpu.commit.committedInsts 273037337 # Number of instructions committed 459system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed 460system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 461system.cpu.commit.refs 177024331 # Number of memory references committed 462system.cpu.commit.loads 94648748 # Number of loads committed 463system.cpu.commit.membars 11033 # Number of memory barriers committed 464system.cpu.commit.branches 30563497 # Number of branches committed 465system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 466system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. 467system.cpu.commit.function_calls 6225112 # Number of function calls committed. | 541system.cpu.commit.committedInsts 273037337 # Number of instructions committed 542system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed 543system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 544system.cpu.commit.refs 177024331 # Number of memory references committed 545system.cpu.commit.loads 94648748 # Number of loads committed 546system.cpu.commit.membars 11033 # Number of memory barriers committed 547system.cpu.commit.branches 30563497 # Number of branches committed 548system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 549system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. 550system.cpu.commit.function_calls 6225112 # Number of function calls committed. |
| 468system.cpu.commit.bw_lim_events 14628693 # number cycles where commit BW limit reached | 551system.cpu.commit.bw_lim_events 14623840 # number cycles where commit BW limit reached |
| 469system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 552system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 470system.cpu.rob.rob_reads 500590394 # The number of ROB reads 471system.cpu.rob.rob_writes 773026490 # The number of ROB writes 472system.cpu.timesIdled 6380 # Number of times that the entire CPU went into an idle state and unscheduled itself 473system.cpu.idleCycles 223680 # Total number of cycles that the CPU has spent unscheduled due to idling | 553system.cpu.rob.rob_reads 500779997 # The number of ROB reads 554system.cpu.rob.rob_writes 773327958 # The number of ROB writes 555system.cpu.timesIdled 6728 # Number of times that the entire CPU went into an idle state and unscheduled itself 556system.cpu.idleCycles 320016 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 474system.cpu.committedInsts 273036725 # Number of Instructions Simulated 475system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated 476system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated | 557system.cpu.committedInsts 273036725 # Number of Instructions Simulated 558system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated 559system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated |
| 477system.cpu.cpi 0.499994 # CPI: Cycles Per Instruction 478system.cpu.cpi_total 0.499994 # CPI: Total CPI of All Threads 479system.cpu.ipc 2.000024 # IPC: Instructions Per Cycle 480system.cpu.ipc_total 2.000024 # IPC: Total IPC of All Threads 481system.cpu.int_regfile_reads 1768667875 # number of integer regfile reads 482system.cpu.int_regfile_writes 232756138 # number of integer regfile writes 483system.cpu.fp_regfile_reads 188077365 # number of floating regfile reads 484system.cpu.fp_regfile_writes 132460015 # number of floating regfile writes 485system.cpu.misc_regfile_reads 566729148 # number of misc regfile reads | 560system.cpu.cpi 0.500593 # CPI: Cycles Per Instruction 561system.cpu.cpi_total 0.500593 # CPI: Total CPI of All Threads 562system.cpu.ipc 1.997633 # IPC: Instructions Per Cycle 563system.cpu.ipc_total 1.997633 # IPC: Total IPC of All Threads 564system.cpu.int_regfile_reads 1768864956 # number of integer regfile reads 565system.cpu.int_regfile_writes 232856502 # number of integer regfile writes 566system.cpu.fp_regfile_reads 188105910 # number of floating regfile reads 567system.cpu.fp_regfile_writes 132495512 # number of floating regfile writes 568system.cpu.misc_regfile_reads 566780330 # number of misc regfile reads |
| 486system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes | 569system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes |
| 487system.cpu.icache.replacements 13935 # number of replacements 488system.cpu.icache.tagsinuse 1853.031974 # Cycle average of tags in use 489system.cpu.icache.total_refs 37502330 # Total number of references to valid blocks. 490system.cpu.icache.sampled_refs 15827 # Sample count of references to valid blocks. 491system.cpu.icache.avg_refs 2369.516017 # Average number of references to valid blocks. | 570system.cpu.toL2Bus.throughput 20129917 # Throughput (bytes/s) 571system.cpu.toL2Bus.trans_dist::ReadReq 17615 # Transaction distribution 572system.cpu.toL2Bus.trans_dist::ReadResp 17615 # Transaction distribution 573system.cpu.toL2Bus.trans_dist::Writeback 1040 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadExReq 2840 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::ReadExResp 2840 # Transaction distribution 578system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31680 # Packet count per connected master and slave (bytes) 579system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10272 # Packet count per connected master and slave (bytes) 580system.cpu.toL2Bus.pkt_count 41952 # Packet count per connected master and slave (bytes) 581system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013504 # Cumulative packet size per connected master and slave (bytes) 582system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361664 # Cumulative packet size per connected master and slave (bytes) 583system.cpu.toL2Bus.tot_pkt_size 1375168 # Cumulative packet size per connected master and slave (bytes) 584system.cpu.toL2Bus.data_through_bus 1375168 # Total data (bytes) 585system.cpu.toL2Bus.snoop_data_through_bus 512 # Total snoop data (bytes) 586system.cpu.toL2Bus.reqLayer0.occupancy 11790000 # Layer occupancy (ticks) 587system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 588system.cpu.toL2Bus.respLayer0.occupancy 23771988 # Layer occupancy (ticks) 589system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 590system.cpu.toL2Bus.respLayer1.occupancy 6938461 # Layer occupancy (ticks) 591system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 592system.cpu.icache.replacements 13951 # number of replacements 593system.cpu.icache.tagsinuse 1844.969918 # Cycle average of tags in use 594system.cpu.icache.total_refs 37505309 # Total number of references to valid blocks. 595system.cpu.icache.sampled_refs 15840 # Sample count of references to valid blocks. 596system.cpu.icache.avg_refs 2367.759407 # Average number of references to valid blocks. |
| 492system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 597system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 493system.cpu.icache.occ_blocks::cpu.inst 1853.031974 # Average occupied blocks per requestor 494system.cpu.icache.occ_percent::cpu.inst 0.904801 # Average percentage of cache occupancy 495system.cpu.icache.occ_percent::total 0.904801 # Average percentage of cache occupancy 496system.cpu.icache.ReadReq_hits::cpu.inst 37502330 # number of ReadReq hits 497system.cpu.icache.ReadReq_hits::total 37502330 # number of ReadReq hits 498system.cpu.icache.demand_hits::cpu.inst 37502330 # number of demand (read+write) hits 499system.cpu.icache.demand_hits::total 37502330 # number of demand (read+write) hits 500system.cpu.icache.overall_hits::cpu.inst 37502330 # number of overall hits 501system.cpu.icache.overall_hits::total 37502330 # number of overall hits 502system.cpu.icache.ReadReq_misses::cpu.inst 17113 # number of ReadReq misses 503system.cpu.icache.ReadReq_misses::total 17113 # number of ReadReq misses 504system.cpu.icache.demand_misses::cpu.inst 17113 # number of demand (read+write) misses 505system.cpu.icache.demand_misses::total 17113 # number of demand (read+write) misses 506system.cpu.icache.overall_misses::cpu.inst 17113 # number of overall misses 507system.cpu.icache.overall_misses::total 17113 # number of overall misses 508system.cpu.icache.ReadReq_miss_latency::cpu.inst 362885498 # number of ReadReq miss cycles 509system.cpu.icache.ReadReq_miss_latency::total 362885498 # number of ReadReq miss cycles 510system.cpu.icache.demand_miss_latency::cpu.inst 362885498 # number of demand (read+write) miss cycles 511system.cpu.icache.demand_miss_latency::total 362885498 # number of demand (read+write) miss cycles 512system.cpu.icache.overall_miss_latency::cpu.inst 362885498 # number of overall miss cycles 513system.cpu.icache.overall_miss_latency::total 362885498 # number of overall miss cycles 514system.cpu.icache.ReadReq_accesses::cpu.inst 37519443 # number of ReadReq accesses(hits+misses) 515system.cpu.icache.ReadReq_accesses::total 37519443 # number of ReadReq accesses(hits+misses) 516system.cpu.icache.demand_accesses::cpu.inst 37519443 # number of demand (read+write) accesses 517system.cpu.icache.demand_accesses::total 37519443 # number of demand (read+write) accesses 518system.cpu.icache.overall_accesses::cpu.inst 37519443 # number of overall (read+write) accesses 519system.cpu.icache.overall_accesses::total 37519443 # number of overall (read+write) accesses 520system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000456 # miss rate for ReadReq accesses 521system.cpu.icache.ReadReq_miss_rate::total 0.000456 # miss rate for ReadReq accesses 522system.cpu.icache.demand_miss_rate::cpu.inst 0.000456 # miss rate for demand accesses 523system.cpu.icache.demand_miss_rate::total 0.000456 # miss rate for demand accesses 524system.cpu.icache.overall_miss_rate::cpu.inst 0.000456 # miss rate for overall accesses 525system.cpu.icache.overall_miss_rate::total 0.000456 # miss rate for overall accesses 526system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21205.253199 # average ReadReq miss latency 527system.cpu.icache.ReadReq_avg_miss_latency::total 21205.253199 # average ReadReq miss latency 528system.cpu.icache.demand_avg_miss_latency::cpu.inst 21205.253199 # average overall miss latency 529system.cpu.icache.demand_avg_miss_latency::total 21205.253199 # average overall miss latency 530system.cpu.icache.overall_avg_miss_latency::cpu.inst 21205.253199 # average overall miss latency 531system.cpu.icache.overall_avg_miss_latency::total 21205.253199 # average overall miss latency 532system.cpu.icache.blocked_cycles::no_mshrs 563 # number of cycles access was blocked | 598system.cpu.icache.occ_blocks::cpu.inst 1844.969918 # Average occupied blocks per requestor 599system.cpu.icache.occ_percent::cpu.inst 0.900864 # Average percentage of cache occupancy 600system.cpu.icache.occ_percent::total 0.900864 # Average percentage of cache occupancy 601system.cpu.icache.ReadReq_hits::cpu.inst 37505309 # number of ReadReq hits 602system.cpu.icache.ReadReq_hits::total 37505309 # number of ReadReq hits 603system.cpu.icache.demand_hits::cpu.inst 37505309 # number of demand (read+write) hits 604system.cpu.icache.demand_hits::total 37505309 # number of demand (read+write) hits 605system.cpu.icache.overall_hits::cpu.inst 37505309 # number of overall hits 606system.cpu.icache.overall_hits::total 37505309 # number of overall hits 607system.cpu.icache.ReadReq_misses::cpu.inst 17311 # number of ReadReq misses 608system.cpu.icache.ReadReq_misses::total 17311 # number of ReadReq misses 609system.cpu.icache.demand_misses::cpu.inst 17311 # number of demand (read+write) misses 610system.cpu.icache.demand_misses::total 17311 # number of demand (read+write) misses 611system.cpu.icache.overall_misses::cpu.inst 17311 # number of overall misses 612system.cpu.icache.overall_misses::total 17311 # number of overall misses 613system.cpu.icache.ReadReq_miss_latency::cpu.inst 438177497 # number of ReadReq miss cycles 614system.cpu.icache.ReadReq_miss_latency::total 438177497 # number of ReadReq miss cycles 615system.cpu.icache.demand_miss_latency::cpu.inst 438177497 # number of demand (read+write) miss cycles 616system.cpu.icache.demand_miss_latency::total 438177497 # number of demand (read+write) miss cycles 617system.cpu.icache.overall_miss_latency::cpu.inst 438177497 # number of overall miss cycles 618system.cpu.icache.overall_miss_latency::total 438177497 # number of overall miss cycles 619system.cpu.icache.ReadReq_accesses::cpu.inst 37522620 # number of ReadReq accesses(hits+misses) 620system.cpu.icache.ReadReq_accesses::total 37522620 # number of ReadReq accesses(hits+misses) 621system.cpu.icache.demand_accesses::cpu.inst 37522620 # number of demand (read+write) accesses 622system.cpu.icache.demand_accesses::total 37522620 # number of demand (read+write) accesses 623system.cpu.icache.overall_accesses::cpu.inst 37522620 # number of overall (read+write) accesses 624system.cpu.icache.overall_accesses::total 37522620 # number of overall (read+write) accesses 625system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses 626system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses 627system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses 628system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses 629system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses 630system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses 631system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25312.084628 # average ReadReq miss latency 632system.cpu.icache.ReadReq_avg_miss_latency::total 25312.084628 # average ReadReq miss latency 633system.cpu.icache.demand_avg_miss_latency::cpu.inst 25312.084628 # average overall miss latency 634system.cpu.icache.demand_avg_miss_latency::total 25312.084628 # average overall miss latency 635system.cpu.icache.overall_avg_miss_latency::cpu.inst 25312.084628 # average overall miss latency 636system.cpu.icache.overall_avg_miss_latency::total 25312.084628 # average overall miss latency 637system.cpu.icache.blocked_cycles::no_mshrs 919 # number of cycles access was blocked |
| 533system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 638system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 534system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked | 639system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked |
| 535system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 640system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 536system.cpu.icache.avg_blocked_cycles::no_mshrs 31.277778 # average number of cycles each access was blocked | 641system.cpu.icache.avg_blocked_cycles::no_mshrs 39.956522 # average number of cycles each access was blocked |
| 537system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 538system.cpu.icache.fast_writes 0 # number of fast writes performed 539system.cpu.icache.cache_copies 0 # number of cache copies performed | 642system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.icache.fast_writes 0 # number of fast writes performed 644system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 540system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1284 # number of ReadReq MSHR hits 541system.cpu.icache.ReadReq_mshr_hits::total 1284 # number of ReadReq MSHR hits 542system.cpu.icache.demand_mshr_hits::cpu.inst 1284 # number of demand (read+write) MSHR hits 543system.cpu.icache.demand_mshr_hits::total 1284 # number of demand (read+write) MSHR hits 544system.cpu.icache.overall_mshr_hits::cpu.inst 1284 # number of overall MSHR hits 545system.cpu.icache.overall_mshr_hits::total 1284 # number of overall MSHR hits 546system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15829 # number of ReadReq MSHR misses 547system.cpu.icache.ReadReq_mshr_misses::total 15829 # number of ReadReq MSHR misses 548system.cpu.icache.demand_mshr_misses::cpu.inst 15829 # number of demand (read+write) MSHR misses 549system.cpu.icache.demand_mshr_misses::total 15829 # number of demand (read+write) MSHR misses 550system.cpu.icache.overall_mshr_misses::cpu.inst 15829 # number of overall MSHR misses 551system.cpu.icache.overall_mshr_misses::total 15829 # number of overall MSHR misses 552system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296585998 # number of ReadReq MSHR miss cycles 553system.cpu.icache.ReadReq_mshr_miss_latency::total 296585998 # number of ReadReq MSHR miss cycles 554system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296585998 # number of demand (read+write) MSHR miss cycles 555system.cpu.icache.demand_mshr_miss_latency::total 296585998 # number of demand (read+write) MSHR miss cycles 556system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296585998 # number of overall MSHR miss cycles 557system.cpu.icache.overall_mshr_miss_latency::total 296585998 # number of overall MSHR miss cycles | 645system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1467 # number of ReadReq MSHR hits 646system.cpu.icache.ReadReq_mshr_hits::total 1467 # number of ReadReq MSHR hits 647system.cpu.icache.demand_mshr_hits::cpu.inst 1467 # number of demand (read+write) MSHR hits 648system.cpu.icache.demand_mshr_hits::total 1467 # number of demand (read+write) MSHR hits 649system.cpu.icache.overall_mshr_hits::cpu.inst 1467 # number of overall MSHR hits 650system.cpu.icache.overall_mshr_hits::total 1467 # number of overall MSHR hits 651system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15844 # number of ReadReq MSHR misses 652system.cpu.icache.ReadReq_mshr_misses::total 15844 # number of ReadReq MSHR misses 653system.cpu.icache.demand_mshr_misses::cpu.inst 15844 # number of demand (read+write) MSHR misses 654system.cpu.icache.demand_mshr_misses::total 15844 # number of demand (read+write) MSHR misses 655system.cpu.icache.overall_mshr_misses::cpu.inst 15844 # number of overall MSHR misses 656system.cpu.icache.overall_mshr_misses::total 15844 # number of overall MSHR misses 657system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 350210509 # number of ReadReq MSHR miss cycles 658system.cpu.icache.ReadReq_mshr_miss_latency::total 350210509 # number of ReadReq MSHR miss cycles 659system.cpu.icache.demand_mshr_miss_latency::cpu.inst 350210509 # number of demand (read+write) MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::total 350210509 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350210509 # number of overall MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::total 350210509 # number of overall MSHR miss cycles |
| 558system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses 559system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses 560system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses 561system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses 562system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses 563system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses | 663system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses 664system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses 665system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses 666system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses 667system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses 668system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses |
| 564system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18736.875229 # average ReadReq mshr miss latency 565system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18736.875229 # average ReadReq mshr miss latency 566system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18736.875229 # average overall mshr miss latency 567system.cpu.icache.demand_avg_mshr_miss_latency::total 18736.875229 # average overall mshr miss latency 568system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18736.875229 # average overall mshr miss latency 569system.cpu.icache.overall_avg_mshr_miss_latency::total 18736.875229 # average overall mshr miss latency | 669system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22103.667571 # average ReadReq mshr miss latency 670system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22103.667571 # average ReadReq mshr miss latency 671system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22103.667571 # average overall mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::total 22103.667571 # average overall mshr miss latency 673system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22103.667571 # average overall mshr miss latency 674system.cpu.icache.overall_avg_mshr_miss_latency::total 22103.667571 # average overall mshr miss latency |
| 570system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 571system.cpu.l2cache.replacements 0 # number of replacements | 675system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 676system.cpu.l2cache.replacements 0 # number of replacements |
| 572system.cpu.l2cache.tagsinuse 3957.039079 # Cycle average of tags in use 573system.cpu.l2cache.total_refs 13204 # Total number of references to valid blocks. 574system.cpu.l2cache.sampled_refs 5395 # Sample count of references to valid blocks. 575system.cpu.l2cache.avg_refs 2.447451 # Average number of references to valid blocks. | 677system.cpu.l2cache.tagsinuse 3935.480728 # Cycle average of tags in use 678system.cpu.l2cache.total_refs 13190 # Total number of references to valid blocks. 679system.cpu.l2cache.sampled_refs 5388 # Sample count of references to valid blocks. 680system.cpu.l2cache.avg_refs 2.448033 # Average number of references to valid blocks. |
| 576system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 681system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 577system.cpu.l2cache.occ_blocks::writebacks 371.045969 # Average occupied blocks per requestor 578system.cpu.l2cache.occ_blocks::cpu.inst 2777.593343 # Average occupied blocks per requestor 579system.cpu.l2cache.occ_blocks::cpu.data 808.399767 # Average occupied blocks per requestor 580system.cpu.l2cache.occ_percent::writebacks 0.011323 # Average percentage of cache occupancy 581system.cpu.l2cache.occ_percent::cpu.inst 0.084765 # Average percentage of cache occupancy 582system.cpu.l2cache.occ_percent::cpu.data 0.024670 # Average percentage of cache occupancy 583system.cpu.l2cache.occ_percent::total 0.120759 # Average percentage of cache occupancy 584system.cpu.l2cache.ReadReq_hits::cpu.inst 12784 # number of ReadReq hits 585system.cpu.l2cache.ReadReq_hits::cpu.data 306 # number of ReadReq hits 586system.cpu.l2cache.ReadReq_hits::total 13090 # number of ReadReq hits 587system.cpu.l2cache.Writeback_hits::writebacks 1043 # number of Writeback hits 588system.cpu.l2cache.Writeback_hits::total 1043 # number of Writeback hits | 682system.cpu.l2cache.occ_blocks::writebacks 380.401816 # Average occupied blocks per requestor 683system.cpu.l2cache.occ_blocks::cpu.inst 2774.612860 # Average occupied blocks per requestor 684system.cpu.l2cache.occ_blocks::cpu.data 780.466052 # Average occupied blocks per requestor 685system.cpu.l2cache.occ_percent::writebacks 0.011609 # Average percentage of cache occupancy 686system.cpu.l2cache.occ_percent::cpu.inst 0.084674 # Average percentage of cache occupancy 687system.cpu.l2cache.occ_percent::cpu.data 0.023818 # Average percentage of cache occupancy 688system.cpu.l2cache.occ_percent::total 0.120101 # Average percentage of cache occupancy 689system.cpu.l2cache.ReadReq_hits::cpu.inst 12795 # number of ReadReq hits 690system.cpu.l2cache.ReadReq_hits::cpu.data 300 # number of ReadReq hits 691system.cpu.l2cache.ReadReq_hits::total 13095 # number of ReadReq hits 692system.cpu.l2cache.Writeback_hits::writebacks 1040 # number of Writeback hits 693system.cpu.l2cache.Writeback_hits::total 1040 # number of Writeback hits |
| 589system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits 590system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits | 694system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits 695system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits |
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| 606system.cpu.l2cache.demand_misses::total 7334 # number of demand (read+write) misses 607system.cpu.l2cache.overall_misses::cpu.inst 3040 # number of overall misses | 711system.cpu.l2cache.demand_misses::total 7335 # number of demand (read+write) misses 712system.cpu.l2cache.overall_misses::cpu.inst 3041 # number of overall misses |
| 608system.cpu.l2cache.overall_misses::cpu.data 4294 # number of overall misses | 713system.cpu.l2cache.overall_misses::cpu.data 4294 # number of overall misses |
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number of overall miss cycles 620system.cpu.l2cache.overall_miss_latency::total 369929000 # number of overall miss cycles 621system.cpu.l2cache.ReadReq_accesses::cpu.inst 15824 # number of ReadReq accesses(hits+misses) 622system.cpu.l2cache.ReadReq_accesses::cpu.data 1803 # number of ReadReq accesses(hits+misses) 623system.cpu.l2cache.ReadReq_accesses::total 17627 # number of ReadReq accesses(hits+misses) 624system.cpu.l2cache.Writeback_accesses::writebacks 1043 # number of Writeback accesses(hits+misses) 625system.cpu.l2cache.Writeback_accesses::total 1043 # number of Writeback accesses(hits+misses) 626system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) 627system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) 628system.cpu.l2cache.ReadExReq_accesses::cpu.data 2814 # number of ReadExReq accesses(hits+misses) 629system.cpu.l2cache.ReadExReq_accesses::total 2814 # number of ReadExReq accesses(hits+misses) 630system.cpu.l2cache.demand_accesses::cpu.inst 15824 # number of demand (read+write) accesses 631system.cpu.l2cache.demand_accesses::cpu.data 4617 # number of demand (read+write) accesses 632system.cpu.l2cache.demand_accesses::total 20441 # number of demand (read+write) accesses 633system.cpu.l2cache.overall_accesses::cpu.inst 15824 # number of overall (read+write) accesses 634system.cpu.l2cache.overall_accesses::cpu.data 4617 # number of overall (read+write) accesses 635system.cpu.l2cache.overall_accesses::total 20441 # number of overall (read+write) accesses 636system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192113 # miss rate for ReadReq accesses 637system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830283 # miss rate for ReadReq accesses 638system.cpu.l2cache.ReadReq_miss_rate::total 0.257389 # miss rate for ReadReq accesses | 714system.cpu.l2cache.overall_misses::total 7335 # number of overall misses 715system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 206379500 # number of ReadReq miss cycles 716system.cpu.l2cache.ReadReq_miss_latency::cpu.data 101600000 # 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number of ReadReq accesses(hits+misses) 728system.cpu.l2cache.ReadReq_accesses::total 17607 # number of ReadReq accesses(hits+misses) 729system.cpu.l2cache.Writeback_accesses::writebacks 1040 # number of Writeback accesses(hits+misses) 730system.cpu.l2cache.Writeback_accesses::total 1040 # number of Writeback accesses(hits+misses) 731system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) 732system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) 733system.cpu.l2cache.ReadExReq_accesses::cpu.data 2840 # number of ReadExReq accesses(hits+misses) 734system.cpu.l2cache.ReadExReq_accesses::total 2840 # number of ReadExReq accesses(hits+misses) 735system.cpu.l2cache.demand_accesses::cpu.inst 15836 # number of demand (read+write) accesses 736system.cpu.l2cache.demand_accesses::cpu.data 4611 # number of demand (read+write) accesses 737system.cpu.l2cache.demand_accesses::total 20447 # number of demand (read+write) accesses 738system.cpu.l2cache.overall_accesses::cpu.inst 15836 # number of overall (read+write) accesses 739system.cpu.l2cache.overall_accesses::cpu.data 4611 # number of overall (read+write) accesses 740system.cpu.l2cache.overall_accesses::total 20447 # number of overall (read+write) accesses 741system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192031 # miss rate for ReadReq accesses 742system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830604 # miss rate for ReadReq accesses 743system.cpu.l2cache.ReadReq_miss_rate::total 0.256262 # miss rate for ReadReq accesses |
| 639system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 640system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 744system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 745system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 641system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993959 # miss rate for ReadExReq accesses 642system.cpu.l2cache.ReadExReq_miss_rate::total 0.993959 # miss rate for ReadExReq accesses 643system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192113 # miss rate for demand accesses 644system.cpu.l2cache.demand_miss_rate::cpu.data 0.930041 # miss rate for demand accesses 645system.cpu.l2cache.demand_miss_rate::total 0.358789 # miss rate for demand accesses 646system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192113 # miss rate for overall accesses 647system.cpu.l2cache.overall_miss_rate::cpu.data 0.930041 # miss rate for overall accesses 648system.cpu.l2cache.overall_miss_rate::total 0.358789 # miss rate for overall accesses 649system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50281.414474 # average ReadReq miss latency 650system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54268.871075 # average ReadReq miss latency 651system.cpu.l2cache.ReadReq_avg_miss_latency::total 51597.090588 # average ReadReq miss latency 652system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48563.818377 # average ReadExReq miss latency 653system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48563.818377 # average ReadExReq miss latency 654system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50281.414474 # average overall miss latency 655system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50552.748020 # average overall miss latency 656system.cpu.l2cache.demand_avg_miss_latency::total 50440.278157 # average overall miss latency 657system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50281.414474 # average overall miss latency 658system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50552.748020 # average overall miss latency 659system.cpu.l2cache.overall_avg_miss_latency::total 50440.278157 # average overall miss latency | 746system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994014 # miss rate for ReadExReq accesses 747system.cpu.l2cache.ReadExReq_miss_rate::total 0.994014 # miss rate for ReadExReq accesses 748system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192031 # miss rate for demand accesses 749system.cpu.l2cache.demand_miss_rate::cpu.data 0.931251 # miss rate for demand accesses 750system.cpu.l2cache.demand_miss_rate::total 0.358732 # miss rate for demand accesses 751system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192031 # miss rate for overall accesses 752system.cpu.l2cache.overall_miss_rate::cpu.data 0.931251 # miss rate for overall accesses 753system.cpu.l2cache.overall_miss_rate::total 0.358732 # miss rate for overall accesses 754system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67865.669188 # average ReadReq miss latency 755system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69068.660775 # average ReadReq miss latency 756system.cpu.l2cache.ReadReq_avg_miss_latency::total 68257.867908 # average ReadReq miss latency 757system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66821.112292 # average ReadExReq miss latency 758system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66821.112292 # average ReadExReq miss latency 759system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67865.669188 # average overall miss latency 760system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67591.057289 # average overall miss latency 761system.cpu.l2cache.demand_avg_miss_latency::total 67704.907975 # average overall miss latency 762system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67865.669188 # average overall miss latency 763system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67591.057289 # average overall miss latency 764system.cpu.l2cache.overall_avg_miss_latency::total 67704.907975 # average overall miss latency |
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| 669system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits 670system.cpu.l2cache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits | 774system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits 775system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits |
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number of overall MSHR misses 793system.cpu.l2cache.overall_mshr_misses::cpu.data 4255 # number of overall MSHR misses 794system.cpu.l2cache.overall_mshr_misses::total 7284 # number of overall MSHR misses 795system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168121750 # number of ReadReq MSHR miss cycles 796system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 81472500 # number of ReadReq MSHR miss cycles 797system.cpu.l2cache.ReadReq_mshr_miss_latency::total 249594250 # number of ReadReq MSHR miss cycles 798system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 51504 # number of UpgradeReq MSHR miss cycles 799system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 51504 # number of UpgradeReq MSHR miss cycles 800system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 153947250 # number of ReadExReq MSHR miss cycles 801system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 153947250 # number of ReadExReq MSHR miss cycles 802system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168121750 # number of demand (read+write) MSHR miss cycles 803system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 235419750 # number of demand (read+write) MSHR miss cycles 804system.cpu.l2cache.demand_mshr_miss_latency::total 403541500 # number of demand (read+write) MSHR miss cycles 805system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168121750 # number of overall MSHR miss cycles 806system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235419750 # number of overall MSHR miss cycles 807system.cpu.l2cache.overall_mshr_miss_latency::total 403541500 # number of overall MSHR miss cycles 808system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for ReadReq accesses 809system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808583 # mshr miss rate for ReadReq accesses 810system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253365 # mshr miss rate for ReadReq accesses |
| 706system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 707system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 811system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 812system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 708system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993959 # mshr miss rate for ReadExReq accesses 709system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993959 # mshr miss rate for ReadExReq accesses 710system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191355 # mshr miss rate for demand accesses 711system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921161 # mshr miss rate for demand accesses 712system.cpu.l2cache.demand_mshr_miss_rate::total 0.356196 # mshr miss rate for demand accesses 713system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191355 # mshr miss rate for overall accesses 714system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921161 # mshr miss rate for overall accesses 715system.cpu.l2cache.overall_mshr_miss_rate::total 0.356196 # mshr miss rate for overall accesses 716system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37896.574306 # average ReadReq mshr miss latency 717system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42305.027473 # average ReadReq mshr miss latency 718system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39328.043488 # average ReadReq mshr miss latency 719system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 720system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 721system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36300.047193 # average ReadExReq mshr miss latency 722system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36300.047193 # average ReadExReq mshr miss latency 723system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37896.574306 # average overall mshr miss latency 724system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38355.831648 # average overall mshr miss latency 725system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38164.837110 # average overall mshr miss latency 726system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37896.574306 # average overall mshr miss latency 727system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38355.831648 # average overall mshr miss latency 728system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38164.837110 # average overall mshr miss latency | 813system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994014 # mshr miss rate for ReadExReq accesses 814system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994014 # mshr miss rate for ReadExReq accesses 815system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for demand accesses 816system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for demand accesses 817system.cpu.l2cache.demand_mshr_miss_rate::total 0.356238 # mshr miss rate for demand accesses 818system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for overall accesses 819system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for overall accesses 820system.cpu.l2cache.overall_mshr_miss_rate::total 0.356238 # mshr miss rate for overall accesses 821system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55504.044239 # average ReadReq mshr miss latency 822system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56894.203911 # average ReadReq mshr miss latency 823system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55950.291414 # average ReadReq mshr miss latency 824system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10300.800000 # average UpgradeReq mshr miss latency 825system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10300.800000 # average UpgradeReq mshr miss latency 826system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54533.209352 # average ReadExReq mshr miss latency 827system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54533.209352 # average ReadExReq mshr miss latency 828system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency 829system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency 830system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency 831system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency 832system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency 833system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency |
| 729system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 834system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 730system.cpu.dcache.replacements 1423 # number of replacements 731system.cpu.dcache.tagsinuse 3104.940004 # Cycle average of tags in use 732system.cpu.dcache.total_refs 170839954 # Total number of references to valid blocks. 733system.cpu.dcache.sampled_refs 4617 # Sample count of references to valid blocks. 734system.cpu.dcache.avg_refs 37002.372536 # Average number of references to valid blocks. | 835system.cpu.dcache.replacements 1417 # number of replacements 836system.cpu.dcache.tagsinuse 3105.227160 # Cycle average of tags in use 837system.cpu.dcache.total_refs 170865642 # Total number of references to valid blocks. 838system.cpu.dcache.sampled_refs 4611 # Sample count of references to valid blocks. 839system.cpu.dcache.avg_refs 37056.092388 # Average number of references to valid blocks. |
| 735system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 840system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 736system.cpu.dcache.occ_blocks::cpu.data 3104.940004 # Average occupied blocks per requestor 737system.cpu.dcache.occ_percent::cpu.data 0.758042 # Average percentage of cache occupancy 738system.cpu.dcache.occ_percent::total 0.758042 # Average percentage of cache occupancy 739system.cpu.dcache.ReadReq_hits::cpu.data 88786548 # number of ReadReq hits 740system.cpu.dcache.ReadReq_hits::total 88786548 # number of ReadReq hits 741system.cpu.dcache.WriteReq_hits::cpu.data 82031492 # number of WriteReq hits 742system.cpu.dcache.WriteReq_hits::total 82031492 # number of WriteReq hits 743system.cpu.dcache.LoadLockedReq_hits::cpu.data 11005 # number of LoadLockedReq hits 744system.cpu.dcache.LoadLockedReq_hits::total 11005 # number of LoadLockedReq hits | 841system.cpu.dcache.occ_blocks::cpu.data 3105.227160 # Average occupied blocks per requestor 842system.cpu.dcache.occ_percent::cpu.data 0.758112 # Average percentage of cache occupancy 843system.cpu.dcache.occ_percent::total 0.758112 # Average percentage of cache occupancy 844system.cpu.dcache.ReadReq_hits::cpu.data 88812489 # number of ReadReq hits 845system.cpu.dcache.ReadReq_hits::total 88812489 # number of ReadReq hits 846system.cpu.dcache.WriteReq_hits::cpu.data 82031226 # number of WriteReq hits 847system.cpu.dcache.WriteReq_hits::total 82031226 # number of WriteReq hits 848system.cpu.dcache.LoadLockedReq_hits::cpu.data 11012 # number of LoadLockedReq hits 849system.cpu.dcache.LoadLockedReq_hits::total 11012 # number of LoadLockedReq hits |
| 745system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 746system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits | 850system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 851system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits |
| 747system.cpu.dcache.demand_hits::cpu.data 170818040 # number of demand (read+write) hits 748system.cpu.dcache.demand_hits::total 170818040 # number of demand (read+write) hits 749system.cpu.dcache.overall_hits::cpu.data 170818040 # number of overall hits 750system.cpu.dcache.overall_hits::total 170818040 # number of overall hits 751system.cpu.dcache.ReadReq_misses::cpu.data 4058 # number of ReadReq misses 752system.cpu.dcache.ReadReq_misses::total 4058 # number of ReadReq misses 753system.cpu.dcache.WriteReq_misses::cpu.data 21173 # number of WriteReq misses 754system.cpu.dcache.WriteReq_misses::total 21173 # number of WriteReq misses | 852system.cpu.dcache.demand_hits::cpu.data 170843715 # number of demand (read+write) hits 853system.cpu.dcache.demand_hits::total 170843715 # number of demand (read+write) hits 854system.cpu.dcache.overall_hits::cpu.data 170843715 # number of overall hits 855system.cpu.dcache.overall_hits::total 170843715 # number of overall hits 856system.cpu.dcache.ReadReq_misses::cpu.data 3995 # number of ReadReq misses 857system.cpu.dcache.ReadReq_misses::total 3995 # number of ReadReq misses 858system.cpu.dcache.WriteReq_misses::cpu.data 21439 # number of WriteReq misses 859system.cpu.dcache.WriteReq_misses::total 21439 # number of WriteReq misses |
| 755system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 756system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 860system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 861system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 757system.cpu.dcache.demand_misses::cpu.data 25231 # number of demand (read+write) misses 758system.cpu.dcache.demand_misses::total 25231 # number of demand (read+write) misses 759system.cpu.dcache.overall_misses::cpu.data 25231 # number of overall misses 760system.cpu.dcache.overall_misses::total 25231 # number of overall misses 761system.cpu.dcache.ReadReq_miss_latency::cpu.data 177480000 # number of ReadReq miss cycles 762system.cpu.dcache.ReadReq_miss_latency::total 177480000 # number of ReadReq miss cycles 763system.cpu.dcache.WriteReq_miss_latency::cpu.data 877819657 # number of WriteReq miss cycles 764system.cpu.dcache.WriteReq_miss_latency::total 877819657 # number of WriteReq miss cycles 765system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116000 # number of LoadLockedReq miss cycles 766system.cpu.dcache.LoadLockedReq_miss_latency::total 116000 # number of LoadLockedReq miss cycles 767system.cpu.dcache.demand_miss_latency::cpu.data 1055299657 # number of demand (read+write) miss cycles 768system.cpu.dcache.demand_miss_latency::total 1055299657 # number of demand (read+write) miss cycles 769system.cpu.dcache.overall_miss_latency::cpu.data 1055299657 # number of overall miss cycles 770system.cpu.dcache.overall_miss_latency::total 1055299657 # number of overall miss cycles 771system.cpu.dcache.ReadReq_accesses::cpu.data 88790606 # number of ReadReq accesses(hits+misses) 772system.cpu.dcache.ReadReq_accesses::total 88790606 # number of ReadReq accesses(hits+misses) | 862system.cpu.dcache.demand_misses::cpu.data 25434 # number of demand (read+write) misses 863system.cpu.dcache.demand_misses::total 25434 # number of demand (read+write) misses 864system.cpu.dcache.overall_misses::cpu.data 25434 # number of overall misses 865system.cpu.dcache.overall_misses::total 25434 # number of overall misses 866system.cpu.dcache.ReadReq_miss_latency::cpu.data 218203000 # number of ReadReq miss cycles 867system.cpu.dcache.ReadReq_miss_latency::total 218203000 # number of ReadReq miss cycles 868system.cpu.dcache.WriteReq_miss_latency::cpu.data 1190820596 # number of WriteReq miss cycles 869system.cpu.dcache.WriteReq_miss_latency::total 1190820596 # number of WriteReq miss cycles 870system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155000 # number of LoadLockedReq miss cycles 871system.cpu.dcache.LoadLockedReq_miss_latency::total 155000 # number of LoadLockedReq miss cycles 872system.cpu.dcache.demand_miss_latency::cpu.data 1409023596 # number of demand (read+write) miss cycles 873system.cpu.dcache.demand_miss_latency::total 1409023596 # number of demand (read+write) miss cycles 874system.cpu.dcache.overall_miss_latency::cpu.data 1409023596 # number of overall miss cycles 875system.cpu.dcache.overall_miss_latency::total 1409023596 # number of overall miss cycles 876system.cpu.dcache.ReadReq_accesses::cpu.data 88816484 # number of ReadReq accesses(hits+misses) 877system.cpu.dcache.ReadReq_accesses::total 88816484 # number of ReadReq accesses(hits+misses) |
| 773system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) 774system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) | 878system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) 879system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) |
| 775system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11007 # number of LoadLockedReq accesses(hits+misses) 776system.cpu.dcache.LoadLockedReq_accesses::total 11007 # number of LoadLockedReq accesses(hits+misses) | 880system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11014 # number of LoadLockedReq accesses(hits+misses) 881system.cpu.dcache.LoadLockedReq_accesses::total 11014 # number of LoadLockedReq accesses(hits+misses) |
| 777system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 778system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) | 882system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 883system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) |
| 779system.cpu.dcache.demand_accesses::cpu.data 170843271 # number of demand (read+write) accesses 780system.cpu.dcache.demand_accesses::total 170843271 # number of demand (read+write) accesses 781system.cpu.dcache.overall_accesses::cpu.data 170843271 # number of overall (read+write) accesses 782system.cpu.dcache.overall_accesses::total 170843271 # number of overall (read+write) accesses 783system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses 784system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses 785system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses 786system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses | 884system.cpu.dcache.demand_accesses::cpu.data 170869149 # number of demand (read+write) accesses 885system.cpu.dcache.demand_accesses::total 170869149 # number of demand (read+write) accesses 886system.cpu.dcache.overall_accesses::cpu.data 170869149 # number of overall (read+write) accesses 887system.cpu.dcache.overall_accesses::total 170869149 # number of overall (read+write) accesses 888system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses 889system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 890system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses 891system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses |
| 787system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses 788system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses | 892system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses 893system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses |
| 789system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses 790system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses 791system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses 792system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses 793system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43735.830458 # average ReadReq miss latency 794system.cpu.dcache.ReadReq_avg_miss_latency::total 43735.830458 # average ReadReq miss latency 795system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389647 # average WriteReq miss latency 796system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389647 # average WriteReq miss latency 797system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58000 # average LoadLockedReq miss latency 798system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58000 # average LoadLockedReq miss latency 799system.cpu.dcache.demand_avg_miss_latency::cpu.data 41825.518489 # average overall miss latency 800system.cpu.dcache.demand_avg_miss_latency::total 41825.518489 # average overall miss latency 801system.cpu.dcache.overall_avg_miss_latency::cpu.data 41825.518489 # average overall miss latency 802system.cpu.dcache.overall_avg_miss_latency::total 41825.518489 # average overall miss latency 803system.cpu.dcache.blocked_cycles::no_mshrs 15191 # number of cycles access was blocked 804system.cpu.dcache.blocked_cycles::no_targets 833 # number of cycles access was blocked 805system.cpu.dcache.blocked::no_mshrs 436 # number of cycles access was blocked | 894system.cpu.dcache.demand_miss_rate::cpu.data 0.000149 # miss rate for demand accesses 895system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses 896system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses 897system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses 898system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54619.023780 # average ReadReq miss latency 899system.cpu.dcache.ReadReq_avg_miss_latency::total 54619.023780 # average ReadReq miss latency 900system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55544.596110 # average WriteReq miss latency 901system.cpu.dcache.WriteReq_avg_miss_latency::total 55544.596110 # average WriteReq miss latency 902system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77500 # average LoadLockedReq miss latency 903system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77500 # average LoadLockedReq miss latency 904system.cpu.dcache.demand_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency 905system.cpu.dcache.demand_avg_miss_latency::total 55399.213494 # average overall miss latency 906system.cpu.dcache.overall_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency 907system.cpu.dcache.overall_avg_miss_latency::total 55399.213494 # average overall miss latency 908system.cpu.dcache.blocked_cycles::no_mshrs 24937 # number of cycles access was blocked 909system.cpu.dcache.blocked_cycles::no_targets 1182 # number of cycles access was blocked 910system.cpu.dcache.blocked::no_mshrs 461 # number of cycles access was blocked |
| 806system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked | 911system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked |
| 807system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.841743 # average number of cycles each access was blocked 808system.cpu.dcache.avg_blocked_cycles::no_targets 64.076923 # average number of cycles each access was blocked | 912system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.093275 # average number of cycles each access was blocked 913system.cpu.dcache.avg_blocked_cycles::no_targets 90.923077 # average number of cycles each access was blocked |
| 809system.cpu.dcache.fast_writes 0 # number of fast writes performed 810system.cpu.dcache.cache_copies 0 # number of cache copies performed | 914system.cpu.dcache.fast_writes 0 # number of fast writes performed 915system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 811system.cpu.dcache.writebacks::writebacks 1043 # number of writebacks 812system.cpu.dcache.writebacks::total 1043 # number of writebacks 813system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2254 # number of ReadReq MSHR hits 814system.cpu.dcache.ReadReq_mshr_hits::total 2254 # number of ReadReq MSHR hits 815system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18357 # number of WriteReq MSHR hits 816system.cpu.dcache.WriteReq_mshr_hits::total 18357 # number of WriteReq MSHR hits | 916system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks 917system.cpu.dcache.writebacks::total 1040 # number of writebacks 918system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2223 # number of ReadReq MSHR hits 919system.cpu.dcache.ReadReq_mshr_hits::total 2223 # number of ReadReq MSHR hits 920system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18595 # number of WriteReq MSHR hits 921system.cpu.dcache.WriteReq_mshr_hits::total 18595 # number of WriteReq MSHR hits |
| 817system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 818system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 922system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 923system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 819system.cpu.dcache.demand_mshr_hits::cpu.data 20611 # number of demand (read+write) MSHR hits 820system.cpu.dcache.demand_mshr_hits::total 20611 # number of demand (read+write) MSHR hits 821system.cpu.dcache.overall_mshr_hits::cpu.data 20611 # number of overall MSHR hits 822system.cpu.dcache.overall_mshr_hits::total 20611 # number of overall MSHR hits 823system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1804 # number of ReadReq MSHR misses 824system.cpu.dcache.ReadReq_mshr_misses::total 1804 # number of ReadReq MSHR misses 825system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2816 # number of WriteReq MSHR misses 826system.cpu.dcache.WriteReq_mshr_misses::total 2816 # number of WriteReq MSHR misses 827system.cpu.dcache.demand_mshr_misses::cpu.data 4620 # number of demand (read+write) MSHR misses 828system.cpu.dcache.demand_mshr_misses::total 4620 # number of demand (read+write) MSHR misses 829system.cpu.dcache.overall_mshr_misses::cpu.data 4620 # number of overall MSHR misses 830system.cpu.dcache.overall_mshr_misses::total 4620 # number of overall MSHR misses 831system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86261000 # number of ReadReq MSHR miss cycles 832system.cpu.dcache.ReadReq_mshr_miss_latency::total 86261000 # number of ReadReq MSHR miss cycles 833system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138898000 # number of WriteReq MSHR miss cycles 834system.cpu.dcache.WriteReq_mshr_miss_latency::total 138898000 # number of WriteReq MSHR miss cycles 835system.cpu.dcache.demand_mshr_miss_latency::cpu.data 225159000 # number of demand (read+write) MSHR miss cycles 836system.cpu.dcache.demand_mshr_miss_latency::total 225159000 # number of demand (read+write) MSHR miss cycles 837system.cpu.dcache.overall_mshr_miss_latency::cpu.data 225159000 # number of overall MSHR miss cycles 838system.cpu.dcache.overall_mshr_miss_latency::total 225159000 # number of overall MSHR miss cycles | 924system.cpu.dcache.demand_mshr_hits::cpu.data 20818 # number of demand (read+write) MSHR hits 925system.cpu.dcache.demand_mshr_hits::total 20818 # number of demand (read+write) MSHR hits 926system.cpu.dcache.overall_mshr_hits::cpu.data 20818 # number of overall MSHR hits 927system.cpu.dcache.overall_mshr_hits::total 20818 # number of overall MSHR hits 928system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1772 # number of ReadReq MSHR misses 929system.cpu.dcache.ReadReq_mshr_misses::total 1772 # number of ReadReq MSHR misses 930system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2844 # number of WriteReq MSHR misses 931system.cpu.dcache.WriteReq_mshr_misses::total 2844 # number of WriteReq MSHR misses 932system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses 933system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses 934system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses 935system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses 936system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106478039 # number of ReadReq MSHR miss cycles 937system.cpu.dcache.ReadReq_mshr_miss_latency::total 106478039 # number of ReadReq MSHR miss cycles 938system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191753000 # number of WriteReq MSHR miss cycles 939system.cpu.dcache.WriteReq_mshr_miss_latency::total 191753000 # number of WriteReq MSHR miss cycles 940system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298231039 # number of demand (read+write) MSHR miss cycles 941system.cpu.dcache.demand_mshr_miss_latency::total 298231039 # number of demand (read+write) MSHR miss cycles 942system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298231039 # number of overall MSHR miss cycles 943system.cpu.dcache.overall_mshr_miss_latency::total 298231039 # number of overall MSHR miss cycles |
| 839system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses 840system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses | 944system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses 945system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses |
| 841system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses 842system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses | 946system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 947system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses |
| 843system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 844system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 845system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 846system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses | 948system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 949system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 950system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 951system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
| 847system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47816.518847 # average ReadReq mshr miss latency 848system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47816.518847 # average ReadReq mshr miss latency 849system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49324.573864 # average WriteReq mshr miss latency 850system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49324.573864 # average WriteReq mshr miss latency 851system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48735.714286 # average overall mshr miss latency 852system.cpu.dcache.demand_avg_mshr_miss_latency::total 48735.714286 # average overall mshr miss latency 853system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48735.714286 # average overall mshr miss latency 854system.cpu.dcache.overall_avg_mshr_miss_latency::total 48735.714286 # average overall mshr miss latency | 952system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60089.186795 # average ReadReq mshr miss latency 953system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60089.186795 # average ReadReq mshr miss latency 954system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67423.699015 # average WriteReq mshr miss latency 955system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67423.699015 # average WriteReq mshr miss latency 956system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency 957system.cpu.dcache.demand_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency 958system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency 959system.cpu.dcache.overall_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency |
| 855system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 856 857---------- End Simulation Statistics ---------- | 960system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 961 962---------- End Simulation Statistics ---------- |