| stats.txt (9490:e6a09d97bdc9) | stats.txt (9568:cd1351d4d850) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.068358 # Number of seconds simulated 4sim_ticks 68358106500 # Number of ticks simulated 5final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.068358 # Number of seconds simulated 4sim_ticks 68358106500 # Number of ticks simulated 5final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 148173 # Simulator instruction rate (inst/s) 8host_op_rate 189432 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37097000 # Simulator tick rate (ticks/s) 10host_mem_usage 250340 # Number of bytes of host memory used 11host_seconds 1842.69 # Real time elapsed on the host | 7host_inst_rate 161957 # Simulator instruction rate (inst/s) 8host_op_rate 207054 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40547923 # Simulator tick rate (ticks/s) 10host_mem_usage 250356 # Number of bytes of host memory used 11host_seconds 1685.86 # Real time elapsed on the host |
| 12sim_insts 273036725 # Number of instructions simulated 13sim_ops 349064449 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory 16system.physmem.bytes_read::total 465728 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 193152 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 193152 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3018 # Number of read requests responded to by this memory --- 53 unchanged lines hidden (view full) --- 73system.physmem.totGap 68358086000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 7278 # Categorize read packet sizes | 12sim_insts 273036725 # Number of instructions simulated 13sim_ops 349064449 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory 16system.physmem.bytes_read::total 465728 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 193152 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 193152 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3018 # Number of read requests responded to by this memory --- 53 unchanged lines hidden (view full) --- 73system.physmem.totGap 68358086000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 7278 # Categorize read packet sizes |
| 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 2 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 101system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 88system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see | |
| 134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 167system.physmem.totQLat 46727256 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests | 152system.physmem.totQLat 46720000 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 192175000 # Sum of mem lat for all requests |
| 169system.physmem.totBusLat 36390000 # Total cycles spent in databus access 170system.physmem.totBankLat 109065000 # Total cycles spent in bank access | 154system.physmem.totBusLat 36390000 # Total cycles spent in databus access 155system.physmem.totBankLat 109065000 # Total cycles spent in bank access |
| 171system.physmem.avgQLat 6420.34 # Average queueing delay per request | 156system.physmem.avgQLat 6419.35 # Average queueing delay per request |
| 172system.physmem.avgBankLat 14985.57 # Average bank access latency per request 173system.physmem.avgBusLat 5000.00 # Average bus latency per request | 157system.physmem.avgBankLat 14985.57 # Average bank access latency per request 158system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 174system.physmem.avgMemAccLat 26405.92 # Average memory access latency | 159system.physmem.avgMemAccLat 26404.92 # Average memory access latency |
| 175system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.05 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time --- 396 unchanged lines hidden (view full) --- 579system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18773.979853 # average ReadReq mshr miss latency 580system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18773.979853 # average ReadReq mshr miss latency 581system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency 582system.cpu.icache.demand_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency 583system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency 584system.cpu.icache.overall_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency 585system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 586system.cpu.l2cache.replacements 0 # number of replacements | 160system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 162system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 0.05 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.00 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time --- 396 unchanged lines hidden (view full) --- 564system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18773.979853 # average ReadReq mshr miss latency 565system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18773.979853 # average ReadReq mshr miss latency 566system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency 567system.cpu.icache.demand_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency 568system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency 569system.cpu.icache.overall_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency 570system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 571system.cpu.l2cache.replacements 0 # number of replacements |
| 587system.cpu.l2cache.tagsinuse 3956.608159 # Cycle average of tags in use | 572system.cpu.l2cache.tagsinuse 3956.608160 # Cycle average of tags in use |
| 588system.cpu.l2cache.total_refs 13151 # Total number of references to valid blocks. 589system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks. 590system.cpu.l2cache.avg_refs 2.436273 # Average number of references to valid blocks. 591system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 592system.cpu.l2cache.occ_blocks::writebacks 373.077110 # Average occupied blocks per requestor 593system.cpu.l2cache.occ_blocks::cpu.inst 2771.508511 # Average occupied blocks per requestor 594system.cpu.l2cache.occ_blocks::cpu.data 812.022538 # Average occupied blocks per requestor 595system.cpu.l2cache.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy --- 101 unchanged lines hidden (view full) --- 697system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2792 # number of ReadExReq MSHR misses 698system.cpu.l2cache.ReadExReq_mshr_misses::total 2792 # number of ReadExReq MSHR misses 699system.cpu.l2cache.demand_mshr_misses::cpu.inst 3019 # number of demand (read+write) MSHR misses 700system.cpu.l2cache.demand_mshr_misses::cpu.data 4259 # number of demand (read+write) MSHR misses 701system.cpu.l2cache.demand_mshr_misses::total 7278 # number of demand (read+write) MSHR misses 702system.cpu.l2cache.overall_mshr_misses::cpu.inst 3019 # number of overall MSHR misses 703system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses 704system.cpu.l2cache.overall_mshr_misses::total 7278 # number of overall MSHR misses | 573system.cpu.l2cache.total_refs 13151 # Total number of references to valid blocks. 574system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks. 575system.cpu.l2cache.avg_refs 2.436273 # Average number of references to valid blocks. 576system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 577system.cpu.l2cache.occ_blocks::writebacks 373.077110 # Average occupied blocks per requestor 578system.cpu.l2cache.occ_blocks::cpu.inst 2771.508511 # Average occupied blocks per requestor 579system.cpu.l2cache.occ_blocks::cpu.data 812.022538 # Average occupied blocks per requestor 580system.cpu.l2cache.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy --- 101 unchanged lines hidden (view full) --- 682system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2792 # number of ReadExReq MSHR misses 683system.cpu.l2cache.ReadExReq_mshr_misses::total 2792 # number of ReadExReq MSHR misses 684system.cpu.l2cache.demand_mshr_misses::cpu.inst 3019 # number of demand (read+write) MSHR misses 685system.cpu.l2cache.demand_mshr_misses::cpu.data 4259 # number of demand (read+write) MSHR misses 686system.cpu.l2cache.demand_mshr_misses::total 7278 # number of demand (read+write) MSHR misses 687system.cpu.l2cache.overall_mshr_misses::cpu.inst 3019 # number of overall MSHR misses 688system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses 689system.cpu.l2cache.overall_mshr_misses::total 7278 # number of overall MSHR misses |
| 705system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115050359 # number of ReadReq MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62984754 # number of ReadReq MSHR miss cycles 707system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178035113 # number of ReadReq MSHR miss cycles | 690system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115047807 # number of ReadReq MSHR miss cycles 691system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62983881 # number of ReadReq MSHR miss cycles 692system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178031688 # number of ReadReq MSHR miss cycles |
| 708system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 709system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles | 693system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 694system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles |
| 710system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100922692 # number of ReadExReq MSHR miss cycles 711system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100922692 # number of ReadExReq MSHR miss cycles 712system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115050359 # number of demand (read+write) MSHR miss cycles 713system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163907446 # number of demand (read+write) MSHR miss cycles 714system.cpu.l2cache.demand_mshr_miss_latency::total 278957805 # number of demand (read+write) MSHR miss cycles 715system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles 716system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles 717system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles | 695system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100921221 # number of ReadExReq MSHR miss cycles 696system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100921221 # number of ReadExReq MSHR miss cycles 697system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115047807 # number of demand (read+write) MSHR miss cycles 698system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163905102 # number of demand (read+write) MSHR miss cycles 699system.cpu.l2cache.demand_mshr_miss_latency::total 278952909 # number of demand (read+write) MSHR miss cycles 700system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115047807 # number of overall MSHR miss cycles 701system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163905102 # number of overall MSHR miss cycles 702system.cpu.l2cache.overall_mshr_miss_latency::total 278952909 # number of overall MSHR miss cycles |
| 718system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses 721system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 722system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 723system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993594 # mshr miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993594 # mshr miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for demand accesses 726system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for demand accesses 727system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940 # mshr miss rate for demand accesses 728system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses 729system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses | 703system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses 704system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses 705system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses 706system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 707system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 708system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993594 # mshr miss rate for ReadExReq accesses 709system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993594 # mshr miss rate for ReadExReq accesses 710system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for demand accesses 711system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for demand accesses 712system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940 # mshr miss rate for demand accesses 713system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses 714system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses 715system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses |
| 731system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency 732system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency 733system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency | 716system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38107.918847 # average ReadReq mshr miss latency 717system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42933.797546 # average ReadReq mshr miss latency 718system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.065091 # average ReadReq mshr miss latency |
| 734system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 735system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency | 719system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 720system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency |
| 736system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency | 721system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36146.569126 # average ReadExReq mshr miss latency 722system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36146.569126 # average ReadExReq mshr miss latency 723system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency 724system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency 725system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency 726system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency 727system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency 728system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency |
| 744system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 745system.cpu.dcache.replacements 1413 # number of replacements 746system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use 747system.cpu.dcache.total_refs 170925187 # Total number of references to valid blocks. 748system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks. 749system.cpu.dcache.avg_refs 37077.047072 # Average number of references to valid blocks. 750system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 751system.cpu.dcache.occ_blocks::cpu.data 3109.949983 # Average occupied blocks per requestor --- 121 unchanged lines hidden --- | 729system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 730system.cpu.dcache.replacements 1413 # number of replacements 731system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use 732system.cpu.dcache.total_refs 170925187 # Total number of references to valid blocks. 733system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks. 734system.cpu.dcache.avg_refs 37077.047072 # Average number of references to valid blocks. 735system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 736system.cpu.dcache.occ_blocks::cpu.data 3109.949983 # Average occupied blocks per requestor --- 121 unchanged lines hidden --- |