| stats.txt (9481:b0fa6b872f40) | stats.txt (9490:e6a09d97bdc9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.068072 # Number of seconds simulated 4sim_ticks 68071881000 # Number of ticks simulated 5final_tick 68071881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.068358 # Number of seconds simulated 4sim_ticks 68358106500 # Number of ticks simulated 5final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 102151 # Simulator instruction rate (inst/s) 8host_op_rate 130595 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25467625 # Simulator tick rate (ticks/s) 10host_mem_usage 296712 # Number of bytes of host memory used 11host_seconds 2672.88 # Real time elapsed on the host | 7host_inst_rate 148173 # Simulator instruction rate (inst/s) 8host_op_rate 189432 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37097000 # Simulator tick rate (ticks/s) 10host_mem_usage 250340 # Number of bytes of host memory used 11host_seconds 1842.69 # Real time elapsed on the host |
| 12sim_insts 273036725 # Number of instructions simulated 13sim_ops 349064449 # Number of ops (including micro ops) simulated | 12sim_insts 273036725 # Number of instructions simulated 13sim_ops 349064449 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory 16system.physmem.bytes_read::total 466240 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2846873 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 4002357 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 6849230 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2846873 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2846873 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2846873 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 4002357 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 6849230 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 7286 # Total number of read requests seen | 14system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory 16system.physmem.bytes_read::total 465728 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 193152 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 193152 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3018 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 7277 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2825590 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 3987471 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 6813062 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2825590 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2825590 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2825590 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 3987471 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 6813062 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 7278 # Total number of read requests seen |
| 31system.physmem.writeReqs 0 # Total number of write requests seen | 31system.physmem.writeReqs 0 # Total number of write requests seen |
| 32system.physmem.cpureqs 7288 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 466240 # Total number of bytes read from memory | 32system.physmem.cpureqs 7280 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 465728 # Total number of bytes read from memory |
| 34system.physmem.bytesWritten 0 # Total number of bytes written to memory | 34system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 35system.physmem.bytesConsumedRd 466240 # bytesRead derated as per pkt->getSize() | 35system.physmem.bytesConsumedRd 465728 # bytesRead derated as per pkt->getSize() |
| 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed | 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed |
| 39system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 577 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 474 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 504 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 481 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 557 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 360 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis | 39system.physmem.perBankRdReqs::0 414 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 413 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 482 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 478 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 504 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 488 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 546 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 585 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 400 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 430 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 455 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 415 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 381 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 421 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 451 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 415 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 68071860500 # Total gap between requests | 73system.physmem.totGap 68358086000 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 80system.physmem.readPktSize::6 7286 # Categorize read packet sizes | 80system.physmem.readPktSize::6 7278 # Categorize read packet sizes |
| 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes --- 4 unchanged lines hidden (view full) --- 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 2 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes --- 4 unchanged lines hidden (view full) --- 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 2 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 101system.physmem.rdQLenPdf::0 4339 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 2127 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 184 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 45 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 45 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 167system.physmem.totQLat 38841760 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 170087760 # Sum of mem lat for all requests 169system.physmem.totBusLat 29144000 # Total cycles spent in databus access 170system.physmem.totBankLat 102102000 # Total cycles spent in bank access 171system.physmem.avgQLat 5331.01 # Average queueing delay per request 172system.physmem.avgBankLat 14013.45 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 23344.46 # Average memory access latency 175system.physmem.avgRdBW 6.85 # Average achieved read bandwidth in MB/s | 167system.physmem.totQLat 46727256 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests 169system.physmem.totBusLat 36390000 # Total cycles spent in databus access 170system.physmem.totBankLat 109065000 # Total cycles spent in bank access 171system.physmem.avgQLat 6420.34 # Average queueing delay per request 172system.physmem.avgBankLat 14985.57 # Average bank access latency per request 173system.physmem.avgBusLat 5000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 26405.92 # Average memory access latency 175system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s |
| 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 177system.physmem.avgConsumedRdBW 6.85 # Average consumed read bandwidth in MB/s | 177system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s |
| 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s | 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s |
| 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.04 # Data bus utilization in percentage | 179system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.05 # Data bus utilization in percentage |
| 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time | 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 183system.physmem.readRowHits 6372 # Number of row buffer hits during reads | 183system.physmem.readRowHits 6070 # Number of row buffer hits during reads |
| 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 185system.physmem.readRowHitRate 87.46 # Row buffer hit rate for reads | 185system.physmem.readRowHitRate 83.40 # Row buffer hit rate for reads |
| 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 187system.physmem.avgGap 9342830.15 # Average gap between requests 188system.cpu.branchPred.lookups 41692065 # Number of BP lookups 189system.cpu.branchPred.condPredicted 21046025 # Number of conditional branches predicted 190system.cpu.branchPred.condIncorrect 1612310 # Number of conditional branches incorrect 191system.cpu.branchPred.BTBLookups 25558633 # Number of BTB lookups 192system.cpu.branchPred.BTBHits 16675018 # Number of BTB hits | 187system.physmem.avgGap 9392427.32 # Average gap between requests 188system.cpu.branchPred.lookups 41732744 # Number of BP lookups 189system.cpu.branchPred.condPredicted 21038238 # Number of conditional branches predicted 190system.cpu.branchPred.condIncorrect 1652729 # Number of conditional branches incorrect 191system.cpu.branchPred.BTBLookups 26040996 # Number of BTB lookups 192system.cpu.branchPred.BTBHits 16764116 # Number of BTB hits |
| 193system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 193system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 194system.cpu.branchPred.BTBHitPct 65.242214 # BTB Hit Percentage 195system.cpu.branchPred.usedRAS 6736046 # Number of times the RAS was used to get a target. 196system.cpu.branchPred.RASInCorrect 7190 # Number of incorrect RAS predictions. | 194system.cpu.branchPred.BTBHitPct 64.375863 # BTB Hit Percentage 195system.cpu.branchPred.usedRAS 6744035 # Number of times the RAS was used to get a target. 196system.cpu.branchPred.RASInCorrect 7274 # Number of incorrect RAS predictions. |
| 197system.cpu.dtb.inst_hits 0 # ITB inst hits 198system.cpu.dtb.inst_misses 0 # ITB inst misses 199system.cpu.dtb.read_hits 0 # DTB read hits 200system.cpu.dtb.read_misses 0 # DTB read misses 201system.cpu.dtb.write_hits 0 # DTB write hits 202system.cpu.dtb.write_misses 0 # DTB write misses 203system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 204system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 232system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 233system.cpu.itb.read_accesses 0 # DTB read accesses 234system.cpu.itb.write_accesses 0 # DTB write accesses 235system.cpu.itb.inst_accesses 0 # ITB inst accesses 236system.cpu.itb.hits 0 # DTB hits 237system.cpu.itb.misses 0 # DTB misses 238system.cpu.itb.accesses 0 # DTB accesses 239system.cpu.workload.num_syscalls 191 # Number of system calls | 197system.cpu.dtb.inst_hits 0 # ITB inst hits 198system.cpu.dtb.inst_misses 0 # ITB inst misses 199system.cpu.dtb.read_hits 0 # DTB read hits 200system.cpu.dtb.read_misses 0 # DTB read misses 201system.cpu.dtb.write_hits 0 # DTB write hits 202system.cpu.dtb.write_misses 0 # DTB write misses 203system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 204system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 232system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 233system.cpu.itb.read_accesses 0 # DTB read accesses 234system.cpu.itb.write_accesses 0 # DTB write accesses 235system.cpu.itb.inst_accesses 0 # ITB inst accesses 236system.cpu.itb.hits 0 # DTB hits 237system.cpu.itb.misses 0 # DTB misses 238system.cpu.itb.accesses 0 # DTB accesses 239system.cpu.workload.num_syscalls 191 # Number of system calls |
| 240system.cpu.numCycles 136143763 # number of cpu cycles simulated | 240system.cpu.numCycles 136716214 # number of cpu cycles simulated |
| 241system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 242system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 241system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 242system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 243system.cpu.fetch.icacheStallCycles 38720751 # Number of cycles fetch is stalled on an Icache miss 244system.cpu.fetch.Insts 316654874 # Number of instructions fetch has processed 245system.cpu.fetch.Branches 41692065 # Number of branches that fetch encountered 246system.cpu.fetch.predictedBranches 23411064 # Number of branches that fetch has predicted taken 247system.cpu.fetch.Cycles 70618145 # Number of cycles fetch has run and was not squashing or blocked 248system.cpu.fetch.SquashCycles 6665842 # Number of cycles fetch has spent squashing 249system.cpu.fetch.BlockedCycles 21550456 # Number of cycles fetch has spent blocked 250system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 251system.cpu.fetch.PendingTrapStallCycles 1364 # Number of stall cycles due to pending traps | 243system.cpu.fetch.icacheStallCycles 38933938 # Number of cycles fetch is stalled on an Icache miss 244system.cpu.fetch.Insts 317883912 # Number of instructions fetch has processed 245system.cpu.fetch.Branches 41732744 # Number of branches that fetch encountered 246system.cpu.fetch.predictedBranches 23508151 # Number of branches that fetch has predicted taken 247system.cpu.fetch.Cycles 70884226 # Number of cycles fetch has run and was not squashing or blocked 248system.cpu.fetch.SquashCycles 6817030 # Number of cycles fetch has spent squashing 249system.cpu.fetch.BlockedCycles 21520624 # Number of cycles fetch has spent blocked 250system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 251system.cpu.fetch.PendingTrapStallCycles 1371 # Number of stall cycles due to pending traps |
| 252system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR | 252system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR |
| 253system.cpu.fetch.CacheLines 37376595 # Number of cache lines fetched 254system.cpu.fetch.IcacheSquashes 521732 # Number of outstanding Icache misses that were squashed 255system.cpu.fetch.rateDist::samples 135933121 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::mean 2.990728 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::stdev 3.456678 # Number of instructions fetched each cycle (Total) | 253system.cpu.fetch.CacheLines 37551869 # Number of cache lines fetched 254system.cpu.fetch.IcacheSquashes 523991 # Number of outstanding Icache misses that were squashed 255system.cpu.fetch.rateDist::samples 136493185 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::mean 2.988959 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::stdev 3.456313 # Number of instructions fetched each cycle (Total) |
| 258system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 258system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 259system.cpu.fetch.rateDist::0 65940392 48.51% 48.51% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::1 6730475 4.95% 53.46% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::2 5637804 4.15% 57.61% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::3 5998950 4.41% 62.02% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::4 4879102 3.59% 65.61% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::5 4141679 3.05% 68.66% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::6 3188425 2.35% 71.00% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::7 4149669 3.05% 74.06% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::8 35266625 25.94% 100.00% # Number of instructions fetched each cycle (Total) | 259system.cpu.fetch.rateDist::0 66238954 48.53% 48.53% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::1 6780831 4.97% 53.50% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::2 5636861 4.13% 57.63% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::3 6036296 4.42% 62.05% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::4 4884969 3.58% 65.63% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::5 4157247 3.05% 68.67% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::6 3216539 2.36% 71.03% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::7 4148137 3.04% 74.07% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::8 35393351 25.93% 100.00% # Number of instructions fetched each cycle (Total) |
| 268system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 268system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 271system.cpu.fetch.rateDist::total 135933121 # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.branchRate 0.306236 # Number of branch fetches per cycle 273system.cpu.fetch.rate 2.325886 # Number of inst fetches per cycle 274system.cpu.decode.IdleCycles 45271721 # Number of cycles decode is idle 275system.cpu.decode.BlockedCycles 16691056 # Number of cycles decode is blocked 276system.cpu.decode.RunCycles 66469199 # Number of cycles decode is running 277system.cpu.decode.UnblockCycles 2527476 # Number of cycles decode is unblocking 278system.cpu.decode.SquashCycles 4973669 # Number of cycles decode is squashing 279system.cpu.decode.BranchResolved 7265289 # Number of times decode resolved a branch 280system.cpu.decode.BranchMispred 69057 # Number of times decode detected a branch misprediction 281system.cpu.decode.DecodedInsts 400237870 # Number of instructions handled by decode 282system.cpu.decode.SquashedInsts 218381 # Number of squashed instructions handled by decode 283system.cpu.rename.SquashCycles 4973669 # Number of cycles rename is squashing 284system.cpu.rename.IdleCycles 50782794 # Number of cycles rename is idle 285system.cpu.rename.BlockCycles 1926905 # Number of cycles rename is blocking 286system.cpu.rename.serializeStallCycles 308736 # count of cycles rename stalled for serializing inst 287system.cpu.rename.RunCycles 63418534 # Number of cycles rename is running 288system.cpu.rename.UnblockCycles 14522483 # Number of cycles rename is unblocking 289system.cpu.rename.RenamedInsts 392567341 # Number of instructions processed by rename 290system.cpu.rename.ROBFullEvents 52 # Number of times rename has blocked due to ROB full 291system.cpu.rename.IQFullEvents 1667501 # Number of times rename has blocked due to IQ full 292system.cpu.rename.LSQFullEvents 10227766 # Number of times rename has blocked due to LSQ full 293system.cpu.rename.FullRegisterEvents 1022 # Number of times there has been no free registers 294system.cpu.rename.RenamedOperands 431145358 # Number of destination operands rename has renamed 295system.cpu.rename.RenameLookups 2325492453 # Number of register rename lookups that rename has made 296system.cpu.rename.int_rename_lookups 1253893551 # Number of integer rename lookups 297system.cpu.rename.fp_rename_lookups 1071598902 # Number of floating rename lookups | 271system.cpu.fetch.rateDist::total 136493185 # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.branchRate 0.305251 # Number of branch fetches per cycle 273system.cpu.fetch.rate 2.325137 # Number of inst fetches per cycle 274system.cpu.decode.IdleCycles 45460656 # Number of cycles decode is idle 275system.cpu.decode.BlockedCycles 16697353 # Number of cycles decode is blocked 276system.cpu.decode.RunCycles 66694244 # Number of cycles decode is running 277system.cpu.decode.UnblockCycles 2556726 # Number of cycles decode is unblocking 278system.cpu.decode.SquashCycles 5084206 # Number of cycles decode is squashing 279system.cpu.decode.BranchResolved 7272433 # Number of times decode resolved a branch 280system.cpu.decode.BranchMispred 69135 # Number of times decode detected a branch misprediction 281system.cpu.decode.DecodedInsts 401643990 # Number of instructions handled by decode 282system.cpu.decode.SquashedInsts 218444 # Number of squashed instructions handled by decode 283system.cpu.rename.SquashCycles 5084206 # Number of cycles rename is squashing 284system.cpu.rename.IdleCycles 50968262 # Number of cycles rename is idle 285system.cpu.rename.BlockCycles 1914523 # Number of cycles rename is blocking 286system.cpu.rename.serializeStallCycles 308341 # count of cycles rename stalled for serializing inst 287system.cpu.rename.RunCycles 63676495 # Number of cycles rename is running 288system.cpu.rename.UnblockCycles 14541358 # Number of cycles rename is unblocking 289system.cpu.rename.RenamedInsts 393775984 # Number of instructions processed by rename 290system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full 291system.cpu.rename.IQFullEvents 1667283 # Number of times rename has blocked due to IQ full 292system.cpu.rename.LSQFullEvents 10312278 # Number of times rename has blocked due to LSQ full 293system.cpu.rename.FullRegisterEvents 1126 # Number of times there has been no free registers 294system.cpu.rename.RenamedOperands 432122953 # Number of destination operands rename has renamed 295system.cpu.rename.RenameLookups 2331950900 # Number of register rename lookups that rename has made 296system.cpu.rename.int_rename_lookups 1259654779 # Number of integer rename lookups 297system.cpu.rename.fp_rename_lookups 1072296121 # Number of floating rename lookups |
| 298system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed | 298system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed |
| 299system.cpu.rename.UndoneMaps 46579165 # Number of HB maps that are undone due to squashing 300system.cpu.rename.serializingInsts 11899 # count of serializing insts renamed 301system.cpu.rename.tempSerializingInsts 11898 # count of temporary serializing insts renamed 302system.cpu.rename.skidInsts 36419091 # count of insts added to the skid buffer 303system.cpu.memDep0.insertedLoads 103284417 # Number of loads inserted to the mem dependence unit. 304system.cpu.memDep0.insertedStores 91190896 # Number of stores inserted to the mem dependence unit. 305system.cpu.memDep0.conflictingLoads 4278404 # Number of conflicting loads. 306system.cpu.memDep0.conflictingStores 5313371 # Number of conflicting stores. 307system.cpu.iq.iqInstsAdded 383399978 # Number of instructions added to the IQ (excludes non-spec) 308system.cpu.iq.iqNonSpecInstsAdded 22859 # Number of non-speculative instructions added to the IQ 309system.cpu.iq.iqInstsIssued 373603209 # Number of instructions issued 310system.cpu.iq.iqSquashedInstsIssued 1225399 # Number of squashed instructions issued 311system.cpu.iq.iqSquashedInstsExamined 33612220 # Number of squashed instructions iterated over during squash; mainly for profiling 312system.cpu.iq.iqSquashedOperandsExamined 83720105 # Number of squashed operands that are examined and possibly removed from graph 313system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed 314system.cpu.iq.issued_per_cycle::samples 135933121 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::mean 2.748434 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::stdev 2.022451 # Number of insts issued each cycle | 299system.cpu.rename.UndoneMaps 47556760 # Number of HB maps that are undone due to squashing 300system.cpu.rename.serializingInsts 11781 # count of serializing insts renamed 301system.cpu.rename.tempSerializingInsts 11780 # count of temporary serializing insts renamed 302system.cpu.rename.skidInsts 36361756 # count of insts added to the skid buffer 303system.cpu.memDep0.insertedLoads 103536184 # Number of loads inserted to the mem dependence unit. 304system.cpu.memDep0.insertedStores 91503384 # Number of stores inserted to the mem dependence unit. 305system.cpu.memDep0.conflictingLoads 4302647 # Number of conflicting loads. 306system.cpu.memDep0.conflictingStores 5369286 # Number of conflicting stores. 307system.cpu.iq.iqInstsAdded 384225176 # Number of instructions added to the IQ (excludes non-spec) 308system.cpu.iq.iqNonSpecInstsAdded 22747 # Number of non-speculative instructions added to the IQ 309system.cpu.iq.iqInstsIssued 374106691 # Number of instructions issued 310system.cpu.iq.iqSquashedInstsIssued 1237893 # Number of squashed instructions issued 311system.cpu.iq.iqSquashedInstsExamined 34434852 # Number of squashed instructions iterated over during squash; mainly for profiling 312system.cpu.iq.iqSquashedOperandsExamined 85933398 # Number of squashed operands that are examined and possibly removed from graph 313system.cpu.iq.iqSquashedNonSpecRemoved 627 # Number of squashed non-spec instructions that were removed 314system.cpu.iq.issued_per_cycle::samples 136493185 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::mean 2.740845 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::stdev 2.023746 # Number of insts issued each cycle |
| 317system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 317system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 318system.cpu.iq.issued_per_cycle::0 24617806 18.11% 18.11% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::1 19905628 14.64% 32.75% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::2 20463769 15.05% 47.81% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::3 18134866 13.34% 61.15% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::4 23975475 17.64% 78.79% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::5 15748338 11.59% 90.37% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::6 8799560 6.47% 96.85% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::7 3376937 2.48% 99.33% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::8 910742 0.67% 100.00% # Number of insts issued each cycle | 318system.cpu.iq.issued_per_cycle::0 24947846 18.28% 18.28% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::1 19979954 14.64% 32.92% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::2 20599928 15.09% 48.01% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::3 18110176 13.27% 61.28% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::4 23967090 17.56% 78.84% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::5 15779150 11.56% 90.40% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::6 8840932 6.48% 96.87% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::7 3358221 2.46% 99.33% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::8 909888 0.67% 100.00% # Number of insts issued each cycle |
| 327system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 327system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 330system.cpu.iq.issued_per_cycle::total 135933121 # Number of insts issued each cycle | 330system.cpu.iq.issued_per_cycle::total 136493185 # Number of insts issued each cycle |
| 331system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 331system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 332system.cpu.iq.fu_full::IntAlu 9041 0.05% 0.05% # attempts to use FU when none available 333system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available | 332system.cpu.iq.fu_full::IntAlu 8903 0.05% 0.05% # attempts to use FU when none available 333system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available |
| 334system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available 339system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available | 334system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available 339system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available |
| 352system.cpu.iq.fu_full::SimdFloatAdd 46127 0.26% 0.34% # attempts to use FU when none available | 352system.cpu.iq.fu_full::SimdFloatAdd 46069 0.26% 0.34% # attempts to use FU when none available |
| 353system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available | 353system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available |
| 354system.cpu.iq.fu_full::SimdFloatCmp 7573 0.04% 0.38% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatCvt 401 0.00% 0.38% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatMisc 189986 1.07% 1.45% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatMult 6027 0.03% 1.49% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatMultAcc 241589 1.36% 2.85% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available 361system.cpu.iq.fu_full::MemRead 9303270 52.42% 55.26% # attempts to use FU when none available 362system.cpu.iq.fu_full::MemWrite 7940124 44.74% 100.00% # attempts to use FU when none available | 354system.cpu.iq.fu_full::SimdFloatCmp 7541 0.04% 0.38% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatCvt 384 0.00% 0.38% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatMisc 189821 1.07% 1.45% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatMult 6023 0.03% 1.48% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatMultAcc 241770 1.36% 2.84% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available 361system.cpu.iq.fu_full::MemRead 9327128 52.38% 55.21% # attempts to use FU when none available 362system.cpu.iq.fu_full::MemWrite 7975640 44.79% 100.00% # attempts to use FU when none available |
| 363system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 364system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 365system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 363system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 364system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 365system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 366system.cpu.iq.FU_type_0::IntAlu 126062452 33.74% 33.74% # Type of FU issued 367system.cpu.iq.FU_type_0::IntMult 2174186 0.58% 34.32% # Type of FU issued 368system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued 369system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued 370system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued 371system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.32% # Type of FU issued 372system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.32% # Type of FU issued 373system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.32% # Type of FU issued 374system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.32% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.32% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.32% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.32% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.32% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.32% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.32% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.32% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.32% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatAdd 6778330 1.81% 36.14% # Type of FU issued | 366system.cpu.iq.FU_type_0::IntAlu 126244558 33.75% 33.75% # Type of FU issued 367system.cpu.iq.FU_type_0::IntMult 2174203 0.58% 34.33% # Type of FU issued 368system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.33% # Type of FU issued 369system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.33% # Type of FU issued 370system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.33% # Type of FU issued 371system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.33% # Type of FU issued 372system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.33% # Type of FU issued 373system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.33% # Type of FU issued 374system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.33% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.33% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.33% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.33% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.33% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.33% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.33% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.33% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.33% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.33% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.33% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.33% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatAdd 6782034 1.81% 36.14% # Type of FU issued |
| 387system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.14% # Type of FU issued | 387system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.14% # Type of FU issued |
| 388system.cpu.iq.FU_type_0::SimdFloatCmp 8468082 2.27% 38.41% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdFloatCvt 3426363 0.92% 39.32% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatDiv 1600385 0.43% 39.75% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatMisc 20905129 5.60% 45.35% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatMult 7170133 1.92% 47.27% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133112 1.91% 49.17% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatSqrt 175289 0.05% 49.22% # Type of FU issued 395system.cpu.iq.FU_type_0::MemRead 101416985 27.15% 76.37% # Type of FU issued 396system.cpu.iq.FU_type_0::MemWrite 88292763 23.63% 100.00% # Type of FU issued | 388system.cpu.iq.FU_type_0::SimdFloatCmp 8468832 2.26% 38.40% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdFloatCvt 3426641 0.92% 39.32% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatDiv 1600511 0.43% 39.75% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatMisc 20905751 5.59% 45.34% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatMult 7170121 1.92% 47.25% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133236 1.91% 49.16% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.21% # Type of FU issued 395system.cpu.iq.FU_type_0::MemRead 101536664 27.14% 76.35% # Type of FU issued 396system.cpu.iq.FU_type_0::MemWrite 88488853 23.65% 100.00% # Type of FU issued |
| 397system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 398system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 397system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 398system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 399system.cpu.iq.FU_type_0::total 373603209 # Type of FU issued 400system.cpu.iq.rate 2.744182 # Inst issue rate 401system.cpu.iq.fu_busy_cnt 17748829 # FU busy when requested 402system.cpu.iq.fu_busy_rate 0.047507 # FU busy rate (busy events/executed inst) 403system.cpu.iq.int_inst_queue_reads 652552700 # Number of integer instruction queue reads 404system.cpu.iq.int_inst_queue_writes 286781782 # Number of integer instruction queue writes 405system.cpu.iq.int_inst_queue_wakeup_accesses 249670215 # Number of integer instruction queue wakeup accesses 406system.cpu.iq.fp_inst_queue_reads 249561067 # Number of floating instruction queue reads 407system.cpu.iq.fp_inst_queue_writes 130267469 # Number of floating instruction queue writes 408system.cpu.iq.fp_inst_queue_wakeup_accesses 118091463 # Number of floating instruction queue wakeup accesses 409system.cpu.iq.int_alu_accesses 262665125 # Number of integer alu accesses 410system.cpu.iq.fp_alu_accesses 128686913 # Number of floating point alu accesses 411system.cpu.iew.lsq.thread0.forwLoads 11143467 # Number of loads that had data forwarded from stores | 399system.cpu.iq.FU_type_0::total 374106691 # Type of FU issued 400system.cpu.iq.rate 2.736374 # Inst issue rate 401system.cpu.iq.fu_busy_cnt 17807974 # FU busy when requested 402system.cpu.iq.fu_busy_rate 0.047601 # FU busy rate (busy events/executed inst) 403system.cpu.iq.int_inst_queue_reads 654078451 # Number of integer instruction queue reads 404system.cpu.iq.int_inst_queue_writes 288293032 # Number of integer instruction queue writes 405system.cpu.iq.int_inst_queue_wakeup_accesses 250000264 # Number of integer instruction queue wakeup accesses 406system.cpu.iq.fp_inst_queue_reads 249673983 # Number of floating instruction queue reads 407system.cpu.iq.fp_inst_queue_writes 130403978 # Number of floating instruction queue writes 408system.cpu.iq.fp_inst_queue_wakeup_accesses 118157993 # Number of floating instruction queue wakeup accesses 409system.cpu.iq.int_alu_accesses 263169120 # Number of integer alu accesses 410system.cpu.iq.fp_alu_accesses 128745545 # Number of floating point alu accesses 411system.cpu.iew.lsq.thread0.forwLoads 11104268 # Number of loads that had data forwarded from stores |
| 412system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 412system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 413system.cpu.iew.lsq.thread0.squashedLoads 8635669 # Number of loads squashed 414system.cpu.iew.lsq.thread0.ignoredResponses 113833 # Number of memory responses ignored because the instruction is squashed 415system.cpu.iew.lsq.thread0.memOrderViolation 14304 # Number of memory ordering violations 416system.cpu.iew.lsq.thread0.squashedStores 8815313 # Number of stores squashed | 413system.cpu.iew.lsq.thread0.squashedLoads 8887436 # Number of loads squashed 414system.cpu.iew.lsq.thread0.ignoredResponses 113793 # Number of memory responses ignored because the instruction is squashed 415system.cpu.iew.lsq.thread0.memOrderViolation 14364 # Number of memory ordering violations 416system.cpu.iew.lsq.thread0.squashedStores 9127801 # Number of stores squashed |
| 417system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 418system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 417system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 418system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 419system.cpu.iew.lsq.thread0.rescheduledLoads 179767 # Number of loads that were rescheduled 420system.cpu.iew.lsq.thread0.cacheBlocked 1150 # Number of times an access to memory failed due to the cache being blocked | 419system.cpu.iew.lsq.thread0.rescheduledLoads 171663 # Number of loads that were rescheduled 420system.cpu.iew.lsq.thread0.cacheBlocked 1472 # Number of times an access to memory failed due to the cache being blocked |
| 421system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 421system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 422system.cpu.iew.iewSquashCycles 4973669 # Number of cycles IEW is squashing 423system.cpu.iew.iewBlockCycles 290169 # Number of cycles IEW is blocking 424system.cpu.iew.iewUnblockCycles 43007 # Number of cycles IEW is unblocking 425system.cpu.iew.iewDispatchedInsts 383424336 # Number of instructions dispatched to IQ 426system.cpu.iew.iewDispSquashedInsts 947805 # Number of squashed instructions skipped by dispatch 427system.cpu.iew.iewDispLoadInsts 103284417 # Number of dispatched load instructions 428system.cpu.iew.iewDispStoreInsts 91190896 # Number of dispatched store instructions 429system.cpu.iew.iewDispNonSpecInsts 11825 # Number of dispatched non-speculative instructions 430system.cpu.iew.iewIQFullEvents 324 # Number of times the IQ has become full, causing a stall 431system.cpu.iew.iewLSQFullEvents 376 # Number of times the LSQ has become full, causing a stall 432system.cpu.iew.memOrderViolationEvents 14304 # Number of memory order violations 433system.cpu.iew.predictedTakenIncorrect 1257323 # Number of branches that were predicted taken incorrectly 434system.cpu.iew.predictedNotTakenIncorrect 355165 # Number of branches that were predicted not taken incorrectly 435system.cpu.iew.branchMispredicts 1612488 # Number of branch mispredicts detected at execute 436system.cpu.iew.iewExecutedInsts 369752091 # Number of executed instructions 437system.cpu.iew.iewExecLoadInsts 100205261 # Number of load instructions executed 438system.cpu.iew.iewExecSquashedInsts 3851118 # Number of squashed instructions skipped in execute | 422system.cpu.iew.iewSquashCycles 5084206 # Number of cycles IEW is squashing 423system.cpu.iew.iewBlockCycles 279212 # Number of cycles IEW is blocking 424system.cpu.iew.iewUnblockCycles 42812 # Number of cycles IEW is unblocking 425system.cpu.iew.iewDispatchedInsts 384249465 # Number of instructions dispatched to IQ 426system.cpu.iew.iewDispSquashedInsts 945099 # Number of squashed instructions skipped by dispatch 427system.cpu.iew.iewDispLoadInsts 103536184 # Number of dispatched load instructions 428system.cpu.iew.iewDispStoreInsts 91503384 # Number of dispatched store instructions 429system.cpu.iew.iewDispNonSpecInsts 11713 # Number of dispatched non-speculative instructions 430system.cpu.iew.iewIQFullEvents 308 # Number of times the IQ has become full, causing a stall 431system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall 432system.cpu.iew.memOrderViolationEvents 14364 # Number of memory order violations 433system.cpu.iew.predictedTakenIncorrect 1301821 # Number of branches that were predicted taken incorrectly 434system.cpu.iew.predictedNotTakenIncorrect 354554 # Number of branches that were predicted not taken incorrectly 435system.cpu.iew.branchMispredicts 1656375 # Number of branch mispredicts detected at execute 436system.cpu.iew.iewExecutedInsts 370204175 # Number of executed instructions 437system.cpu.iew.iewExecLoadInsts 100335709 # Number of load instructions executed 438system.cpu.iew.iewExecSquashedInsts 3902516 # Number of squashed instructions skipped in execute |
| 439system.cpu.iew.exec_swp 0 # number of swp insts executed | 439system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 440system.cpu.iew.exec_nop 1499 # number of nop insts executed 441system.cpu.iew.exec_refs 187415465 # number of memory reference insts executed 442system.cpu.iew.exec_branches 38269539 # Number of branches executed 443system.cpu.iew.exec_stores 87210204 # Number of stores executed 444system.cpu.iew.exec_rate 2.715894 # Inst execution rate 445system.cpu.iew.wb_sent 368418252 # cumulative count of insts sent to commit 446system.cpu.iew.wb_count 367761678 # cumulative count of insts written-back 447system.cpu.iew.wb_producers 182872307 # num instructions producing a value 448system.cpu.iew.wb_consumers 363527613 # num instructions consuming a value | 440system.cpu.iew.exec_nop 1542 # number of nop insts executed 441system.cpu.iew.exec_refs 187704225 # number of memory reference insts executed 442system.cpu.iew.exec_branches 38278467 # Number of branches executed 443system.cpu.iew.exec_stores 87368516 # Number of stores executed 444system.cpu.iew.exec_rate 2.707829 # Inst execution rate 445system.cpu.iew.wb_sent 368827623 # cumulative count of insts sent to commit 446system.cpu.iew.wb_count 368158257 # cumulative count of insts written-back 447system.cpu.iew.wb_producers 183056844 # num instructions producing a value 448system.cpu.iew.wb_consumers 364050324 # num instructions consuming a value |
| 449system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 449system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 450system.cpu.iew.wb_rate 2.701275 # insts written-back per cycle 451system.cpu.iew.wb_fanout 0.503049 # average fanout of values written-back | 450system.cpu.iew.wb_rate 2.692865 # insts written-back per cycle 451system.cpu.iew.wb_fanout 0.502834 # average fanout of values written-back |
| 452system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 452system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 453system.cpu.commit.commitSquashedInsts 34359338 # The number of squashed insts skipped by commit | 453system.cpu.commit.commitSquashedInsts 35184491 # The number of squashed insts skipped by commit |
| 454system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards | 454system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards |
| 455system.cpu.commit.branchMispredicts 1543637 # The number of times a branch was mispredicted 456system.cpu.commit.committed_per_cycle::samples 130959452 # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::mean 2.665444 # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::stdev 2.660816 # Number of insts commited each cycle | 455system.cpu.commit.branchMispredicts 1583973 # The number of times a branch was mispredicted 456system.cpu.commit.committed_per_cycle::samples 131408979 # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::mean 2.656326 # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::stdev 2.660791 # Number of insts commited each cycle |
| 459system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 459system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 460system.cpu.commit.committed_per_cycle::0 34245793 26.15% 26.15% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::1 28403736 21.69% 47.84% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::2 13297993 10.15% 57.99% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::3 11400251 8.71% 66.70% # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::4 13789663 10.53% 77.23% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::5 7417902 5.66% 82.89% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::6 3851196 2.94% 85.83% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::7 3914096 2.99% 88.82% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::8 14638822 11.18% 100.00% # Number of insts commited each cycle | 460system.cpu.commit.committed_per_cycle::0 34626776 26.35% 26.35% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::1 28501850 21.69% 48.04% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::2 13315357 10.13% 58.17% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::3 11364955 8.65% 66.82% # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::4 13794993 10.50% 77.32% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::5 7395322 5.63% 82.95% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::6 3829564 2.91% 85.86% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::7 3937630 3.00% 88.86% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::8 14642532 11.14% 100.00% # Number of insts commited each cycle |
| 469system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 469system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 472system.cpu.commit.committed_per_cycle::total 130959452 # Number of insts commited each cycle | 472system.cpu.commit.committed_per_cycle::total 131408979 # Number of insts commited each cycle |
| 473system.cpu.commit.committedInsts 273037337 # Number of instructions committed 474system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed 475system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 476system.cpu.commit.refs 177024331 # Number of memory references committed 477system.cpu.commit.loads 94648748 # Number of loads committed 478system.cpu.commit.membars 11033 # Number of memory barriers committed 479system.cpu.commit.branches 36546710 # Number of branches committed 480system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 481system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. 482system.cpu.commit.function_calls 6225112 # Number of function calls committed. | 473system.cpu.commit.committedInsts 273037337 # Number of instructions committed 474system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed 475system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 476system.cpu.commit.refs 177024331 # Number of memory references committed 477system.cpu.commit.loads 94648748 # Number of loads committed 478system.cpu.commit.membars 11033 # Number of memory barriers committed 479system.cpu.commit.branches 36546710 # Number of branches committed 480system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 481system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. 482system.cpu.commit.function_calls 6225112 # Number of function calls committed. |
| 483system.cpu.commit.bw_lim_events 14638822 # number cycles where commit BW limit reached | 483system.cpu.commit.bw_lim_events 14642532 # number cycles where commit BW limit reached |
| 484system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 484system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 485system.cpu.rob.rob_reads 499742506 # The number of ROB reads 486system.cpu.rob.rob_writes 771826211 # The number of ROB writes 487system.cpu.timesIdled 6299 # Number of times that the entire CPU went into an idle state and unscheduled itself 488system.cpu.idleCycles 210642 # Total number of cycles that the CPU has spent unscheduled due to idling | 485system.cpu.rob.rob_reads 501013476 # The number of ROB reads 486system.cpu.rob.rob_writes 773587232 # The number of ROB writes 487system.cpu.timesIdled 6387 # Number of times that the entire CPU went into an idle state and unscheduled itself 488system.cpu.idleCycles 223029 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 489system.cpu.committedInsts 273036725 # Number of Instructions Simulated 490system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated 491system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated | 489system.cpu.committedInsts 273036725 # Number of Instructions Simulated 490system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated 491system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated |
| 492system.cpu.cpi 0.498628 # CPI: Cycles Per Instruction 493system.cpu.cpi_total 0.498628 # CPI: Total CPI of All Threads 494system.cpu.ipc 2.005503 # IPC: Instructions Per Cycle 495system.cpu.ipc_total 2.005503 # IPC: Total IPC of All Threads 496system.cpu.int_regfile_reads 1767787991 # number of integer regfile reads 497system.cpu.int_regfile_writes 232574551 # number of integer regfile writes 498system.cpu.fp_regfile_reads 188239368 # number of floating regfile reads 499system.cpu.fp_regfile_writes 132566541 # number of floating regfile writes 500system.cpu.misc_regfile_reads 566998882 # number of misc regfile reads | 492system.cpu.cpi 0.500725 # CPI: Cycles Per Instruction 493system.cpu.cpi_total 0.500725 # CPI: Total CPI of All Threads 494system.cpu.ipc 1.997106 # IPC: Instructions Per Cycle 495system.cpu.ipc_total 1.997106 # IPC: Total IPC of All Threads 496system.cpu.int_regfile_reads 1769939132 # number of integer regfile reads 497system.cpu.int_regfile_writes 232882500 # number of integer regfile writes 498system.cpu.fp_regfile_reads 188356577 # number of floating regfile reads 499system.cpu.fp_regfile_writes 132592082 # number of floating regfile writes 500system.cpu.misc_regfile_reads 567391435 # number of misc regfile reads |
| 501system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes | 501system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes |
| 502system.cpu.icache.replacements 13918 # number of replacements 503system.cpu.icache.tagsinuse 1846.260886 # Cycle average of tags in use 504system.cpu.icache.total_refs 37359528 # Total number of references to valid blocks. 505system.cpu.icache.sampled_refs 15804 # Sample count of references to valid blocks. 506system.cpu.icache.avg_refs 2363.928626 # Average number of references to valid blocks. | 502system.cpu.icache.replacements 13893 # number of replacements 503system.cpu.icache.tagsinuse 1849.968594 # Cycle average of tags in use 504system.cpu.icache.total_refs 37534809 # Total number of references to valid blocks. 505system.cpu.icache.sampled_refs 15782 # Sample count of references to valid blocks. 506system.cpu.icache.avg_refs 2378.330313 # Average number of references to valid blocks. |
| 507system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 507system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 508system.cpu.icache.occ_blocks::cpu.inst 1846.260886 # Average occupied blocks per requestor 509system.cpu.icache.occ_percent::cpu.inst 0.901495 # Average percentage of cache occupancy 510system.cpu.icache.occ_percent::total 0.901495 # Average percentage of cache occupancy 511system.cpu.icache.ReadReq_hits::cpu.inst 37359528 # number of ReadReq hits 512system.cpu.icache.ReadReq_hits::total 37359528 # number of ReadReq hits 513system.cpu.icache.demand_hits::cpu.inst 37359528 # number of demand (read+write) hits 514system.cpu.icache.demand_hits::total 37359528 # number of demand (read+write) hits 515system.cpu.icache.overall_hits::cpu.inst 37359528 # number of overall hits 516system.cpu.icache.overall_hits::total 37359528 # number of overall hits 517system.cpu.icache.ReadReq_misses::cpu.inst 17066 # number of ReadReq misses 518system.cpu.icache.ReadReq_misses::total 17066 # number of ReadReq misses 519system.cpu.icache.demand_misses::cpu.inst 17066 # number of demand (read+write) misses 520system.cpu.icache.demand_misses::total 17066 # number of demand (read+write) misses 521system.cpu.icache.overall_misses::cpu.inst 17066 # number of overall misses 522system.cpu.icache.overall_misses::total 17066 # number of overall misses 523system.cpu.icache.ReadReq_miss_latency::cpu.inst 359194498 # number of ReadReq miss cycles 524system.cpu.icache.ReadReq_miss_latency::total 359194498 # number of ReadReq miss cycles 525system.cpu.icache.demand_miss_latency::cpu.inst 359194498 # number of demand (read+write) miss cycles 526system.cpu.icache.demand_miss_latency::total 359194498 # number of demand (read+write) miss cycles 527system.cpu.icache.overall_miss_latency::cpu.inst 359194498 # number of overall miss cycles 528system.cpu.icache.overall_miss_latency::total 359194498 # number of overall miss cycles 529system.cpu.icache.ReadReq_accesses::cpu.inst 37376594 # number of ReadReq accesses(hits+misses) 530system.cpu.icache.ReadReq_accesses::total 37376594 # number of ReadReq accesses(hits+misses) 531system.cpu.icache.demand_accesses::cpu.inst 37376594 # number of demand (read+write) accesses 532system.cpu.icache.demand_accesses::total 37376594 # number of demand (read+write) accesses 533system.cpu.icache.overall_accesses::cpu.inst 37376594 # number of overall (read+write) accesses 534system.cpu.icache.overall_accesses::total 37376594 # number of overall (read+write) accesses 535system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000457 # miss rate for ReadReq accesses 536system.cpu.icache.ReadReq_miss_rate::total 0.000457 # miss rate for ReadReq accesses 537system.cpu.icache.demand_miss_rate::cpu.inst 0.000457 # miss rate for demand accesses 538system.cpu.icache.demand_miss_rate::total 0.000457 # miss rate for demand accesses 539system.cpu.icache.overall_miss_rate::cpu.inst 0.000457 # miss rate for overall accesses 540system.cpu.icache.overall_miss_rate::total 0.000457 # miss rate for overall accesses 541system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21047.374780 # average ReadReq miss latency 542system.cpu.icache.ReadReq_avg_miss_latency::total 21047.374780 # average ReadReq miss latency 543system.cpu.icache.demand_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency 544system.cpu.icache.demand_avg_miss_latency::total 21047.374780 # average overall miss latency 545system.cpu.icache.overall_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency 546system.cpu.icache.overall_avg_miss_latency::total 21047.374780 # average overall miss latency 547system.cpu.icache.blocked_cycles::no_mshrs 550 # number of cycles access was blocked | 508system.cpu.icache.occ_blocks::cpu.inst 1849.968594 # Average occupied blocks per requestor 509system.cpu.icache.occ_percent::cpu.inst 0.903305 # Average percentage of cache occupancy 510system.cpu.icache.occ_percent::total 0.903305 # Average percentage of cache occupancy 511system.cpu.icache.ReadReq_hits::cpu.inst 37534809 # number of ReadReq hits 512system.cpu.icache.ReadReq_hits::total 37534809 # number of ReadReq hits 513system.cpu.icache.demand_hits::cpu.inst 37534809 # number of demand (read+write) hits 514system.cpu.icache.demand_hits::total 37534809 # number of demand (read+write) hits 515system.cpu.icache.overall_hits::cpu.inst 37534809 # number of overall hits 516system.cpu.icache.overall_hits::total 37534809 # number of overall hits 517system.cpu.icache.ReadReq_misses::cpu.inst 17059 # number of ReadReq misses 518system.cpu.icache.ReadReq_misses::total 17059 # number of ReadReq misses 519system.cpu.icache.demand_misses::cpu.inst 17059 # number of demand (read+write) misses 520system.cpu.icache.demand_misses::total 17059 # number of demand (read+write) misses 521system.cpu.icache.overall_misses::cpu.inst 17059 # number of overall misses 522system.cpu.icache.overall_misses::total 17059 # number of overall misses 523system.cpu.icache.ReadReq_miss_latency::cpu.inst 362452498 # number of ReadReq miss cycles 524system.cpu.icache.ReadReq_miss_latency::total 362452498 # number of ReadReq miss cycles 525system.cpu.icache.demand_miss_latency::cpu.inst 362452498 # number of demand (read+write) miss cycles 526system.cpu.icache.demand_miss_latency::total 362452498 # number of demand (read+write) miss cycles 527system.cpu.icache.overall_miss_latency::cpu.inst 362452498 # number of overall miss cycles 528system.cpu.icache.overall_miss_latency::total 362452498 # number of overall miss cycles 529system.cpu.icache.ReadReq_accesses::cpu.inst 37551868 # number of ReadReq accesses(hits+misses) 530system.cpu.icache.ReadReq_accesses::total 37551868 # number of ReadReq accesses(hits+misses) 531system.cpu.icache.demand_accesses::cpu.inst 37551868 # number of demand (read+write) accesses 532system.cpu.icache.demand_accesses::total 37551868 # number of demand (read+write) accesses 533system.cpu.icache.overall_accesses::cpu.inst 37551868 # number of overall (read+write) accesses 534system.cpu.icache.overall_accesses::total 37551868 # number of overall (read+write) accesses 535system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000454 # miss rate for ReadReq accesses 536system.cpu.icache.ReadReq_miss_rate::total 0.000454 # miss rate for ReadReq accesses 537system.cpu.icache.demand_miss_rate::cpu.inst 0.000454 # miss rate for demand accesses 538system.cpu.icache.demand_miss_rate::total 0.000454 # miss rate for demand accesses 539system.cpu.icache.overall_miss_rate::cpu.inst 0.000454 # miss rate for overall accesses 540system.cpu.icache.overall_miss_rate::total 0.000454 # miss rate for overall accesses 541system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21246.995603 # average ReadReq miss latency 542system.cpu.icache.ReadReq_avg_miss_latency::total 21246.995603 # average ReadReq miss latency 543system.cpu.icache.demand_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency 544system.cpu.icache.demand_avg_miss_latency::total 21246.995603 # average overall miss latency 545system.cpu.icache.overall_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency 546system.cpu.icache.overall_avg_miss_latency::total 21246.995603 # average overall miss latency 547system.cpu.icache.blocked_cycles::no_mshrs 477 # number of cycles access was blocked |
| 548system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 548system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 549system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked | 549system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked |
| 550system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 550system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 551system.cpu.icache.avg_blocked_cycles::no_mshrs 28.947368 # average number of cycles each access was blocked | 551system.cpu.icache.avg_blocked_cycles::no_mshrs 28.058824 # average number of cycles each access was blocked |
| 552system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.icache.fast_writes 0 # number of fast writes performed 554system.cpu.icache.cache_copies 0 # number of cache copies performed | 552system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.icache.fast_writes 0 # number of fast writes performed 554system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 555system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1259 # number of ReadReq MSHR hits 556system.cpu.icache.ReadReq_mshr_hits::total 1259 # number of ReadReq MSHR hits 557system.cpu.icache.demand_mshr_hits::cpu.inst 1259 # number of demand (read+write) MSHR hits 558system.cpu.icache.demand_mshr_hits::total 1259 # number of demand (read+write) MSHR hits 559system.cpu.icache.overall_mshr_hits::cpu.inst 1259 # number of overall MSHR hits 560system.cpu.icache.overall_mshr_hits::total 1259 # number of overall MSHR hits 561system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15807 # number of ReadReq MSHR misses 562system.cpu.icache.ReadReq_mshr_misses::total 15807 # number of ReadReq MSHR misses 563system.cpu.icache.demand_mshr_misses::cpu.inst 15807 # number of demand (read+write) MSHR misses 564system.cpu.icache.demand_mshr_misses::total 15807 # number of demand (read+write) MSHR misses 565system.cpu.icache.overall_mshr_misses::cpu.inst 15807 # number of overall MSHR misses 566system.cpu.icache.overall_mshr_misses::total 15807 # number of overall MSHR misses 567system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 293030998 # number of ReadReq MSHR miss cycles 568system.cpu.icache.ReadReq_mshr_miss_latency::total 293030998 # number of ReadReq MSHR miss cycles 569system.cpu.icache.demand_mshr_miss_latency::cpu.inst 293030998 # number of demand (read+write) MSHR miss cycles 570system.cpu.icache.demand_mshr_miss_latency::total 293030998 # number of demand (read+write) MSHR miss cycles 571system.cpu.icache.overall_mshr_miss_latency::cpu.inst 293030998 # number of overall MSHR miss cycles 572system.cpu.icache.overall_mshr_miss_latency::total 293030998 # number of overall MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for ReadReq accesses 574system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses 575system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for demand accesses 576system.cpu.icache.demand_mshr_miss_rate::total 0.000423 # mshr miss rate for demand accesses 577system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for overall accesses 578system.cpu.icache.overall_mshr_miss_rate::total 0.000423 # mshr miss rate for overall accesses 579system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18538.052635 # average ReadReq mshr miss latency 580system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18538.052635 # average ReadReq mshr miss latency 581system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18538.052635 # average overall mshr miss latency 582system.cpu.icache.demand_avg_mshr_miss_latency::total 18538.052635 # average overall mshr miss latency 583system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18538.052635 # average overall mshr miss latency 584system.cpu.icache.overall_avg_mshr_miss_latency::total 18538.052635 # average overall mshr miss latency | 555system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1275 # number of ReadReq MSHR hits 556system.cpu.icache.ReadReq_mshr_hits::total 1275 # number of ReadReq MSHR hits 557system.cpu.icache.demand_mshr_hits::cpu.inst 1275 # number of demand (read+write) MSHR hits 558system.cpu.icache.demand_mshr_hits::total 1275 # number of demand (read+write) MSHR hits 559system.cpu.icache.overall_mshr_hits::cpu.inst 1275 # number of overall MSHR hits 560system.cpu.icache.overall_mshr_hits::total 1275 # number of overall MSHR hits 561system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15784 # number of ReadReq MSHR misses 562system.cpu.icache.ReadReq_mshr_misses::total 15784 # number of ReadReq MSHR misses 563system.cpu.icache.demand_mshr_misses::cpu.inst 15784 # number of demand (read+write) MSHR misses 564system.cpu.icache.demand_mshr_misses::total 15784 # number of demand (read+write) MSHR misses 565system.cpu.icache.overall_mshr_misses::cpu.inst 15784 # number of overall MSHR misses 566system.cpu.icache.overall_mshr_misses::total 15784 # number of overall MSHR misses 567system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296328498 # number of ReadReq MSHR miss cycles 568system.cpu.icache.ReadReq_mshr_miss_latency::total 296328498 # number of ReadReq MSHR miss cycles 569system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296328498 # number of demand (read+write) MSHR miss cycles 570system.cpu.icache.demand_mshr_miss_latency::total 296328498 # number of demand (read+write) MSHR miss cycles 571system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296328498 # number of overall MSHR miss cycles 572system.cpu.icache.overall_mshr_miss_latency::total 296328498 # number of overall MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for ReadReq accesses 574system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000420 # mshr miss rate for ReadReq accesses 575system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for demand accesses 576system.cpu.icache.demand_mshr_miss_rate::total 0.000420 # mshr miss rate for demand accesses 577system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for overall accesses 578system.cpu.icache.overall_mshr_miss_rate::total 0.000420 # mshr miss rate for overall accesses 579system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18773.979853 # average ReadReq mshr miss latency 580system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18773.979853 # average ReadReq mshr miss latency 581system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency 582system.cpu.icache.demand_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency 583system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency 584system.cpu.icache.overall_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency |
| 585system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 586system.cpu.l2cache.replacements 0 # number of replacements | 585system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 586system.cpu.l2cache.replacements 0 # number of replacements |
| 587system.cpu.l2cache.tagsinuse 3947.622015 # Cycle average of tags in use 588system.cpu.l2cache.total_refs 13172 # Total number of references to valid blocks. | 587system.cpu.l2cache.tagsinuse 3956.608159 # Cycle average of tags in use 588system.cpu.l2cache.total_refs 13151 # Total number of references to valid blocks. |
| 589system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks. | 589system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks. |
| 590system.cpu.l2cache.avg_refs 2.440163 # Average number of references to valid blocks. | 590system.cpu.l2cache.avg_refs 2.436273 # Average number of references to valid blocks. |
| 591system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 591system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 592system.cpu.l2cache.occ_blocks::writebacks 367.078870 # Average occupied blocks per requestor 593system.cpu.l2cache.occ_blocks::cpu.inst 2774.586146 # Average occupied blocks per requestor 594system.cpu.l2cache.occ_blocks::cpu.data 805.956999 # Average occupied blocks per requestor 595system.cpu.l2cache.occ_percent::writebacks 0.011202 # Average percentage of cache occupancy 596system.cpu.l2cache.occ_percent::cpu.inst 0.084674 # Average percentage of cache occupancy 597system.cpu.l2cache.occ_percent::cpu.data 0.024596 # Average percentage of cache occupancy 598system.cpu.l2cache.occ_percent::total 0.120472 # Average percentage of cache occupancy 599system.cpu.l2cache.ReadReq_hits::cpu.inst 12765 # number of ReadReq hits 600system.cpu.l2cache.ReadReq_hits::cpu.data 296 # number of ReadReq hits 601system.cpu.l2cache.ReadReq_hits::total 13061 # number of ReadReq hits 602system.cpu.l2cache.Writeback_hits::writebacks 1039 # number of Writeback hits 603system.cpu.l2cache.Writeback_hits::total 1039 # number of Writeback hits 604system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits 605system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits 606system.cpu.l2cache.demand_hits::cpu.inst 12765 # number of demand (read+write) hits 607system.cpu.l2cache.demand_hits::cpu.data 313 # number of demand (read+write) hits 608system.cpu.l2cache.demand_hits::total 13078 # number of demand (read+write) hits 609system.cpu.l2cache.overall_hits::cpu.inst 12765 # number of overall hits 610system.cpu.l2cache.overall_hits::cpu.data 313 # number of overall hits 611system.cpu.l2cache.overall_hits::total 13078 # number of overall hits 612system.cpu.l2cache.ReadReq_misses::cpu.inst 3040 # number of ReadReq misses 613system.cpu.l2cache.ReadReq_misses::cpu.data 1500 # number of ReadReq misses 614system.cpu.l2cache.ReadReq_misses::total 4540 # number of ReadReq misses | 592system.cpu.l2cache.occ_blocks::writebacks 373.077110 # Average occupied blocks per requestor 593system.cpu.l2cache.occ_blocks::cpu.inst 2771.508511 # Average occupied blocks per requestor 594system.cpu.l2cache.occ_blocks::cpu.data 812.022538 # Average occupied blocks per requestor 595system.cpu.l2cache.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy 596system.cpu.l2cache.occ_percent::cpu.inst 0.084580 # Average percentage of cache occupancy 597system.cpu.l2cache.occ_percent::cpu.data 0.024781 # Average percentage of cache occupancy 598system.cpu.l2cache.occ_percent::total 0.120746 # Average percentage of cache occupancy 599system.cpu.l2cache.ReadReq_hits::cpu.inst 12748 # number of ReadReq hits 600system.cpu.l2cache.ReadReq_hits::cpu.data 293 # number of ReadReq hits 601system.cpu.l2cache.ReadReq_hits::total 13041 # number of ReadReq hits 602system.cpu.l2cache.Writeback_hits::writebacks 1043 # number of Writeback hits 603system.cpu.l2cache.Writeback_hits::total 1043 # number of Writeback hits 604system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits 605system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits 606system.cpu.l2cache.demand_hits::cpu.inst 12748 # number of demand (read+write) hits 607system.cpu.l2cache.demand_hits::cpu.data 311 # number of demand (read+write) hits 608system.cpu.l2cache.demand_hits::total 13059 # number of demand (read+write) hits 609system.cpu.l2cache.overall_hits::cpu.inst 12748 # number of overall hits 610system.cpu.l2cache.overall_hits::cpu.data 311 # number of overall hits 611system.cpu.l2cache.overall_hits::total 13059 # number of overall hits 612system.cpu.l2cache.ReadReq_misses::cpu.inst 3032 # number of ReadReq misses 613system.cpu.l2cache.ReadReq_misses::cpu.data 1507 # number of ReadReq misses 614system.cpu.l2cache.ReadReq_misses::total 4539 # number of ReadReq misses |
| 615system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 616system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses | 615system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 616system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses |
| 617system.cpu.l2cache.ReadExReq_misses::cpu.data 2797 # number of ReadExReq misses 618system.cpu.l2cache.ReadExReq_misses::total 2797 # number of ReadExReq misses 619system.cpu.l2cache.demand_misses::cpu.inst 3040 # number of demand (read+write) misses 620system.cpu.l2cache.demand_misses::cpu.data 4297 # number of demand (read+write) misses 621system.cpu.l2cache.demand_misses::total 7337 # number of demand (read+write) misses 622system.cpu.l2cache.overall_misses::cpu.inst 3040 # number of overall misses 623system.cpu.l2cache.overall_misses::cpu.data 4297 # number of overall misses 624system.cpu.l2cache.overall_misses::total 7337 # number of overall misses 625system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149534000 # number of ReadReq miss cycles 626system.cpu.l2cache.ReadReq_miss_latency::cpu.data 75407000 # number of ReadReq miss cycles 627system.cpu.l2cache.ReadReq_miss_latency::total 224941000 # number of ReadReq miss cycles 628system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 129040500 # number of ReadExReq miss cycles 629system.cpu.l2cache.ReadExReq_miss_latency::total 129040500 # number of ReadExReq miss cycles 630system.cpu.l2cache.demand_miss_latency::cpu.inst 149534000 # number of demand (read+write) miss cycles 631system.cpu.l2cache.demand_miss_latency::cpu.data 204447500 # number of demand (read+write) miss cycles 632system.cpu.l2cache.demand_miss_latency::total 353981500 # number of demand (read+write) miss cycles 633system.cpu.l2cache.overall_miss_latency::cpu.inst 149534000 # number of overall miss cycles 634system.cpu.l2cache.overall_miss_latency::cpu.data 204447500 # number of overall miss cycles 635system.cpu.l2cache.overall_miss_latency::total 353981500 # number of overall miss cycles 636system.cpu.l2cache.ReadReq_accesses::cpu.inst 15805 # number of ReadReq accesses(hits+misses) 637system.cpu.l2cache.ReadReq_accesses::cpu.data 1796 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.ReadReq_accesses::total 17601 # number of ReadReq accesses(hits+misses) 639system.cpu.l2cache.Writeback_accesses::writebacks 1039 # number of Writeback accesses(hits+misses) 640system.cpu.l2cache.Writeback_accesses::total 1039 # number of Writeback accesses(hits+misses) | 617system.cpu.l2cache.ReadExReq_misses::cpu.data 2792 # number of ReadExReq misses 618system.cpu.l2cache.ReadExReq_misses::total 2792 # number of ReadExReq misses 619system.cpu.l2cache.demand_misses::cpu.inst 3032 # number of demand (read+write) misses 620system.cpu.l2cache.demand_misses::cpu.data 4299 # number of demand (read+write) misses 621system.cpu.l2cache.demand_misses::total 7331 # number of demand (read+write) misses 622system.cpu.l2cache.overall_misses::cpu.inst 3032 # number of overall misses 623system.cpu.l2cache.overall_misses::cpu.data 4299 # number of overall misses 624system.cpu.l2cache.overall_misses::total 7331 # number of overall misses 625system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153017500 # number of ReadReq miss cycles 626system.cpu.l2cache.ReadReq_miss_latency::cpu.data 82832500 # number of ReadReq miss cycles 627system.cpu.l2cache.ReadReq_miss_latency::total 235850000 # number of ReadReq miss cycles 628system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 135162000 # number of ReadExReq miss cycles 629system.cpu.l2cache.ReadExReq_miss_latency::total 135162000 # number of ReadExReq miss cycles 630system.cpu.l2cache.demand_miss_latency::cpu.inst 153017500 # number of demand (read+write) miss cycles 631system.cpu.l2cache.demand_miss_latency::cpu.data 217994500 # number of demand (read+write) miss cycles 632system.cpu.l2cache.demand_miss_latency::total 371012000 # number of demand (read+write) miss cycles 633system.cpu.l2cache.overall_miss_latency::cpu.inst 153017500 # number of overall miss cycles 634system.cpu.l2cache.overall_miss_latency::cpu.data 217994500 # number of overall miss cycles 635system.cpu.l2cache.overall_miss_latency::total 371012000 # number of overall miss cycles 636system.cpu.l2cache.ReadReq_accesses::cpu.inst 15780 # number of ReadReq accesses(hits+misses) 637system.cpu.l2cache.ReadReq_accesses::cpu.data 1800 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.ReadReq_accesses::total 17580 # number of ReadReq accesses(hits+misses) 639system.cpu.l2cache.Writeback_accesses::writebacks 1043 # number of Writeback accesses(hits+misses) 640system.cpu.l2cache.Writeback_accesses::total 1043 # number of Writeback accesses(hits+misses) |
| 641system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 642system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) | 641system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 642system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) |
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| 646system.cpu.l2cache.demand_accesses::cpu.data 4610 # number of demand (read+write) accesses | 646system.cpu.l2cache.demand_accesses::cpu.data 4610 # number of demand (read+write) accesses |
| 647system.cpu.l2cache.demand_accesses::total 20415 # number of demand (read+write) accesses 648system.cpu.l2cache.overall_accesses::cpu.inst 15805 # number of overall (read+write) accesses | 647system.cpu.l2cache.demand_accesses::total 20390 # number of demand (read+write) accesses 648system.cpu.l2cache.overall_accesses::cpu.inst 15780 # number of overall (read+write) accesses |
| 649system.cpu.l2cache.overall_accesses::cpu.data 4610 # number of overall (read+write) accesses | 649system.cpu.l2cache.overall_accesses::cpu.data 4610 # number of overall (read+write) accesses |
| 650system.cpu.l2cache.overall_accesses::total 20415 # number of overall (read+write) accesses 651system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192344 # miss rate for ReadReq accesses 652system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835189 # miss rate for ReadReq accesses 653system.cpu.l2cache.ReadReq_miss_rate::total 0.257940 # miss rate for ReadReq accesses | 650system.cpu.l2cache.overall_accesses::total 20390 # number of overall (read+write) accesses 651system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192142 # miss rate for ReadReq accesses 652system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.837222 # miss rate for ReadReq accesses 653system.cpu.l2cache.ReadReq_miss_rate::total 0.258191 # miss rate for ReadReq accesses |
| 654system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 655system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 654system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 655system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 656system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993959 # miss rate for ReadExReq accesses 657system.cpu.l2cache.ReadExReq_miss_rate::total 0.993959 # miss rate for ReadExReq accesses 658system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192344 # miss rate for demand accesses 659system.cpu.l2cache.demand_miss_rate::cpu.data 0.932104 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate::total 0.359393 # miss rate for demand accesses 661system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192344 # miss rate for overall accesses 662system.cpu.l2cache.overall_miss_rate::cpu.data 0.932104 # miss rate for overall accesses 663system.cpu.l2cache.overall_miss_rate::total 0.359393 # miss rate for overall accesses 664system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49188.815789 # average ReadReq miss latency 665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50271.333333 # average ReadReq miss latency 666system.cpu.l2cache.ReadReq_avg_miss_latency::total 49546.475771 # average ReadReq miss latency 667system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46135.323561 # average ReadExReq miss latency 668system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46135.323561 # average ReadExReq miss latency 669system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49188.815789 # average overall miss latency 670system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47579.124971 # average overall miss latency 671system.cpu.l2cache.demand_avg_miss_latency::total 48246.081505 # average overall miss latency 672system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49188.815789 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47579.124971 # average overall miss latency 674system.cpu.l2cache.overall_avg_miss_latency::total 48246.081505 # average overall miss latency | 656system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993594 # miss rate for ReadExReq accesses 657system.cpu.l2cache.ReadExReq_miss_rate::total 0.993594 # miss rate for ReadExReq accesses 658system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192142 # miss rate for demand accesses 659system.cpu.l2cache.demand_miss_rate::cpu.data 0.932538 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate::total 0.359539 # miss rate for demand accesses 661system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192142 # miss rate for overall accesses 662system.cpu.l2cache.overall_miss_rate::cpu.data 0.932538 # miss rate for overall accesses 663system.cpu.l2cache.overall_miss_rate::total 0.359539 # miss rate for overall accesses 664system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50467.513193 # average ReadReq miss latency 665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54965.162575 # average ReadReq miss latency 666system.cpu.l2cache.ReadReq_avg_miss_latency::total 51960.784314 # average ReadReq miss latency 667system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48410.458453 # average ReadExReq miss latency 668system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48410.458453 # average ReadExReq miss latency 669system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50467.513193 # average overall miss latency 670system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50708.187951 # average overall miss latency 671system.cpu.l2cache.demand_avg_miss_latency::total 50608.648206 # average overall miss latency 672system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50467.513193 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50708.187951 # average overall miss latency 674system.cpu.l2cache.overall_avg_miss_latency::total 50608.648206 # average overall miss latency |
| 675system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 676system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 678system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 679system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 680system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 681system.cpu.l2cache.fast_writes 0 # number of fast writes performed 682system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 675system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 676system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 678system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 679system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 680system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 681system.cpu.l2cache.fast_writes 0 # number of fast writes performed 682system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 683system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits | 683system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits |
| 684system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits | 684system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits |
| 685system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits 686system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits | 685system.cpu.l2cache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits 686system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits |
| 687system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits | 687system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits |
| 688system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits 689system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits | 688system.cpu.l2cache.demand_mshr_hits::total 53 # number of demand (read+write) MSHR hits 689system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits |
| 690system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits | 690system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits |
| 691system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits 692system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses 693system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1460 # number of ReadReq MSHR misses 694system.cpu.l2cache.ReadReq_mshr_misses::total 4489 # number of ReadReq MSHR misses | 691system.cpu.l2cache.overall_mshr_hits::total 53 # number of overall MSHR hits 692system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3019 # number of ReadReq MSHR misses 693system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1467 # number of ReadReq MSHR misses 694system.cpu.l2cache.ReadReq_mshr_misses::total 4486 # number of ReadReq MSHR misses |
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| 697system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2797 # number of ReadExReq MSHR misses 698system.cpu.l2cache.ReadExReq_mshr_misses::total 2797 # number of ReadExReq MSHR misses 699system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses 700system.cpu.l2cache.demand_mshr_misses::cpu.data 4257 # number of demand (read+write) MSHR misses 701system.cpu.l2cache.demand_mshr_misses::total 7286 # number of demand (read+write) MSHR misses 702system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses 703system.cpu.l2cache.overall_mshr_misses::cpu.data 4257 # number of overall MSHR misses 704system.cpu.l2cache.overall_mshr_misses::total 7286 # number of overall MSHR misses 705system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110751088 # number of ReadReq MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55451199 # number of ReadReq MSHR miss cycles 707system.cpu.l2cache.ReadReq_mshr_miss_latency::total 166202287 # number of ReadReq MSHR miss cycles | 697system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2792 # number of ReadExReq MSHR misses 698system.cpu.l2cache.ReadExReq_mshr_misses::total 2792 # number of ReadExReq MSHR misses 699system.cpu.l2cache.demand_mshr_misses::cpu.inst 3019 # number of demand (read+write) MSHR misses 700system.cpu.l2cache.demand_mshr_misses::cpu.data 4259 # number of demand (read+write) MSHR misses 701system.cpu.l2cache.demand_mshr_misses::total 7278 # number of demand (read+write) MSHR misses 702system.cpu.l2cache.overall_mshr_misses::cpu.inst 3019 # number of overall MSHR misses 703system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses 704system.cpu.l2cache.overall_mshr_misses::total 7278 # number of overall MSHR misses 705system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115050359 # number of ReadReq MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62984754 # number of ReadReq MSHR miss cycles 707system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178035113 # number of ReadReq MSHR miss cycles |
| 708system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 709system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles | 708system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 709system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles |
| 710system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94361392 # number of ReadExReq MSHR miss cycles 711system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94361392 # number of ReadExReq MSHR miss cycles 712system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110751088 # number of demand (read+write) MSHR miss cycles 713system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149812591 # number of demand (read+write) MSHR miss cycles 714system.cpu.l2cache.demand_mshr_miss_latency::total 260563679 # number of demand (read+write) MSHR miss cycles 715system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110751088 # number of overall MSHR miss cycles 716system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149812591 # number of overall MSHR miss cycles 717system.cpu.l2cache.overall_mshr_miss_latency::total 260563679 # number of overall MSHR miss cycles 718system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812918 # mshr miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255042 # mshr miss rate for ReadReq accesses | 710system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100922692 # number of ReadExReq MSHR miss cycles 711system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100922692 # number of ReadExReq MSHR miss cycles 712system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115050359 # number of demand (read+write) MSHR miss cycles 713system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163907446 # number of demand (read+write) MSHR miss cycles 714system.cpu.l2cache.demand_mshr_miss_latency::total 278957805 # number of demand (read+write) MSHR miss cycles 715system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles 716system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles 717system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles 718system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses |
| 721system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 722system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 721system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 722system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 723system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993959 # mshr miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993959 # mshr miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for demand accesses 726system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for demand accesses 727system.cpu.l2cache.demand_mshr_miss_rate::total 0.356894 # mshr miss rate for demand accesses 728system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for overall accesses 729system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::total 0.356894 # mshr miss rate for overall accesses 731system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36563.581380 # average ReadReq mshr miss latency 732system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37980.273288 # average ReadReq mshr miss latency 733system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37024.345511 # average ReadReq mshr miss latency | 723system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993594 # mshr miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993594 # mshr miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for demand accesses 726system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for demand accesses 727system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940 # mshr miss rate for demand accesses 728system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses 729system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses 731system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency 732system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency 733system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency |
| 734system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 735system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency | 734system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 735system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency |
| 736system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33736.643547 # average ReadExReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33736.643547 # average ReadExReq mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency | 736system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency |
| 744system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 745system.cpu.dcache.replacements 1413 # number of replacements | 744system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 745system.cpu.dcache.replacements 1413 # number of replacements |
| 746system.cpu.dcache.tagsinuse 3109.588822 # Cycle average of tags in use 747system.cpu.dcache.total_refs 170749767 # Total number of references to valid blocks. | 746system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use 747system.cpu.dcache.total_refs 170925187 # Total number of references to valid blocks. |
| 748system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks. | 748system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks. |
| 749system.cpu.dcache.avg_refs 37038.995011 # Average number of references to valid blocks. | 749system.cpu.dcache.avg_refs 37077.047072 # Average number of references to valid blocks. |
| 750system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 750system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 751system.cpu.dcache.occ_blocks::cpu.data 3109.588822 # Average occupied blocks per requestor 752system.cpu.dcache.occ_percent::cpu.data 0.759177 # Average percentage of cache occupancy 753system.cpu.dcache.occ_percent::total 0.759177 # Average percentage of cache occupancy 754system.cpu.dcache.ReadReq_hits::cpu.data 88696383 # number of ReadReq hits 755system.cpu.dcache.ReadReq_hits::total 88696383 # number of ReadReq hits 756system.cpu.dcache.WriteReq_hits::cpu.data 82031533 # number of WriteReq hits 757system.cpu.dcache.WriteReq_hits::total 82031533 # number of WriteReq hits | 751system.cpu.dcache.occ_blocks::cpu.data 3109.949983 # Average occupied blocks per requestor 752system.cpu.dcache.occ_percent::cpu.data 0.759265 # Average percentage of cache occupancy 753system.cpu.dcache.occ_percent::total 0.759265 # Average percentage of cache occupancy 754system.cpu.dcache.ReadReq_hits::cpu.data 88871803 # number of ReadReq hits 755system.cpu.dcache.ReadReq_hits::total 88871803 # number of ReadReq hits 756system.cpu.dcache.WriteReq_hits::cpu.data 82031525 # number of WriteReq hits 757system.cpu.dcache.WriteReq_hits::total 82031525 # number of WriteReq hits |
| 758system.cpu.dcache.LoadLockedReq_hits::cpu.data 10952 # number of LoadLockedReq hits 759system.cpu.dcache.LoadLockedReq_hits::total 10952 # number of LoadLockedReq hits 760system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 761system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits | 758system.cpu.dcache.LoadLockedReq_hits::cpu.data 10952 # number of LoadLockedReq hits 759system.cpu.dcache.LoadLockedReq_hits::total 10952 # number of LoadLockedReq hits 760system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 761system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits |
| 762system.cpu.dcache.demand_hits::cpu.data 170727916 # number of demand (read+write) hits 763system.cpu.dcache.demand_hits::total 170727916 # number of demand (read+write) hits 764system.cpu.dcache.overall_hits::cpu.data 170727916 # number of overall hits 765system.cpu.dcache.overall_hits::total 170727916 # number of overall hits 766system.cpu.dcache.ReadReq_misses::cpu.data 4041 # number of ReadReq misses 767system.cpu.dcache.ReadReq_misses::total 4041 # number of ReadReq misses 768system.cpu.dcache.WriteReq_misses::cpu.data 21132 # number of WriteReq misses 769system.cpu.dcache.WriteReq_misses::total 21132 # number of WriteReq misses | 762system.cpu.dcache.demand_hits::cpu.data 170903328 # number of demand (read+write) hits 763system.cpu.dcache.demand_hits::total 170903328 # number of demand (read+write) hits 764system.cpu.dcache.overall_hits::cpu.data 170903328 # number of overall hits 765system.cpu.dcache.overall_hits::total 170903328 # number of overall hits 766system.cpu.dcache.ReadReq_misses::cpu.data 4023 # number of ReadReq misses 767system.cpu.dcache.ReadReq_misses::total 4023 # number of ReadReq misses 768system.cpu.dcache.WriteReq_misses::cpu.data 21140 # number of WriteReq misses 769system.cpu.dcache.WriteReq_misses::total 21140 # number of WriteReq misses |
| 770system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 771system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 770system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 771system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 772system.cpu.dcache.demand_misses::cpu.data 25173 # number of demand (read+write) misses 773system.cpu.dcache.demand_misses::total 25173 # number of demand (read+write) misses 774system.cpu.dcache.overall_misses::cpu.data 25173 # number of overall misses 775system.cpu.dcache.overall_misses::total 25173 # number of overall misses 776system.cpu.dcache.ReadReq_miss_latency::cpu.data 164980000 # number of ReadReq miss cycles 777system.cpu.dcache.ReadReq_miss_latency::total 164980000 # number of ReadReq miss cycles 778system.cpu.dcache.WriteReq_miss_latency::cpu.data 832721164 # number of WriteReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::total 832721164 # number of WriteReq miss cycles 780system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles 782system.cpu.dcache.demand_miss_latency::cpu.data 997701164 # number of demand (read+write) miss cycles 783system.cpu.dcache.demand_miss_latency::total 997701164 # number of demand (read+write) miss cycles 784system.cpu.dcache.overall_miss_latency::cpu.data 997701164 # number of overall miss cycles 785system.cpu.dcache.overall_miss_latency::total 997701164 # number of overall miss cycles 786system.cpu.dcache.ReadReq_accesses::cpu.data 88700424 # number of ReadReq accesses(hits+misses) 787system.cpu.dcache.ReadReq_accesses::total 88700424 # number of ReadReq accesses(hits+misses) | 772system.cpu.dcache.demand_misses::cpu.data 25163 # number of demand (read+write) misses 773system.cpu.dcache.demand_misses::total 25163 # number of demand (read+write) misses 774system.cpu.dcache.overall_misses::cpu.data 25163 # number of overall misses 775system.cpu.dcache.overall_misses::total 25163 # number of overall misses 776system.cpu.dcache.ReadReq_miss_latency::cpu.data 177641500 # number of ReadReq miss cycles 777system.cpu.dcache.ReadReq_miss_latency::total 177641500 # number of ReadReq miss cycles 778system.cpu.dcache.WriteReq_miss_latency::cpu.data 874574146 # number of WriteReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::total 874574146 # number of WriteReq miss cycles 780system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116000 # number of LoadLockedReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::total 116000 # number of LoadLockedReq miss cycles 782system.cpu.dcache.demand_miss_latency::cpu.data 1052215646 # number of demand (read+write) miss cycles 783system.cpu.dcache.demand_miss_latency::total 1052215646 # number of demand (read+write) miss cycles 784system.cpu.dcache.overall_miss_latency::cpu.data 1052215646 # number of overall miss cycles 785system.cpu.dcache.overall_miss_latency::total 1052215646 # number of overall miss cycles 786system.cpu.dcache.ReadReq_accesses::cpu.data 88875826 # number of ReadReq accesses(hits+misses) 787system.cpu.dcache.ReadReq_accesses::total 88875826 # number of ReadReq accesses(hits+misses) |
| 788system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10954 # number of LoadLockedReq accesses(hits+misses) 791system.cpu.dcache.LoadLockedReq_accesses::total 10954 # number of LoadLockedReq accesses(hits+misses) 792system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 793system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) | 788system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10954 # number of LoadLockedReq accesses(hits+misses) 791system.cpu.dcache.LoadLockedReq_accesses::total 10954 # number of LoadLockedReq accesses(hits+misses) 792system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 793system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) |
| 794system.cpu.dcache.demand_accesses::cpu.data 170753089 # number of demand (read+write) accesses 795system.cpu.dcache.demand_accesses::total 170753089 # number of demand (read+write) accesses 796system.cpu.dcache.overall_accesses::cpu.data 170753089 # number of overall (read+write) accesses 797system.cpu.dcache.overall_accesses::total 170753089 # number of overall (read+write) accesses 798system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses 799system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses | 794system.cpu.dcache.demand_accesses::cpu.data 170928491 # number of demand (read+write) accesses 795system.cpu.dcache.demand_accesses::total 170928491 # number of demand (read+write) accesses 796system.cpu.dcache.overall_accesses::cpu.data 170928491 # number of overall (read+write) accesses 797system.cpu.dcache.overall_accesses::total 170928491 # number of overall (read+write) accesses 798system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses 799system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses |
| 800system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses 801system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses 802system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000183 # miss rate for LoadLockedReq accesses 803system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000183 # miss rate for LoadLockedReq accesses 804system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses 805system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses 806system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses 807system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses | 800system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses 801system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses 802system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000183 # miss rate for LoadLockedReq accesses 803system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000183 # miss rate for LoadLockedReq accesses 804system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses 805system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses 806system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses 807system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses |
| 808system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40826.528087 # average ReadReq miss latency 809system.cpu.dcache.ReadReq_avg_miss_latency::total 40826.528087 # average ReadReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39405.695817 # average WriteReq miss latency 811system.cpu.dcache.WriteReq_avg_miss_latency::total 39405.695817 # average WriteReq miss latency 812system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency 813system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency 814system.cpu.dcache.demand_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency 815system.cpu.dcache.demand_avg_miss_latency::total 39633.780797 # average overall miss latency 816system.cpu.dcache.overall_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency 817system.cpu.dcache.overall_avg_miss_latency::total 39633.780797 # average overall miss latency 818system.cpu.dcache.blocked_cycles::no_mshrs 13427 # number of cycles access was blocked 819system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked 820system.cpu.dcache.blocked::no_mshrs 430 # number of cycles access was blocked 821system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked 822system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.225581 # average number of cycles each access was blocked 823system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked | 808system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44156.475267 # average ReadReq miss latency 809system.cpu.dcache.ReadReq_avg_miss_latency::total 44156.475267 # average ReadReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41370.584011 # average WriteReq miss latency 811system.cpu.dcache.WriteReq_avg_miss_latency::total 41370.584011 # average WriteReq miss latency 812system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58000 # average LoadLockedReq miss latency 813system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58000 # average LoadLockedReq miss latency 814system.cpu.dcache.demand_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency 815system.cpu.dcache.demand_avg_miss_latency::total 41815.985614 # average overall miss latency 816system.cpu.dcache.overall_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency 817system.cpu.dcache.overall_avg_miss_latency::total 41815.985614 # average overall miss latency 818system.cpu.dcache.blocked_cycles::no_mshrs 15531 # number of cycles access was blocked 819system.cpu.dcache.blocked_cycles::no_targets 796 # number of cycles access was blocked 820system.cpu.dcache.blocked::no_mshrs 449 # number of cycles access was blocked 821system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked 822system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.590200 # average number of cycles each access was blocked 823system.cpu.dcache.avg_blocked_cycles::no_targets 61.230769 # average number of cycles each access was blocked |
| 824system.cpu.dcache.fast_writes 0 # number of fast writes performed 825system.cpu.dcache.cache_copies 0 # number of cache copies performed | 824system.cpu.dcache.fast_writes 0 # number of fast writes performed 825system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 826system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks 827system.cpu.dcache.writebacks::total 1039 # number of writebacks 828system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2244 # number of ReadReq MSHR hits 829system.cpu.dcache.ReadReq_mshr_hits::total 2244 # number of ReadReq MSHR hits 830system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18317 # number of WriteReq MSHR hits 831system.cpu.dcache.WriteReq_mshr_hits::total 18317 # number of WriteReq MSHR hits | 826system.cpu.dcache.writebacks::writebacks 1043 # number of writebacks 827system.cpu.dcache.writebacks::total 1043 # number of writebacks 828system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2222 # number of ReadReq MSHR hits 829system.cpu.dcache.ReadReq_mshr_hits::total 2222 # number of ReadReq MSHR hits 830system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18329 # number of WriteReq MSHR hits 831system.cpu.dcache.WriteReq_mshr_hits::total 18329 # number of WriteReq MSHR hits |
| 832system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 833system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 832system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 833system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 834system.cpu.dcache.demand_mshr_hits::cpu.data 20561 # number of demand (read+write) MSHR hits 835system.cpu.dcache.demand_mshr_hits::total 20561 # number of demand (read+write) MSHR hits 836system.cpu.dcache.overall_mshr_hits::cpu.data 20561 # number of overall MSHR hits 837system.cpu.dcache.overall_mshr_hits::total 20561 # number of overall MSHR hits 838system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1797 # number of ReadReq MSHR misses 839system.cpu.dcache.ReadReq_mshr_misses::total 1797 # number of ReadReq MSHR misses 840system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2815 # number of WriteReq MSHR misses 841system.cpu.dcache.WriteReq_mshr_misses::total 2815 # number of WriteReq MSHR misses | 834system.cpu.dcache.demand_mshr_hits::cpu.data 20551 # number of demand (read+write) MSHR hits 835system.cpu.dcache.demand_mshr_hits::total 20551 # number of demand (read+write) MSHR hits 836system.cpu.dcache.overall_mshr_hits::cpu.data 20551 # number of overall MSHR hits 837system.cpu.dcache.overall_mshr_hits::total 20551 # number of overall MSHR hits 838system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1801 # number of ReadReq MSHR misses 839system.cpu.dcache.ReadReq_mshr_misses::total 1801 # number of ReadReq MSHR misses 840system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2811 # number of WriteReq MSHR misses 841system.cpu.dcache.WriteReq_mshr_misses::total 2811 # number of WriteReq MSHR misses |
| 842system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses 843system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses 844system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses 845system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses | 842system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses 843system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses 844system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses 845system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses |
| 846system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80314500 # number of ReadReq MSHR miss cycles 847system.cpu.dcache.ReadReq_mshr_miss_latency::total 80314500 # number of ReadReq MSHR miss cycles 848system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 132089500 # number of WriteReq MSHR miss cycles 849system.cpu.dcache.WriteReq_mshr_miss_latency::total 132089500 # number of WriteReq MSHR miss cycles 850system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212404000 # number of demand (read+write) MSHR miss cycles 851system.cpu.dcache.demand_mshr_miss_latency::total 212404000 # number of demand (read+write) MSHR miss cycles 852system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212404000 # number of overall MSHR miss cycles 853system.cpu.dcache.overall_mshr_miss_latency::total 212404000 # number of overall MSHR miss cycles | 846system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87720000 # number of ReadReq MSHR miss cycles 847system.cpu.dcache.ReadReq_mshr_miss_latency::total 87720000 # number of ReadReq MSHR miss cycles 848system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138213500 # number of WriteReq MSHR miss cycles 849system.cpu.dcache.WriteReq_mshr_miss_latency::total 138213500 # number of WriteReq MSHR miss cycles 850system.cpu.dcache.demand_mshr_miss_latency::cpu.data 225933500 # number of demand (read+write) MSHR miss cycles 851system.cpu.dcache.demand_mshr_miss_latency::total 225933500 # number of demand (read+write) MSHR miss cycles 852system.cpu.dcache.overall_mshr_miss_latency::cpu.data 225933500 # number of overall MSHR miss cycles 853system.cpu.dcache.overall_mshr_miss_latency::total 225933500 # number of overall MSHR miss cycles |
| 854system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses 855system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses 856system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses 857system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses 858system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 859system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 860system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 861system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses | 854system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses 855system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses 856system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses 857system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses 858system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 859system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 860system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 861system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
| 862system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44693.656093 # average ReadReq mshr miss latency 863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44693.656093 # average ReadReq mshr miss latency 864system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46923.445826 # average WriteReq mshr miss latency 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46923.445826 # average WriteReq mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency | 862system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48706.274292 # average ReadReq mshr miss latency 863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48706.274292 # average ReadReq mshr miss latency 864system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49168.801138 # average WriteReq mshr miss latency 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49168.801138 # average WriteReq mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency |
| 870system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 871 872---------- End Simulation Statistics ---------- | 870system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 871 872---------- End Simulation Statistics ---------- |