| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.071775 # Number of seconds simulated 4sim_ticks 71774859500 # Number of ticks simulated 5final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.071775 # Number of seconds simulated 4sim_ticks 71774859500 # Number of ticks simulated 5final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 200202 # Simulator instruction rate (inst/s) 8host_op_rate 255946 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52626024 # Simulator tick rate (ticks/s) 10host_mem_usage 233120 # Number of bytes of host memory used 11host_seconds 1363.87 # Real time elapsed on the host | 7host_inst_rate 69606 # Simulator instruction rate (inst/s) 8host_op_rate 88987 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18296996 # Simulator tick rate (ticks/s) 10host_mem_usage 240272 # Number of bytes of host memory used 11host_seconds 3922.77 # Real time elapsed on the host |
| 12sim_insts 273048474 # Number of instructions simulated 13sim_ops 349076199 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 472896 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 7389 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 352 unchanged lines hidden (view full) --- 372system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses 373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency 374system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency 375system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency 376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 273048474 # Number of instructions simulated 13sim_ops 349076199 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 472896 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 7389 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 352 unchanged lines hidden (view full) --- 372system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses 373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency 374system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency 375system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency 376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 380system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 381system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 380system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 381system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 382system.cpu.icache.fast_writes 0 # number of fast writes performed 383system.cpu.icache.cache_copies 0 # number of cache copies performed 384system.cpu.icache.ReadReq_mshr_hits::cpu.inst 900 # number of ReadReq MSHR hits 385system.cpu.icache.ReadReq_mshr_hits::total 900 # number of ReadReq MSHR hits 386system.cpu.icache.demand_mshr_hits::cpu.inst 900 # number of demand (read+write) MSHR hits 387system.cpu.icache.demand_mshr_hits::total 900 # number of demand (read+write) MSHR hits 388system.cpu.icache.overall_mshr_hits::cpu.inst 900 # number of overall MSHR hits 389system.cpu.icache.overall_mshr_hits::total 900 # number of overall MSHR hits --- 78 unchanged lines hidden (view full) --- 468system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency 469system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency 470system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency 472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 473system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked | 382system.cpu.icache.fast_writes 0 # number of fast writes performed 383system.cpu.icache.cache_copies 0 # number of cache copies performed 384system.cpu.icache.ReadReq_mshr_hits::cpu.inst 900 # number of ReadReq MSHR hits 385system.cpu.icache.ReadReq_mshr_hits::total 900 # number of ReadReq MSHR hits 386system.cpu.icache.demand_mshr_hits::cpu.inst 900 # number of demand (read+write) MSHR hits 387system.cpu.icache.demand_mshr_hits::total 900 # number of demand (read+write) MSHR hits 388system.cpu.icache.overall_mshr_hits::cpu.inst 900 # number of overall MSHR hits 389system.cpu.icache.overall_mshr_hits::total 900 # number of overall MSHR hits --- 78 unchanged lines hidden (view full) --- 468system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency 469system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency 470system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency 472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 473system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked |
| 476system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked | 476system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 477system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked 478system.cpu.dcache.fast_writes 0 # number of fast writes performed 479system.cpu.dcache.cache_copies 0 # number of cache copies performed 480system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks 481system.cpu.dcache.writebacks::total 1038 # number of writebacks 482system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1792 # number of ReadReq MSHR hits 483system.cpu.dcache.ReadReq_mshr_hits::total 1792 # number of ReadReq MSHR hits 484system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16671 # number of WriteReq MSHR hits --- 108 unchanged lines hidden (view full) --- 593system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency 594system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency 595system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency 596system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency 597system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 598system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 599system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 600system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 477system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked 478system.cpu.dcache.fast_writes 0 # number of fast writes performed 479system.cpu.dcache.cache_copies 0 # number of cache copies performed 480system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks 481system.cpu.dcache.writebacks::total 1038 # number of writebacks 482system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1792 # number of ReadReq MSHR hits 483system.cpu.dcache.ReadReq_mshr_hits::total 1792 # number of ReadReq MSHR hits 484system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16671 # number of WriteReq MSHR hits --- 108 unchanged lines hidden (view full) --- 593system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency 594system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency 595system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency 596system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency 597system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 598system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 599system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 600system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 601system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 602system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 601system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 602system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 603system.cpu.l2cache.fast_writes 0 # number of fast writes performed 604system.cpu.l2cache.cache_copies 0 # number of cache copies performed 605system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits 606system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 607system.cpu.l2cache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits 608system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits 609system.cpu.l2cache.demand_mshr_hits::cpu.data 49 # number of demand (read+write) MSHR hits 610system.cpu.l2cache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits --- 48 unchanged lines hidden --- | 603system.cpu.l2cache.fast_writes 0 # number of fast writes performed 604system.cpu.l2cache.cache_copies 0 # number of cache copies performed 605system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits 606system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 607system.cpu.l2cache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits 608system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits 609system.cpu.l2cache.demand_mshr_hits::cpu.data 49 # number of demand (read+write) MSHR hits 610system.cpu.l2cache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits --- 48 unchanged lines hidden --- |