| stats.txt (11589:af2f7fef4875) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.111754 # Number of seconds simulated 4sim_ticks 111753553500 # Number of ticks simulated 5final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.120480 # Number of seconds simulated 4sim_ticks 120480458500 # Number of ticks simulated 5final_tick 120480458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 142273 # Simulator instruction rate (inst/s) 8host_op_rate 170814 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 58231903 # Simulator tick rate (ticks/s) 10host_mem_usage 288696 # Number of bytes of host memory used 11host_seconds 1919.11 # Real time elapsed on the host 12sim_insts 273037220 # Number of instructions simulated 13sim_ops 327811602 # Number of ops (including micro ops) simulated | 7host_inst_rate 129515 # Simulator instruction rate (inst/s) 8host_op_rate 155497 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57149813 # Simulator tick rate (ticks/s) 10host_mem_usage 293332 # Number of bytes of host memory used 11host_seconds 2108.15 # Real time elapsed on the host 12sim_insts 273037218 # Number of instructions simulated 13sim_ops 327811600 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory 20system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 620544 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 620544 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 9696 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 72283 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.l2cache.prefetcher 2638 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 84617 # Number of read requests responded to by this memory 27system.physmem.bw_read::cpu.inst 5552790 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.data 41395659 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.l2cache.prefetcher 1510753 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 48459202 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 5552790 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 5552790 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 5552790 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.data 41395659 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.l2cache.prefetcher 1510753 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 48459202 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 84617 # Number of read requests accepted | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 1888064 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 14651392 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 167808 # Number of bytes read from this memory 20system.physmem.bytes_read::total 16707264 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1888064 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1888064 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 29501 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 228928 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.l2cache.prefetcher 2622 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 261051 # Number of read requests responded to by this memory 27system.physmem.bw_read::cpu.inst 15671122 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.data 121608037 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.l2cache.prefetcher 1392823 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 138671982 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 15671122 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 15671122 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 15671122 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.data 121608037 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.l2cache.prefetcher 1392823 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 138671982 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 261052 # Number of read requests accepted |
| 38system.physmem.writeReqs 0 # Number of write requests accepted | 38system.physmem.writeReqs 0 # Number of write requests accepted |
| 39system.physmem.readBursts 84617 # Number of DRAM read bursts, including those serviced by the write queue | 39system.physmem.readBursts 261052 # Number of DRAM read bursts, including those serviced by the write queue |
| 40system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 40system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 41system.physmem.bytesReadDRAM 5415488 # Total number of bytes read from DRAM | 41system.physmem.bytesReadDRAM 16707328 # Total number of bytes read from DRAM |
| 42system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 43system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 42system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 43system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 44system.physmem.bytesReadSys 5415488 # Total read bytes from the system interface side | 44system.physmem.bytesReadSys 16707328 # Total read bytes from the system interface side |
| 45system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 49system.physmem.perBankRdBursts::0 956 # Per bank write bursts 50system.physmem.perBankRdBursts::1 811 # Per bank write bursts 51system.physmem.perBankRdBursts::2 834 # Per bank write bursts 52system.physmem.perBankRdBursts::3 2907 # Per bank write bursts 53system.physmem.perBankRdBursts::4 10637 # Per bank write bursts 54system.physmem.perBankRdBursts::5 59817 # Per bank write bursts 55system.physmem.perBankRdBursts::6 152 # Per bank write bursts 56system.physmem.perBankRdBursts::7 259 # Per bank write bursts 57system.physmem.perBankRdBursts::8 225 # Per bank write bursts 58system.physmem.perBankRdBursts::9 303 # Per bank write bursts 59system.physmem.perBankRdBursts::10 3870 # Per bank write bursts 60system.physmem.perBankRdBursts::11 811 # Per bank write bursts 61system.physmem.perBankRdBursts::12 1141 # Per bank write bursts 62system.physmem.perBankRdBursts::13 693 # Per bank write bursts 63system.physmem.perBankRdBursts::14 638 # Per bank write bursts 64system.physmem.perBankRdBursts::15 563 # Per bank write bursts | 49system.physmem.perBankRdBursts::0 1258 # Per bank write bursts 50system.physmem.perBankRdBursts::1 69992 # Per bank write bursts 51system.physmem.perBankRdBursts::2 1296 # Per bank write bursts 52system.physmem.perBankRdBursts::3 10757 # Per bank write bursts 53system.physmem.perBankRdBursts::4 42908 # Per bank write bursts 54system.physmem.perBankRdBursts::5 121820 # Per bank write bursts 55system.physmem.perBankRdBursts::6 160 # Per bank write bursts 56system.physmem.perBankRdBursts::7 266 # Per bank write bursts 57system.physmem.perBankRdBursts::8 224 # Per bank write bursts 58system.physmem.perBankRdBursts::9 562 # Per bank write bursts 59system.physmem.perBankRdBursts::10 7776 # Per bank write bursts 60system.physmem.perBankRdBursts::11 812 # Per bank write bursts 61system.physmem.perBankRdBursts::12 1213 # Per bank write bursts 62system.physmem.perBankRdBursts::13 743 # Per bank write bursts 63system.physmem.perBankRdBursts::14 656 # Per bank write bursts 64system.physmem.perBankRdBursts::15 609 # Per bank write bursts |
| 65system.physmem.perBankWrBursts::0 0 # Per bank write bursts 66system.physmem.perBankWrBursts::1 0 # Per bank write bursts 67system.physmem.perBankWrBursts::2 0 # Per bank write bursts 68system.physmem.perBankWrBursts::3 0 # Per bank write bursts 69system.physmem.perBankWrBursts::4 0 # Per bank write bursts 70system.physmem.perBankWrBursts::5 0 # Per bank write bursts 71system.physmem.perBankWrBursts::6 0 # Per bank write bursts 72system.physmem.perBankWrBursts::7 0 # Per bank write bursts 73system.physmem.perBankWrBursts::8 0 # Per bank write bursts 74system.physmem.perBankWrBursts::9 0 # Per bank write bursts 75system.physmem.perBankWrBursts::10 0 # Per bank write bursts 76system.physmem.perBankWrBursts::11 0 # Per bank write bursts 77system.physmem.perBankWrBursts::12 0 # Per bank write bursts 78system.physmem.perBankWrBursts::13 0 # Per bank write bursts 79system.physmem.perBankWrBursts::14 0 # Per bank write bursts 80system.physmem.perBankWrBursts::15 0 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 65system.physmem.perBankWrBursts::0 0 # Per bank write bursts 66system.physmem.perBankWrBursts::1 0 # Per bank write bursts 67system.physmem.perBankWrBursts::2 0 # Per bank write bursts 68system.physmem.perBankWrBursts::3 0 # Per bank write bursts 69system.physmem.perBankWrBursts::4 0 # Per bank write bursts 70system.physmem.perBankWrBursts::5 0 # Per bank write bursts 71system.physmem.perBankWrBursts::6 0 # Per bank write bursts 72system.physmem.perBankWrBursts::7 0 # Per bank write bursts 73system.physmem.perBankWrBursts::8 0 # Per bank write bursts 74system.physmem.perBankWrBursts::9 0 # Per bank write bursts 75system.physmem.perBankWrBursts::10 0 # Per bank write bursts 76system.physmem.perBankWrBursts::11 0 # Per bank write bursts 77system.physmem.perBankWrBursts::12 0 # Per bank write bursts 78system.physmem.perBankWrBursts::13 0 # Per bank write bursts 79system.physmem.perBankWrBursts::14 0 # Per bank write bursts 80system.physmem.perBankWrBursts::15 0 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 83system.physmem.totGap 111753395000 # Total gap between requests | 83system.physmem.totGap 120480449000 # Total gap between requests |
| 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) | 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 90system.physmem.readPktSize::6 84617 # Read request sizes (log2) | 90system.physmem.readPktSize::6 261052 # Read request sizes (log2) |
| 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 0 # Write request sizes (log2) | 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 98system.physmem.rdQLenPdf::0 64967 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 17796 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 465 # What read queue length does an incoming req see | 98system.physmem.rdQLenPdf::0 204297 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 43283 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 12075 # What read queue length does an incoming req see |
| 101system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see |
| 102system.physmem.rdQLenPdf::4 226 # What read queue length does an incoming req see | 102system.physmem.rdQLenPdf::4 234 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see | 103system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::6 173 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 172 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 172 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 53 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see | 104system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 216 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 113 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see |
| 109system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see | 109system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see |
| 110system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see | 110system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see |
| 111system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see --- 67 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 111system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see --- 67 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 194system.physmem.bytesPerActivate::samples 21291 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 254.217463 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 213.921670 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 155.515771 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::0-127 2572 12.08% 12.08% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-255 7102 33.36% 45.44% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::256-383 8141 38.24% 83.67% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::384-511 1445 6.79% 90.46% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-639 1060 4.98% 95.44% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::640-767 699 3.28% 98.72% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::768-895 33 0.15% 98.88% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::896-1023 27 0.13% 99.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1024-1151 212 1.00% 100.00% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::total 21291 # Bytes accessed per row activation 208system.physmem.totQLat 818886094 # Total ticks spent queuing 209system.physmem.totMemAccLat 2405454844 # Total ticks spent from burst creation until serviced by the DRAM 210system.physmem.totBusLat 423085000 # Total ticks spent in databus transfers 211system.physmem.avgQLat 9677.56 # Average queueing delay per DRAM burst | 194system.physmem.bytesPerActivate::samples 67045 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 249.160415 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 181.717328 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 205.520754 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::0-127 18369 27.40% 27.40% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-255 21159 31.56% 58.96% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::256-383 11457 17.09% 76.05% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::384-511 6629 9.89% 85.93% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-639 4618 6.89% 92.82% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::640-767 2220 3.31% 96.13% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::768-895 1372 2.05% 98.18% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::896-1023 491 0.73% 98.91% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1024-1151 730 1.09% 100.00% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::total 67045 # Bytes accessed per row activation 208system.physmem.totQLat 2500931533 # Total ticks spent queuing 209system.physmem.totMemAccLat 7395656533 # Total ticks spent from burst creation until serviced by the DRAM 210system.physmem.totBusLat 1305260000 # Total ticks spent in databus transfers 211system.physmem.avgQLat 9580.20 # Average queueing delay per DRAM burst |
| 212system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 212system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 213system.physmem.avgMemAccLat 28427.56 # Average memory access latency per DRAM burst 214system.physmem.avgRdBW 48.46 # Average DRAM read bandwidth in MiByte/s | 213system.physmem.avgMemAccLat 28330.20 # Average memory access latency per DRAM burst 214system.physmem.avgRdBW 138.67 # Average DRAM read bandwidth in MiByte/s |
| 215system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 215system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 216system.physmem.avgRdBWSys 48.46 # Average system read bandwidth in MiByte/s | 216system.physmem.avgRdBWSys 138.67 # Average system read bandwidth in MiByte/s |
| 217system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 217system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 219system.physmem.busUtil 0.38 # Data bus utilization in percentage 220system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads | 219system.physmem.busUtil 1.08 # Data bus utilization in percentage 220system.physmem.busUtilRead 1.08 # Data bus utilization in percentage for reads |
| 221system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 221system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 222system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing | 222system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing |
| 223system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 223system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 224system.physmem.readRowHits 63316 # Number of row buffer hits during reads | 224system.physmem.readRowHits 193998 # Number of row buffer hits during reads |
| 225system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 225system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 226system.physmem.readRowHitRate 74.83 # Row buffer hit rate for reads | 226system.physmem.readRowHitRate 74.31 # Row buffer hit rate for reads |
| 227system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 227system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 228system.physmem.avgGap 1320696.73 # Average gap between requests 229system.physmem.pageHitRate 74.83 # Row buffer hit rate, read and write combined 230system.physmem_0.actEnergy 137093040 # Energy for activate commands per rank (pJ) 231system.physmem_0.preEnergy 74802750 # Energy for precharge commands per rank (pJ) 232system.physmem_0.readEnergy 595467600 # Energy for read commands per rank (pJ) | 228system.physmem.avgGap 461518.97 # Average gap between requests 229system.physmem.pageHitRate 74.31 # Row buffer hit rate, read and write combined 230system.physmem_0.actEnergy 469687680 # Energy for activate commands per rank (pJ) 231system.physmem_0.preEnergy 256278000 # Energy for precharge commands per rank (pJ) 232system.physmem_0.readEnergy 1937777400 # Energy for read commands per rank (pJ) |
| 233system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 233system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 234system.physmem_0.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) 235system.physmem_0.actBackEnergy 61580578995 # Energy for active background per rank (pJ) 236system.physmem_0.preBackEnergy 13031079750 # Energy for precharge background per rank (pJ) 237system.physmem_0.totalEnergy 82717875255 # Total energy per rank (pJ) 238system.physmem_0.averagePower 740.214288 # Core power per rank (mW) 239system.physmem_0.memoryStateTime::IDLE 21327892271 # Time in different power states 240system.physmem_0.memoryStateTime::REF 3731520000 # Time in different power states | 234system.physmem_0.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) 235system.physmem_0.actBackEnergy 73664414550 # Energy for active background per rank (pJ) 236system.physmem_0.preBackEnergy 7668236250 # Energy for precharge background per rank (pJ) 237system.physmem_0.totalEnergy 91865342760 # Total energy per rank (pJ) 238system.physmem_0.averagePower 762.514125 # Core power per rank (mW) 239system.physmem_0.memoryStateTime::IDLE 12350213739 # Time in different power states 240system.physmem_0.memoryStateTime::REF 4022980000 # Time in different power states |
| 241system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 241system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 242system.physmem_0.memoryStateTime::ACT 86689152979 # Time in different power states | 242system.physmem_0.memoryStateTime::ACT 104104852261 # Time in different power states |
| 243system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 243system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 244system.physmem_1.actEnergy 23821560 # Energy for activate commands per rank (pJ) 245system.physmem_1.preEnergy 12997875 # Energy for precharge commands per rank (pJ) 246system.physmem_1.readEnergy 64092600 # Energy for read commands per rank (pJ) | 244system.physmem_1.actEnergy 37134720 # Energy for activate commands per rank (pJ) 245system.physmem_1.preEnergy 20262000 # Energy for precharge commands per rank (pJ) 246system.physmem_1.readEnergy 98069400 # Energy for read commands per rank (pJ) |
| 247system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 247system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 248system.physmem_1.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) 249system.physmem_1.actBackEnergy 10878672015 # Energy for active background per rank (pJ) 250system.physmem_1.preBackEnergy 57506417250 # Energy for precharge background per rank (pJ) 251system.physmem_1.totalEnergy 75784854420 # Total energy per rank (pJ) 252system.physmem_1.averagePower 678.173227 # Core power per rank (mW) 253system.physmem_1.memoryStateTime::IDLE 95612479879 # Time in different power states 254system.physmem_1.memoryStateTime::REF 3731520000 # Time in different power states | 248system.physmem_1.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) 249system.physmem_1.actBackEnergy 16939770435 # Energy for active background per rank (pJ) 250system.physmem_1.preBackEnergy 57426696000 # Energy for precharge background per rank (pJ) 251system.physmem_1.totalEnergy 82390881435 # Total energy per rank (pJ) 252system.physmem_1.averagePower 683.872818 # Core power per rank (mW) 253system.physmem_1.memoryStateTime::IDLE 95444315624 # Time in different power states 254system.physmem_1.memoryStateTime::REF 4022980000 # Time in different power states |
| 255system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 255system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 256system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states | 256system.physmem_1.memoryStateTime::ACT 21009739880 # Time in different power states |
| 257system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 257system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 258system.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states 259system.cpu.branchPred.lookups 35971731 # Number of BP lookups 260system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted 261system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect 262system.cpu.branchPred.BTBLookups 17894968 # Number of BTB lookups 263system.cpu.branchPred.BTBHits 13923402 # Number of BTB hits | 258system.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states 259system.cpu.branchPred.lookups 35971487 # Number of BP lookups 260system.cpu.branchPred.condPredicted 19266966 # Number of conditional branches predicted 261system.cpu.branchPred.condIncorrect 984300 # Number of conditional branches incorrect 262system.cpu.branchPred.BTBLookups 17894295 # Number of BTB lookups 263system.cpu.branchPred.BTBHits 13923321 # Number of BTB hits |
| 264system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 264system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 265system.cpu.branchPred.BTBHitPct 77.806241 # BTB Hit Percentage 266system.cpu.branchPred.usedRAS 6951964 # Number of times the RAS was used to get a target. 267system.cpu.branchPred.RASInCorrect 4431 # Number of incorrect RAS predictions. 268system.cpu.branchPred.indirectLookups 2517343 # Number of indirect predictor lookups. 269system.cpu.branchPred.indirectHits 2473442 # Number of indirect target hits. 270system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses. 271system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches. | 265system.cpu.branchPred.BTBHitPct 77.808715 # BTB Hit Percentage 266system.cpu.branchPred.usedRAS 6951891 # Number of times the RAS was used to get a target. 267system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. 268system.cpu.branchPred.indirectLookups 2517210 # Number of indirect predictor lookups. 269system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. 270system.cpu.branchPred.indirectMisses 43855 # Number of indirect misses. 271system.cpu.branchPredindirectMispredicted 128902 # Number of mispredicted indirect branches. |
| 272system.cpu_clk_domain.clock 500 # Clock period in ticks | 272system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 273system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states | 273system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states |
| 274system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 280system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 295system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 296system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 298system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 299system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 300system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 301system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 302system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 274system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 280system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 295system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 296system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 298system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 299system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 300system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 301system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 302system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 303system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states | 303system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states |
| 304system.cpu.dtb.walker.walks 0 # Table walker walks requested 305system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dtb.read_accesses 0 # DTB read accesses 328system.cpu.dtb.write_accesses 0 # DTB write accesses 329system.cpu.dtb.inst_accesses 0 # ITB inst accesses 330system.cpu.dtb.hits 0 # DTB hits 331system.cpu.dtb.misses 0 # DTB misses 332system.cpu.dtb.accesses 0 # DTB accesses | 304system.cpu.dtb.walker.walks 0 # Table walker walks requested 305system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dtb.read_accesses 0 # DTB read accesses 328system.cpu.dtb.write_accesses 0 # DTB write accesses 329system.cpu.dtb.inst_accesses 0 # ITB inst accesses 330system.cpu.dtb.hits 0 # DTB hits 331system.cpu.dtb.misses 0 # DTB misses 332system.cpu.dtb.accesses 0 # DTB accesses |
| 333system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states | 333system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states |
| 334system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 358system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 359system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 360system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 361system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 362system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 334system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 358system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 359system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 360system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 361system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 362system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 363system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states | 363system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states |
| 364system.cpu.itb.walker.walks 0 # Table walker walks requested 365system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 386system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.itb.read_accesses 0 # DTB read accesses 388system.cpu.itb.write_accesses 0 # DTB write accesses 389system.cpu.itb.inst_accesses 0 # ITB inst accesses 390system.cpu.itb.hits 0 # DTB hits 391system.cpu.itb.misses 0 # DTB misses 392system.cpu.itb.accesses 0 # DTB accesses 393system.cpu.workload.num_syscalls 191 # Number of system calls | 364system.cpu.itb.walker.walks 0 # Table walker walks requested 365system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 386system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.itb.read_accesses 0 # DTB read accesses 388system.cpu.itb.write_accesses 0 # DTB write accesses 389system.cpu.itb.inst_accesses 0 # ITB inst accesses 390system.cpu.itb.hits 0 # DTB hits 391system.cpu.itb.misses 0 # DTB misses 392system.cpu.itb.accesses 0 # DTB accesses 393system.cpu.workload.num_syscalls 191 # Number of system calls |
| 394system.cpu.pwrStateResidencyTicks::ON 111753553500 # Cumulative time (in ticks) in various power states 395system.cpu.numCycles 223507108 # number of cpu cycles simulated | 394system.cpu.pwrStateResidencyTicks::ON 120480458500 # Cumulative time (in ticks) in various power states 395system.cpu.numCycles 240960918 # number of cpu cycles simulated |
| 396system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 397system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 396system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 397system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 398system.cpu.fetch.icacheStallCycles 12083599 # Number of cycles fetch is stalled on an Icache miss 399system.cpu.fetch.Insts 309381854 # Number of instructions fetch has processed 400system.cpu.fetch.Branches 35971731 # Number of branches that fetch encountered 401system.cpu.fetch.predictedBranches 23348808 # Number of branches that fetch has predicted taken 402system.cpu.fetch.Cycles 209499863 # Number of cycles fetch has run and was not squashing or blocked 403system.cpu.fetch.SquashCycles 1989645 # Number of cycles fetch has spent squashing 404system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 398system.cpu.fetch.icacheStallCycles 12852393 # Number of cycles fetch is stalled on an Icache miss 399system.cpu.fetch.Insts 309387545 # Number of instructions fetch has processed 400system.cpu.fetch.Branches 35971487 # Number of branches that fetch encountered 401system.cpu.fetch.predictedBranches 23348567 # Number of branches that fetch has predicted taken 402system.cpu.fetch.Cycles 224289895 # Number of cycles fetch has run and was not squashing or blocked 403system.cpu.fetch.SquashCycles 1990323 # Number of cycles fetch has spent squashing 404system.cpu.fetch.MiscStallCycles 1871 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 405system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps | 405system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps |
| 406system.cpu.fetch.IcacheWaitRetryStallCycles 2666 # Number of stall cycles due to full MSHR 407system.cpu.fetch.CacheLines 82203342 # Number of cache lines fetched 408system.cpu.fetch.IcacheSquashes 33398 # Number of outstanding Icache misses that were squashed 409system.cpu.fetch.rateDist::samples 222582301 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::mean 1.671920 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::stdev 1.267628 # Number of instructions fetched each cycle (Total) | 406system.cpu.fetch.IcacheWaitRetryStallCycles 3026 # Number of stall cycles due to full MSHR 407system.cpu.fetch.CacheLines 82204082 # Number of cache lines fetched 408system.cpu.fetch.IcacheSquashes 34266 # Number of outstanding Icache misses that were squashed 409system.cpu.fetch.rateDist::samples 238142439 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::mean 1.562665 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::stdev 1.293284 # Number of instructions fetched each cycle (Total) |
| 412system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 412system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 413system.cpu.fetch.rateDist::0 62373241 28.02% 28.02% # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.rateDist::1 40203334 18.06% 46.08% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::2 28080746 12.62% 58.70% # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::3 91924980 41.30% 100.00% # Number of instructions fetched each cycle (Total) | 413system.cpu.fetch.rateDist::0 77933727 32.73% 32.73% # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.rateDist::1 40203358 16.88% 49.61% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::2 28082672 11.79% 61.40% # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::3 91922682 38.60% 100.00% # Number of instructions fetched each cycle (Total) |
| 417system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 417system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 420system.cpu.fetch.rateDist::total 222582301 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.branchRate 0.160942 # Number of branch fetches per cycle 422system.cpu.fetch.rate 1.384215 # Number of inst fetches per cycle 423system.cpu.decode.IdleCycles 26238985 # Number of cycles decode is idle 424system.cpu.decode.BlockedCycles 73050782 # Number of cycles decode is blocked 425system.cpu.decode.RunCycles 98117127 # Number of cycles decode is running 426system.cpu.decode.UnblockCycles 24314460 # Number of cycles decode is unblocking 427system.cpu.decode.SquashCycles 860947 # Number of cycles decode is squashing 428system.cpu.decode.BranchResolved 6686817 # Number of times decode resolved a branch 429system.cpu.decode.BranchMispred 134221 # Number of times decode detected a branch misprediction 430system.cpu.decode.DecodedInsts 348541423 # Number of instructions handled by decode 431system.cpu.decode.SquashedInsts 3410145 # Number of squashed instructions handled by decode 432system.cpu.rename.SquashCycles 860947 # Number of cycles rename is squashing 433system.cpu.rename.IdleCycles 42548430 # Number of cycles rename is idle 434system.cpu.rename.BlockCycles 23450678 # Number of cycles rename is blocking 435system.cpu.rename.serializeStallCycles 285531 # count of cycles rename stalled for serializing inst 436system.cpu.rename.RunCycles 105165670 # Number of cycles rename is running 437system.cpu.rename.UnblockCycles 50271045 # Number of cycles rename is unblocking 438system.cpu.rename.RenamedInsts 344601348 # Number of instructions processed by rename 439system.cpu.rename.SquashedInsts 1453656 # Number of squashed instructions processed by rename 440system.cpu.rename.ROBFullEvents 7084396 # Number of times rename has blocked due to ROB full 441system.cpu.rename.IQFullEvents 85832 # Number of times rename has blocked due to IQ full 442system.cpu.rename.LQFullEvents 7483674 # Number of times rename has blocked due to LQ full 443system.cpu.rename.SQFullEvents 23725025 # Number of times rename has blocked due to SQ full 444system.cpu.rename.FullRegisterEvents 3279176 # Number of times there has been no free registers 445system.cpu.rename.RenamedOperands 394880845 # Number of destination operands rename has renamed 446system.cpu.rename.RenameLookups 2218133140 # Number of register rename lookups that rename has made 447system.cpu.rename.int_rename_lookups 335914250 # Number of integer rename lookups 448system.cpu.rename.fp_rename_lookups 192916662 # Number of floating rename lookups 449system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed 450system.cpu.rename.UndoneMaps 22650794 # Number of HB maps that are undone due to squashing 451system.cpu.rename.serializingInsts 11588 # count of serializing insts renamed 452system.cpu.rename.tempSerializingInsts 11554 # count of temporary serializing insts renamed 453system.cpu.rename.skidInsts 57533645 # count of insts added to the skid buffer 454system.cpu.memDep0.insertedLoads 89989968 # Number of loads inserted to the mem dependence unit. 455system.cpu.memDep0.insertedStores 84391268 # Number of stores inserted to the mem dependence unit. 456system.cpu.memDep0.conflictingLoads 1975718 # Number of conflicting loads. 457system.cpu.memDep0.conflictingStores 1902358 # Number of conflicting stores. 458system.cpu.iq.iqInstsAdded 343283622 # Number of instructions added to the IQ (excludes non-spec) 459system.cpu.iq.iqNonSpecInstsAdded 22608 # Number of non-speculative instructions added to the IQ 460system.cpu.iq.iqInstsIssued 339469619 # Number of instructions issued 461system.cpu.iq.iqSquashedInstsIssued 966789 # Number of squashed instructions issued 462system.cpu.iq.iqSquashedInstsExamined 15494628 # Number of squashed instructions iterated over during squash; mainly for profiling 463system.cpu.iq.iqSquashedOperandsExamined 37288530 # Number of squashed operands that are examined and possibly removed from graph 464system.cpu.iq.iqSquashedNonSpecRemoved 488 # Number of squashed non-spec instructions that were removed 465system.cpu.iq.issued_per_cycle::samples 222582301 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::mean 1.525142 # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::stdev 1.109331 # Number of insts issued each cycle | 420system.cpu.fetch.rateDist::total 238142439 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.branchRate 0.149283 # Number of branch fetches per cycle 422system.cpu.fetch.rate 1.283974 # Number of inst fetches per cycle 423system.cpu.decode.IdleCycles 26809492 # Number of cycles decode is idle 424system.cpu.decode.BlockedCycles 87975457 # Number of cycles decode is blocked 425system.cpu.decode.RunCycles 98235303 # Number of cycles decode is running 426system.cpu.decode.UnblockCycles 24260898 # Number of cycles decode is unblocking 427system.cpu.decode.SquashCycles 861289 # Number of cycles decode is squashing 428system.cpu.decode.BranchResolved 6686645 # Number of times decode resolved a branch 429system.cpu.decode.BranchMispred 134215 # Number of times decode detected a branch misprediction 430system.cpu.decode.DecodedInsts 348536073 # Number of instructions handled by decode 431system.cpu.decode.SquashedInsts 3411178 # Number of squashed instructions handled by decode 432system.cpu.rename.SquashCycles 861289 # Number of cycles rename is squashing 433system.cpu.rename.IdleCycles 43087679 # Number of cycles rename is idle 434system.cpu.rename.BlockCycles 34729777 # Number of cycles rename is blocking 435system.cpu.rename.serializeStallCycles 287359 # count of cycles rename stalled for serializing inst 436system.cpu.rename.RunCycles 105264108 # Number of cycles rename is running 437system.cpu.rename.UnblockCycles 53912227 # Number of cycles rename is unblocking 438system.cpu.rename.RenamedInsts 344595535 # Number of instructions processed by rename 439system.cpu.rename.SquashedInsts 1451317 # Number of squashed instructions processed by rename 440system.cpu.rename.ROBFullEvents 7117459 # Number of times rename has blocked due to ROB full 441system.cpu.rename.IQFullEvents 85486 # Number of times rename has blocked due to IQ full 442system.cpu.rename.LQFullEvents 7456793 # Number of times rename has blocked due to LQ full 443system.cpu.rename.SQFullEvents 27429966 # Number of times rename has blocked due to SQ full 444system.cpu.rename.FullRegisterEvents 3277218 # Number of times there has been no free registers 445system.cpu.rename.RenamedOperands 394867605 # Number of destination operands rename has renamed 446system.cpu.rename.RenameLookups 2218081796 # Number of register rename lookups that rename has made 447system.cpu.rename.int_rename_lookups 335910446 # Number of integer rename lookups 448system.cpu.rename.fp_rename_lookups 192911530 # Number of floating rename lookups 449system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed 450system.cpu.rename.UndoneMaps 22637557 # Number of HB maps that are undone due to squashing 451system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed 452system.cpu.rename.tempSerializingInsts 11573 # count of temporary serializing insts renamed 453system.cpu.rename.skidInsts 57394706 # count of insts added to the skid buffer 454system.cpu.memDep0.insertedLoads 89984018 # Number of loads inserted to the mem dependence unit. 455system.cpu.memDep0.insertedStores 84392471 # Number of stores inserted to the mem dependence unit. 456system.cpu.memDep0.conflictingLoads 1976841 # Number of conflicting loads. 457system.cpu.memDep0.conflictingStores 1898355 # Number of conflicting stores. 458system.cpu.iq.iqInstsAdded 343274386 # Number of instructions added to the IQ (excludes non-spec) 459system.cpu.iq.iqNonSpecInstsAdded 22623 # Number of non-speculative instructions added to the IQ 460system.cpu.iq.iqInstsIssued 339465004 # Number of instructions issued 461system.cpu.iq.iqSquashedInstsIssued 967637 # Number of squashed instructions issued 462system.cpu.iq.iqSquashedInstsExamined 15485409 # Number of squashed instructions iterated over during squash; mainly for profiling 463system.cpu.iq.iqSquashedOperandsExamined 37250778 # Number of squashed operands that are examined and possibly removed from graph 464system.cpu.iq.iqSquashedNonSpecRemoved 503 # Number of squashed non-spec instructions that were removed 465system.cpu.iq.issued_per_cycle::samples 238142439 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::mean 1.425470 # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::stdev 1.136916 # Number of insts issued each cycle |
| 468system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 468system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 469system.cpu.iq.issued_per_cycle::0 42440680 19.07% 19.07% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::1 76122495 34.20% 53.27% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::2 59389973 26.68% 79.95% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::3 34692267 15.59% 95.54% # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::4 9226095 4.15% 99.68% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::5 678749 0.30% 99.99% # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::6 32042 0.01% 100.00% # Number of insts issued each cycle | 469system.cpu.iq.issued_per_cycle::0 57979720 24.35% 24.35% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::1 76155774 31.98% 56.33% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::2 59457503 24.97% 81.29% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::3 34550396 14.51% 95.80% # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::4 9286722 3.90% 99.70% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::5 677796 0.28% 99.99% # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::6 34528 0.01% 100.00% # Number of insts issued each cycle |
| 476system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle | 476system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle |
| 481system.cpu.iq.issued_per_cycle::total 222582301 # Number of insts issued each cycle | 481system.cpu.iq.issued_per_cycle::total 238142439 # Number of insts issued each cycle |
| 482system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 482system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 483system.cpu.iq.fu_full::IntAlu 9228112 7.75% 7.75% # attempts to use FU when none available 484system.cpu.iq.fu_full::IntMult 7358 0.01% 7.75% # attempts to use FU when none available 485system.cpu.iq.fu_full::IntDiv 0 0.00% 7.75% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.75% # attempts to use FU when none available 487system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.75% # attempts to use FU when none available 488system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.75% # attempts to use FU when none available 489system.cpu.iq.fu_full::FloatMult 0 0.00% 7.75% # attempts to use FU when none available 490system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.75% # attempts to use FU when none available 491system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.75% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.75% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.75% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.75% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.75% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.75% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.75% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdMult 0 0.00% 7.75% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.75% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdShift 0 0.00% 7.75% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.75% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.75% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatAdd 237798 0.20% 7.95% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.95% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatCmp 147681 0.12% 8.08% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatCvt 70485 0.06% 8.14% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdFloatDiv 67886 0.06% 8.19% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdFloatMisc 638269 0.54% 8.73% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdFloatMult 297789 0.25% 8.98% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdFloatMultAcc 542439 0.46% 9.44% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available 512system.cpu.iq.fu_full::MemRead 51542568 43.28% 52.71% # attempts to use FU when none available 513system.cpu.iq.fu_full::MemWrite 56315471 47.29% 100.00% # attempts to use FU when none available | 483system.cpu.iq.fu_full::IntAlu 9217758 7.75% 7.75% # attempts to use FU when none available 484system.cpu.iq.fu_full::IntMult 7319 0.01% 7.76% # attempts to use FU when none available 485system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available 487system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available 488system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.76% # attempts to use FU when none available 489system.cpu.iq.fu_full::FloatMult 0 0.00% 7.76% # attempts to use FU when none available 490system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.76% # attempts to use FU when none available 491system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.76% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.76% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.76% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.76% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.76% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.76% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.76% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdMult 0 0.00% 7.76% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatAdd 238781 0.20% 7.96% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatCmp 138932 0.12% 8.08% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatCvt 70694 0.06% 8.13% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdFloatDiv 68373 0.06% 8.19% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdFloatMisc 637081 0.54% 8.73% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdFloatMult 296736 0.25% 8.98% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdFloatMultAcc 541785 0.46% 9.43% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available 512system.cpu.iq.fu_full::MemRead 51510154 43.32% 52.75% # attempts to use FU when none available 513system.cpu.iq.fu_full::MemWrite 56187310 47.25% 100.00% # attempts to use FU when none available |
| 514system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 515system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 516system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 514system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 515system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 516system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 517system.cpu.iq.FU_type_0::IntAlu 108184507 31.87% 31.87% # Type of FU issued 518system.cpu.iq.FU_type_0::IntMult 2148145 0.63% 32.50% # Type of FU issued | 517system.cpu.iq.FU_type_0::IntAlu 108183295 31.87% 31.87% # Type of FU issued 518system.cpu.iq.FU_type_0::IntMult 2148337 0.63% 32.50% # Type of FU issued |
| 519system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued 521system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued 522system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.50% # Type of FU issued 523system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.50% # Type of FU issued 524system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.50% # Type of FU issued 525system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.50% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.50% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.50% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.50% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.50% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.50% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.50% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.50% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued | 519system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued 521system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued 522system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.50% # Type of FU issued 523system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.50% # Type of FU issued 524system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.50% # Type of FU issued 525system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.50% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.50% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.50% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.50% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.50% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.50% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.50% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.50% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued |
| 537system.cpu.iq.FU_type_0::SimdFloatAdd 6792731 2.00% 34.50% # Type of FU issued | 537system.cpu.iq.FU_type_0::SimdFloatAdd 6792696 2.00% 34.50% # Type of FU issued |
| 538system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued | 538system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued |
| 539system.cpu.iq.FU_type_0::SimdFloatCmp 8635726 2.54% 37.05% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatCvt 3210403 0.95% 37.99% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdFloatDiv 1592905 0.47% 38.46% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdFloatMisc 20864008 6.15% 44.61% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdFloatMult 7178651 2.11% 46.72% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141492 2.10% 48.83% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdFloatSqrt 175295 0.05% 48.88% # Type of FU issued 546system.cpu.iq.FU_type_0::MemRead 90027492 26.52% 75.40% # Type of FU issued 547system.cpu.iq.FU_type_0::MemWrite 83518264 24.60% 100.00% # Type of FU issued | 539system.cpu.iq.FU_type_0::SimdFloatCmp 8634939 2.54% 37.05% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatCvt 3210556 0.95% 37.99% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdFloatMisc 20863290 6.15% 44.61% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdFloatMult 7179112 2.11% 46.72% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141893 2.10% 48.83% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued 546system.cpu.iq.FU_type_0::MemRead 90024001 26.52% 75.40% # Type of FU issued 547system.cpu.iq.FU_type_0::MemWrite 83518602 24.60% 100.00% # Type of FU issued |
| 548system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 549system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 548system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 549system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 550system.cpu.iq.FU_type_0::total 339469619 # Type of FU issued 551system.cpu.iq.rate 1.518831 # Inst issue rate 552system.cpu.iq.fu_busy_cnt 119095856 # FU busy when requested 553system.cpu.iq.fu_busy_rate 0.350829 # FU busy rate (busy events/executed inst) 554system.cpu.iq.int_inst_queue_reads 738018306 # Number of integer instruction queue reads 555system.cpu.iq.int_inst_queue_writes 235153924 # Number of integer instruction queue writes 556system.cpu.iq.int_inst_queue_wakeup_accesses 219171367 # Number of integer instruction queue wakeup accesses 557system.cpu.iq.fp_inst_queue_reads 283565878 # Number of floating instruction queue reads 558system.cpu.iq.fp_inst_queue_writes 123658767 # Number of floating instruction queue writes 559system.cpu.iq.fp_inst_queue_wakeup_accesses 116921576 # Number of floating instruction queue wakeup accesses 560system.cpu.iq.int_alu_accesses 293614389 # Number of integer alu accesses 561system.cpu.iq.fp_alu_accesses 164951086 # Number of floating point alu accesses 562system.cpu.iew.lsq.thread0.forwLoads 5389138 # Number of loads that had data forwarded from stores | 550system.cpu.iq.FU_type_0::total 339465004 # Type of FU issued 551system.cpu.iq.rate 1.408797 # Inst issue rate 552system.cpu.iq.fu_busy_cnt 118914923 # FU busy when requested 553system.cpu.iq.fu_busy_rate 0.350301 # FU busy rate (busy events/executed inst) 554system.cpu.iq.int_inst_queue_reads 753593457 # Number of integer instruction queue reads 555system.cpu.iq.int_inst_queue_writes 235149136 # Number of integer instruction queue writes 556system.cpu.iq.int_inst_queue_wakeup_accesses 219170609 # Number of integer instruction queue wakeup accesses 557system.cpu.iq.fp_inst_queue_reads 283361550 # Number of floating instruction queue reads 558system.cpu.iq.fp_inst_queue_writes 123645361 # Number of floating instruction queue writes 559system.cpu.iq.fp_inst_queue_wakeup_accesses 116917491 # Number of floating instruction queue wakeup accesses 560system.cpu.iq.int_alu_accesses 293630516 # Number of integer alu accesses 561system.cpu.iq.fp_alu_accesses 164749411 # Number of floating point alu accesses 562system.cpu.iew.lsq.thread0.forwLoads 5409371 # Number of loads that had data forwarded from stores |
| 563system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 563system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 564system.cpu.iew.lsq.thread0.squashedLoads 4257693 # Number of loads squashed 565system.cpu.iew.lsq.thread0.ignoredResponses 7295 # Number of memory responses ignored because the instruction is squashed 566system.cpu.iew.lsq.thread0.memOrderViolation 11836 # Number of memory ordering violations 567system.cpu.iew.lsq.thread0.squashedStores 2015651 # Number of stores squashed | 564system.cpu.iew.lsq.thread0.squashedLoads 4251743 # Number of loads squashed 565system.cpu.iew.lsq.thread0.ignoredResponses 7382 # Number of memory responses ignored because the instruction is squashed 566system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations 567system.cpu.iew.lsq.thread0.squashedStores 2016854 # Number of stores squashed |
| 568system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 569system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 568system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 569system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 570system.cpu.iew.lsq.thread0.rescheduledLoads 126905 # Number of loads that were rescheduled 571system.cpu.iew.lsq.thread0.cacheBlocked 613909 # Number of times an access to memory failed due to the cache being blocked | 570system.cpu.iew.lsq.thread0.rescheduledLoads 126951 # Number of loads that were rescheduled 571system.cpu.iew.lsq.thread0.cacheBlocked 613385 # Number of times an access to memory failed due to the cache being blocked |
| 572system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 572system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 573system.cpu.iew.iewSquashCycles 860947 # Number of cycles IEW is squashing 574system.cpu.iew.iewBlockCycles 1344821 # Number of cycles IEW is blocking 575system.cpu.iew.iewUnblockCycles 736472 # Number of cycles IEW is unblocking 576system.cpu.iew.iewDispatchedInsts 343307622 # Number of instructions dispatched to IQ | 573system.cpu.iew.iewSquashCycles 861289 # Number of cycles IEW is squashing 574system.cpu.iew.iewBlockCycles 1346418 # Number of cycles IEW is blocking 575system.cpu.iew.iewUnblockCycles 1223561 # Number of cycles IEW is unblocking 576system.cpu.iew.iewDispatchedInsts 343298428 # Number of instructions dispatched to IQ |
| 577system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 577system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 578system.cpu.iew.iewDispLoadInsts 89989968 # Number of dispatched load instructions 579system.cpu.iew.iewDispStoreInsts 84391268 # Number of dispatched store instructions 580system.cpu.iew.iewDispNonSpecInsts 11575 # Number of dispatched non-speculative instructions 581system.cpu.iew.iewIQFullEvents 7371 # Number of times the IQ has become full, causing a stall 582system.cpu.iew.iewLSQFullEvents 729404 # Number of times the LSQ has become full, causing a stall 583system.cpu.iew.memOrderViolationEvents 11836 # Number of memory order violations 584system.cpu.iew.predictedTakenIncorrect 437891 # Number of branches that were predicted taken incorrectly 585system.cpu.iew.predictedNotTakenIncorrect 454375 # Number of branches that were predicted not taken incorrectly 586system.cpu.iew.branchMispredicts 892266 # Number of branch mispredicts detected at execute 587system.cpu.iew.iewExecutedInsts 337441545 # Number of executed instructions 588system.cpu.iew.iewExecLoadInsts 89439870 # Number of load instructions executed 589system.cpu.iew.iewExecSquashedInsts 2028074 # Number of squashed instructions skipped in execute | 578system.cpu.iew.iewDispLoadInsts 89984018 # Number of dispatched load instructions 579system.cpu.iew.iewDispStoreInsts 84392471 # Number of dispatched store instructions 580system.cpu.iew.iewDispNonSpecInsts 11590 # Number of dispatched non-speculative instructions 581system.cpu.iew.iewIQFullEvents 7654 # Number of times the IQ has become full, causing a stall 582system.cpu.iew.iewLSQFullEvents 1216581 # Number of times the LSQ has become full, causing a stall 583system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations 584system.cpu.iew.predictedTakenIncorrect 438027 # Number of branches that were predicted taken incorrectly 585system.cpu.iew.predictedNotTakenIncorrect 454511 # Number of branches that were predicted not taken incorrectly 586system.cpu.iew.branchMispredicts 892538 # Number of branch mispredicts detected at execute 587system.cpu.iew.iewExecutedInsts 337435973 # Number of executed instructions 588system.cpu.iew.iewExecLoadInsts 89435470 # Number of load instructions executed 589system.cpu.iew.iewExecSquashedInsts 2029031 # Number of squashed instructions skipped in execute |
| 590system.cpu.iew.exec_swp 0 # number of swp insts executed | 590system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 591system.cpu.iew.exec_nop 1392 # number of nop insts executed 592system.cpu.iew.exec_refs 172567373 # number of memory reference insts executed 593system.cpu.iew.exec_branches 31555849 # Number of branches executed 594system.cpu.iew.exec_stores 83127503 # Number of stores executed 595system.cpu.iew.exec_rate 1.509758 # Inst execution rate 596system.cpu.iew.wb_sent 336239137 # cumulative count of insts sent to commit 597system.cpu.iew.wb_count 336092943 # cumulative count of insts written-back 598system.cpu.iew.wb_producers 151867680 # num instructions producing a value 599system.cpu.iew.wb_consumers 263704827 # num instructions consuming a value 600system.cpu.iew.wb_rate 1.503724 # insts written-back per cycle 601system.cpu.iew.wb_fanout 0.575900 # average fanout of values written-back 602system.cpu.commit.commitSquashedInsts 14172678 # The number of squashed insts skipped by commit | 591system.cpu.iew.exec_nop 1419 # number of nop insts executed 592system.cpu.iew.exec_refs 172563167 # number of memory reference insts executed 593system.cpu.iew.exec_branches 31555788 # Number of branches executed 594system.cpu.iew.exec_stores 83127697 # Number of stores executed 595system.cpu.iew.exec_rate 1.400376 # Inst execution rate 596system.cpu.iew.wb_sent 336234414 # cumulative count of insts sent to commit 597system.cpu.iew.wb_count 336088100 # cumulative count of insts written-back 598system.cpu.iew.wb_producers 151781597 # num instructions producing a value 599system.cpu.iew.wb_consumers 263546089 # num instructions consuming a value 600system.cpu.iew.wb_rate 1.394783 # insts written-back per cycle 601system.cpu.iew.wb_fanout 0.575921 # average fanout of values written-back 602system.cpu.commit.commitSquashedInsts 14163176 # The number of squashed insts skipped by commit |
| 603system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards | 603system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards |
| 604system.cpu.commit.branchMispredicts 850314 # The number of times a branch was mispredicted 605system.cpu.commit.committed_per_cycle::samples 220392023 # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::mean 1.487405 # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::stdev 2.078236 # Number of insts commited each cycle | 604system.cpu.commit.branchMispredicts 850428 # The number of times a branch was mispredicted 605system.cpu.commit.committed_per_cycle::samples 235953046 # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::mean 1.389311 # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::stdev 2.042233 # Number of insts commited each cycle |
| 608system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 608system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 609system.cpu.commit.committed_per_cycle::0 89247998 40.50% 40.50% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::1 67546822 30.65% 71.14% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::2 20918501 9.49% 80.64% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::3 13253983 6.01% 86.65% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::4 8642695 3.92% 90.57% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::5 4496391 2.04% 92.61% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::6 3033426 1.38% 93.99% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::7 2604506 1.18% 95.17% # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::8 10647701 4.83% 100.00% # Number of insts commited each cycle | 609system.cpu.commit.committed_per_cycle::0 104793604 44.41% 44.41% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::1 67594704 28.65% 73.06% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::2 20883417 8.85% 81.91% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::3 13239055 5.61% 87.52% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::4 8655759 3.67% 91.19% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::5 4517031 1.91% 93.10% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::6 3019754 1.28% 94.38% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::7 2590982 1.10% 95.48% # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::8 10658740 4.52% 100.00% # Number of insts commited each cycle |
| 618system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 618system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 621system.cpu.commit.committed_per_cycle::total 220392023 # Number of insts commited each cycle 622system.cpu.commit.committedInsts 273037832 # Number of instructions committed 623system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed | 621system.cpu.commit.committed_per_cycle::total 235953046 # Number of insts commited each cycle 622system.cpu.commit.committedInsts 273037830 # Number of instructions committed 623system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed |
| 624system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 625system.cpu.commit.refs 168107892 # Number of memory references committed 626system.cpu.commit.loads 85732275 # Number of loads committed 627system.cpu.commit.membars 11033 # Number of memory barriers committed | 624system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 625system.cpu.commit.refs 168107892 # Number of memory references committed 626system.cpu.commit.loads 85732275 # Number of loads committed 627system.cpu.commit.membars 11033 # Number of memory barriers committed |
| 628system.cpu.commit.branches 30563526 # Number of branches committed | 628system.cpu.commit.branches 30563525 # Number of branches committed |
| 629system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. | 629system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. |
| 630system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. | 630system.cpu.commit.int_insts 258331703 # Number of committed integer instructions. |
| 631system.cpu.commit.function_calls 6225114 # Number of function calls committed. 632system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 631system.cpu.commit.function_calls 6225114 # Number of function calls committed. 632system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 633system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction | 633system.cpu.commit.op_class_0::IntAlu 104312485 31.82% 31.82% # Class of committed instruction |
| 634system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction 635system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 636system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 637system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 638system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 639system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction 640system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction 641system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction --- 16 unchanged lines hidden (view full) --- 658system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 662system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 663system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 664system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 665system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 634system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction 635system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 636system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 637system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 638system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 639system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction 640system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction 641system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction --- 16 unchanged lines hidden (view full) --- 658system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 662system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 663system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 664system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 665system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 666system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction 667system.cpu.commit.bw_lim_events 10647701 # number cycles where commit BW limit reached 668system.cpu.rob.rob_reads 551726691 # The number of ROB reads 669system.cpu.rob.rob_writes 686162246 # The number of ROB writes 670system.cpu.timesIdled 18335 # Number of times that the entire CPU went into an idle state and unscheduled itself 671system.cpu.idleCycles 924807 # Total number of cycles that the CPU has spent unscheduled due to idling 672system.cpu.committedInsts 273037220 # Number of Instructions Simulated 673system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated 674system.cpu.cpi 0.818596 # CPI: Cycles Per Instruction 675system.cpu.cpi_total 0.818596 # CPI: Total CPI of All Threads 676system.cpu.ipc 1.221604 # IPC: Instructions Per Cycle 677system.cpu.ipc_total 1.221604 # IPC: Total IPC of All Threads 678system.cpu.int_regfile_reads 325161919 # number of integer regfile reads 679system.cpu.int_regfile_writes 134094717 # number of integer regfile writes 680system.cpu.fp_regfile_reads 186641875 # number of floating regfile reads 681system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes 682system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads 683system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes 684system.cpu.misc_regfile_reads 1056766062 # number of misc regfile reads | 666system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction 667system.cpu.commit.bw_lim_events 10658740 # number cycles where commit BW limit reached 668system.cpu.rob.rob_reads 567267171 # The number of ROB reads 669system.cpu.rob.rob_writes 686142351 # The number of ROB writes 670system.cpu.timesIdled 39413 # Number of times that the entire CPU went into an idle state and unscheduled itself 671system.cpu.idleCycles 2818479 # Total number of cycles that the CPU has spent unscheduled due to idling 672system.cpu.committedInsts 273037218 # Number of Instructions Simulated 673system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated 674system.cpu.cpi 0.882520 # CPI: Cycles Per Instruction 675system.cpu.cpi_total 0.882520 # CPI: Total CPI of All Threads 676system.cpu.ipc 1.133118 # IPC: Instructions Per Cycle 677system.cpu.ipc_total 1.133118 # IPC: Total IPC of All Threads 678system.cpu.int_regfile_reads 325162337 # number of integer regfile reads 679system.cpu.int_regfile_writes 134093699 # number of integer regfile writes 680system.cpu.fp_regfile_reads 186638060 # number of floating regfile reads 681system.cpu.fp_regfile_writes 131662989 # number of floating regfile writes 682system.cpu.cc_regfile_reads 1279404689 # number of cc regfile reads 683system.cpu.cc_regfile_writes 80058303 # number of cc regfile writes 684system.cpu.misc_regfile_reads 1056730531 # number of misc regfile reads |
| 685system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes | 685system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes |
| 686system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states 687system.cpu.dcache.tags.replacements 1542955 # number of replacements 688system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use 689system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks. 690system.cpu.dcache.tags.sampled_refs 1543467 # Sample count of references to valid blocks. 691system.cpu.dcache.tags.avg_refs 105.008222 # Average number of references to valid blocks. 692system.cpu.dcache.tags.warmup_cycle 85416000 # Cycle when the warmup percentage was hit. 693system.cpu.dcache.tags.occ_blocks::cpu.data 511.836799 # Average occupied blocks per requestor 694system.cpu.dcache.tags.occ_percent::cpu.data 0.999681 # Average percentage of cache occupancy 695system.cpu.dcache.tags.occ_percent::total 0.999681 # Average percentage of cache occupancy | 686system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states 687system.cpu.dcache.tags.replacements 1542807 # number of replacements 688system.cpu.dcache.tags.tagsinuse 511.846983 # Cycle average of tags in use 689system.cpu.dcache.tags.total_refs 162052499 # Total number of references to valid blocks. 690system.cpu.dcache.tags.sampled_refs 1543319 # Sample count of references to valid blocks. 691system.cpu.dcache.tags.avg_refs 105.002594 # Average number of references to valid blocks. 692system.cpu.dcache.tags.warmup_cycle 87321000 # Cycle when the warmup percentage was hit. 693system.cpu.dcache.tags.occ_blocks::cpu.data 511.846983 # Average occupied blocks per requestor 694system.cpu.dcache.tags.occ_percent::cpu.data 0.999701 # Average percentage of cache occupancy 695system.cpu.dcache.tags.occ_percent::total 0.999701 # Average percentage of cache occupancy |
| 696system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 696system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 697system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 698system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id | 697system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 698system.cpu.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id |
| 699system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id 700system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 701system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 699system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id 700system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 701system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 702system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses 703system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses 704system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states 705system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits 706system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits 707system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits 708system.cpu.dcache.WriteReq_hits::total 80920030 # number of WriteReq hits 709system.cpu.dcache.SoftPFReq_hits::cpu.data 69611 # number of SoftPFReq hits 710system.cpu.dcache.SoftPFReq_hits::total 69611 # number of SoftPFReq hits 711system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits 712system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits | 702system.cpu.dcache.tags.tag_accesses 333478959 # Number of tag accesses 703system.cpu.dcache.tags.data_accesses 333478959 # Number of data accesses 704system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states 705system.cpu.dcache.ReadReq_hits::cpu.data 81039652 # number of ReadReq hits 706system.cpu.dcache.ReadReq_hits::total 81039652 # number of ReadReq hits 707system.cpu.dcache.WriteReq_hits::cpu.data 80921351 # number of WriteReq hits 708system.cpu.dcache.WriteReq_hits::total 80921351 # number of WriteReq hits 709system.cpu.dcache.SoftPFReq_hits::cpu.data 69633 # number of SoftPFReq hits 710system.cpu.dcache.SoftPFReq_hits::total 69633 # number of SoftPFReq hits 711system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits 712system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits |
| 713system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 714system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits | 713system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 714system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits |
| 715system.cpu.dcache.demand_hits::cpu.data 161985266 # number of demand (read+write) hits 716system.cpu.dcache.demand_hits::total 161985266 # number of demand (read+write) hits 717system.cpu.dcache.overall_hits::cpu.data 162054877 # number of overall hits 718system.cpu.dcache.overall_hits::total 162054877 # number of overall hits 719system.cpu.dcache.ReadReq_misses::cpu.data 2782957 # number of ReadReq misses 720system.cpu.dcache.ReadReq_misses::total 2782957 # number of ReadReq misses 721system.cpu.dcache.WriteReq_misses::cpu.data 1132669 # number of WriteReq misses 722system.cpu.dcache.WriteReq_misses::total 1132669 # number of WriteReq misses | 715system.cpu.dcache.demand_hits::cpu.data 161961003 # number of demand (read+write) hits 716system.cpu.dcache.demand_hits::total 161961003 # number of demand (read+write) hits 717system.cpu.dcache.overall_hits::cpu.data 162030636 # number of overall hits 718system.cpu.dcache.overall_hits::total 162030636 # number of overall hits 719system.cpu.dcache.ReadReq_misses::cpu.data 2784011 # number of ReadReq misses 720system.cpu.dcache.ReadReq_misses::total 2784011 # number of ReadReq misses 721system.cpu.dcache.WriteReq_misses::cpu.data 1131348 # number of WriteReq misses 722system.cpu.dcache.WriteReq_misses::total 1131348 # number of WriteReq misses |
| 723system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses 724system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses 725system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 726system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses | 723system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses 724system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses 725system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 726system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses |
| 727system.cpu.dcache.demand_misses::cpu.data 3915626 # number of demand (read+write) misses 728system.cpu.dcache.demand_misses::total 3915626 # number of demand (read+write) misses 729system.cpu.dcache.overall_misses::cpu.data 3915644 # number of overall misses 730system.cpu.dcache.overall_misses::total 3915644 # number of overall misses 731system.cpu.dcache.ReadReq_miss_latency::cpu.data 31092984500 # number of ReadReq miss cycles 732system.cpu.dcache.ReadReq_miss_latency::total 31092984500 # number of ReadReq miss cycles 733system.cpu.dcache.WriteReq_miss_latency::cpu.data 9127104911 # number of WriteReq miss cycles 734system.cpu.dcache.WriteReq_miss_latency::total 9127104911 # number of WriteReq miss cycles 735system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 182000 # number of LoadLockedReq miss cycles 736system.cpu.dcache.LoadLockedReq_miss_latency::total 182000 # number of LoadLockedReq miss cycles 737system.cpu.dcache.demand_miss_latency::cpu.data 40220089411 # number of demand (read+write) miss cycles 738system.cpu.dcache.demand_miss_latency::total 40220089411 # number of demand (read+write) miss cycles 739system.cpu.dcache.overall_miss_latency::cpu.data 40220089411 # number of overall miss cycles 740system.cpu.dcache.overall_miss_latency::total 40220089411 # number of overall miss cycles 741system.cpu.dcache.ReadReq_accesses::cpu.data 83848193 # number of ReadReq accesses(hits+misses) 742system.cpu.dcache.ReadReq_accesses::total 83848193 # number of ReadReq accesses(hits+misses) | 727system.cpu.dcache.demand_misses::cpu.data 3915359 # number of demand (read+write) misses 728system.cpu.dcache.demand_misses::total 3915359 # number of demand (read+write) misses 729system.cpu.dcache.overall_misses::cpu.data 3915377 # number of overall misses 730system.cpu.dcache.overall_misses::total 3915377 # number of overall misses 731system.cpu.dcache.ReadReq_miss_latency::cpu.data 45256653500 # number of ReadReq miss cycles 732system.cpu.dcache.ReadReq_miss_latency::total 45256653500 # number of ReadReq miss cycles 733system.cpu.dcache.WriteReq_miss_latency::cpu.data 9138834402 # number of WriteReq miss cycles 734system.cpu.dcache.WriteReq_miss_latency::total 9138834402 # number of WriteReq miss cycles 735system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184000 # number of LoadLockedReq miss cycles 736system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles 737system.cpu.dcache.demand_miss_latency::cpu.data 54395487902 # number of demand (read+write) miss cycles 738system.cpu.dcache.demand_miss_latency::total 54395487902 # number of demand (read+write) miss cycles 739system.cpu.dcache.overall_miss_latency::cpu.data 54395487902 # number of overall miss cycles 740system.cpu.dcache.overall_miss_latency::total 54395487902 # number of overall miss cycles 741system.cpu.dcache.ReadReq_accesses::cpu.data 83823663 # number of ReadReq accesses(hits+misses) 742system.cpu.dcache.ReadReq_accesses::total 83823663 # number of ReadReq accesses(hits+misses) |
| 743system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 744system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) | 743system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 744system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) |
| 745system.cpu.dcache.SoftPFReq_accesses::cpu.data 69629 # number of SoftPFReq accesses(hits+misses) 746system.cpu.dcache.SoftPFReq_accesses::total 69629 # number of SoftPFReq accesses(hits+misses) 747system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses) 748system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses) | 745system.cpu.dcache.SoftPFReq_accesses::cpu.data 69651 # number of SoftPFReq accesses(hits+misses) 746system.cpu.dcache.SoftPFReq_accesses::total 69651 # number of SoftPFReq accesses(hits+misses) 747system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) 748system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) |
| 749system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 750system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) | 749system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 750system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) |
| 751system.cpu.dcache.demand_accesses::cpu.data 165900892 # number of demand (read+write) accesses 752system.cpu.dcache.demand_accesses::total 165900892 # number of demand (read+write) accesses 753system.cpu.dcache.overall_accesses::cpu.data 165970521 # number of overall (read+write) accesses 754system.cpu.dcache.overall_accesses::total 165970521 # number of overall (read+write) accesses 755system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033190 # miss rate for ReadReq accesses 756system.cpu.dcache.ReadReq_miss_rate::total 0.033190 # miss rate for ReadReq accesses 757system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013804 # miss rate for WriteReq accesses 758system.cpu.dcache.WriteReq_miss_rate::total 0.013804 # miss rate for WriteReq accesses 759system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000259 # miss rate for SoftPFReq accesses 760system.cpu.dcache.SoftPFReq_miss_rate::total 0.000259 # miss rate for SoftPFReq accesses | 751system.cpu.dcache.demand_accesses::cpu.data 165876362 # number of demand (read+write) accesses 752system.cpu.dcache.demand_accesses::total 165876362 # number of demand (read+write) accesses 753system.cpu.dcache.overall_accesses::cpu.data 165946013 # number of overall (read+write) accesses 754system.cpu.dcache.overall_accesses::total 165946013 # number of overall (read+write) accesses 755system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033213 # miss rate for ReadReq accesses 756system.cpu.dcache.ReadReq_miss_rate::total 0.033213 # miss rate for ReadReq accesses 757system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses 758system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses 759system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses 760system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses |
| 761system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses 762system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses | 761system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses 762system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses |
| 763system.cpu.dcache.demand_miss_rate::cpu.data 0.023602 # miss rate for demand accesses 764system.cpu.dcache.demand_miss_rate::total 0.023602 # miss rate for demand accesses 765system.cpu.dcache.overall_miss_rate::cpu.data 0.023592 # miss rate for overall accesses 766system.cpu.dcache.overall_miss_rate::total 0.023592 # miss rate for overall accesses 767system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11172.642804 # average ReadReq miss latency 768system.cpu.dcache.ReadReq_avg_miss_latency::total 11172.642804 # average ReadReq miss latency 769system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8058.051303 # average WriteReq miss latency 770system.cpu.dcache.WriteReq_avg_miss_latency::total 8058.051303 # average WriteReq miss latency 771system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45500 # average LoadLockedReq miss latency 772system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45500 # average LoadLockedReq miss latency 773system.cpu.dcache.demand_avg_miss_latency::cpu.data 10271.688208 # average overall miss latency 774system.cpu.dcache.demand_avg_miss_latency::total 10271.688208 # average overall miss latency 775system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990 # average overall miss latency 776system.cpu.dcache.overall_avg_miss_latency::total 10271.640990 # average overall miss latency | 763system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 # miss rate for demand accesses 764system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses 765system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses 766system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses 767system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16255.917631 # average ReadReq miss latency 768system.cpu.dcache.ReadReq_avg_miss_latency::total 16255.917631 # average ReadReq miss latency 769system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8077.827867 # average WriteReq miss latency 770system.cpu.dcache.WriteReq_avg_miss_latency::total 8077.827867 # average WriteReq miss latency 771system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 46000 # average LoadLockedReq miss latency 772system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 46000 # average LoadLockedReq miss latency 773system.cpu.dcache.demand_avg_miss_latency::cpu.data 13892.848115 # average overall miss latency 774system.cpu.dcache.demand_avg_miss_latency::total 13892.848115 # average overall miss latency 775system.cpu.dcache.overall_avg_miss_latency::cpu.data 13892.784246 # average overall miss latency 776system.cpu.dcache.overall_avg_miss_latency::total 13892.784246 # average overall miss latency |
| 777system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 777system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 778system.cpu.dcache.blocked_cycles::no_targets 1079488 # number of cycles access was blocked | 778system.cpu.dcache.blocked_cycles::no_targets 1086145 # number of cycles access was blocked |
| 779system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked | 779system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 780system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked | 780system.cpu.dcache.blocked::no_targets 136219 # number of cycles access was blocked |
| 781system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 781system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 782system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked 783system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks 784system.cpu.dcache.writebacks::total 1542955 # number of writebacks 785system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits 786system.cpu.dcache.ReadReq_mshr_hits::total 1460236 # number of ReadReq MSHR hits 787system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911920 # number of WriteReq MSHR hits 788system.cpu.dcache.WriteReq_mshr_hits::total 911920 # number of WriteReq MSHR hits | 782system.cpu.dcache.avg_blocked_cycles::no_targets 7.973521 # average number of cycles each access was blocked 783system.cpu.dcache.writebacks::writebacks 1542807 # number of writebacks 784system.cpu.dcache.writebacks::total 1542807 # number of writebacks 785system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461430 # number of ReadReq MSHR hits 786system.cpu.dcache.ReadReq_mshr_hits::total 1461430 # number of ReadReq MSHR hits 787system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910604 # number of WriteReq MSHR hits 788system.cpu.dcache.WriteReq_mshr_hits::total 910604 # number of WriteReq MSHR hits |
| 789system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 790system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits | 789system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 790system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits |
| 791system.cpu.dcache.demand_mshr_hits::cpu.data 2372156 # number of demand (read+write) MSHR hits 792system.cpu.dcache.demand_mshr_hits::total 2372156 # number of demand (read+write) MSHR hits 793system.cpu.dcache.overall_mshr_hits::cpu.data 2372156 # number of overall MSHR hits 794system.cpu.dcache.overall_mshr_hits::total 2372156 # number of overall MSHR hits 795system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322721 # number of ReadReq MSHR misses 796system.cpu.dcache.ReadReq_mshr_misses::total 1322721 # number of ReadReq MSHR misses 797system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220749 # number of WriteReq MSHR misses 798system.cpu.dcache.WriteReq_mshr_misses::total 220749 # number of WriteReq MSHR misses | 791system.cpu.dcache.demand_mshr_hits::cpu.data 2372034 # number of demand (read+write) MSHR hits 792system.cpu.dcache.demand_mshr_hits::total 2372034 # number of demand (read+write) MSHR hits 793system.cpu.dcache.overall_mshr_hits::cpu.data 2372034 # number of overall MSHR hits 794system.cpu.dcache.overall_mshr_hits::total 2372034 # number of overall MSHR hits 795system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322581 # number of ReadReq MSHR misses 796system.cpu.dcache.ReadReq_mshr_misses::total 1322581 # number of ReadReq MSHR misses 797system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220744 # number of WriteReq MSHR misses 798system.cpu.dcache.WriteReq_mshr_misses::total 220744 # number of WriteReq MSHR misses |
| 799system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 800system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses | 799system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 800system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses |
| 801system.cpu.dcache.demand_mshr_misses::cpu.data 1543470 # number of demand (read+write) MSHR misses 802system.cpu.dcache.demand_mshr_misses::total 1543470 # number of demand (read+write) MSHR misses 803system.cpu.dcache.overall_mshr_misses::cpu.data 1543481 # number of overall MSHR misses 804system.cpu.dcache.overall_mshr_misses::total 1543481 # number of overall MSHR misses 805system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15298451500 # number of ReadReq MSHR miss cycles 806system.cpu.dcache.ReadReq_mshr_miss_latency::total 15298451500 # number of ReadReq MSHR miss cycles 807system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1831859691 # number of WriteReq MSHR miss cycles 808system.cpu.dcache.WriteReq_mshr_miss_latency::total 1831859691 # number of WriteReq MSHR miss cycles 809system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 695500 # number of SoftPFReq MSHR miss cycles 810system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 695500 # number of SoftPFReq MSHR miss cycles 811system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17130311191 # number of demand (read+write) MSHR miss cycles 812system.cpu.dcache.demand_mshr_miss_latency::total 17130311191 # number of demand (read+write) MSHR miss cycles 813system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17131006691 # number of overall MSHR miss cycles 814system.cpu.dcache.overall_mshr_miss_latency::total 17131006691 # number of overall MSHR miss cycles 815system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015775 # mshr miss rate for ReadReq accesses 816system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015775 # mshr miss rate for ReadReq accesses | 801system.cpu.dcache.demand_mshr_misses::cpu.data 1543325 # number of demand (read+write) MSHR misses 802system.cpu.dcache.demand_mshr_misses::total 1543325 # number of demand (read+write) MSHR misses 803system.cpu.dcache.overall_mshr_misses::cpu.data 1543336 # number of overall MSHR misses 804system.cpu.dcache.overall_mshr_misses::total 1543336 # number of overall MSHR misses 805system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25407816000 # number of ReadReq MSHR miss cycles 806system.cpu.dcache.ReadReq_mshr_miss_latency::total 25407816000 # number of ReadReq MSHR miss cycles 807system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1834277181 # number of WriteReq MSHR miss cycles 808system.cpu.dcache.WriteReq_mshr_miss_latency::total 1834277181 # number of WriteReq MSHR miss cycles 809system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 705000 # number of SoftPFReq MSHR miss cycles 810system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 705000 # number of SoftPFReq MSHR miss cycles 811system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27242093181 # number of demand (read+write) MSHR miss cycles 812system.cpu.dcache.demand_mshr_miss_latency::total 27242093181 # number of demand (read+write) MSHR miss cycles 813system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27242798181 # number of overall MSHR miss cycles 814system.cpu.dcache.overall_mshr_miss_latency::total 27242798181 # number of overall MSHR miss cycles 815system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015778 # mshr miss rate for ReadReq accesses 816system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015778 # mshr miss rate for ReadReq accesses |
| 817system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses 818system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses 819system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses 820system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses 821system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 # mshr miss rate for demand accesses 822system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses 823system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses 824system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses | 817system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses 818system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses 819system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses 820system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses 821system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 # mshr miss rate for demand accesses 822system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses 823system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses 824system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses |
| 825system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11565.894471 # average ReadReq mshr miss latency 826system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11565.894471 # average ReadReq mshr miss latency 827system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency 828system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency 829system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency 830system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency 831system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency 832system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency 833system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency 834system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency 835system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states 836system.cpu.icache.tags.replacements 726201 # number of replacements 837system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use 838system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. 839system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks. 840system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks. 841system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit. 842system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor 843system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy 844system.cpu.icache.tags.occ_percent::total 0.999616 # Average percentage of cache occupancy | 825system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19210.782553 # average ReadReq mshr miss latency 826system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19210.782553 # average ReadReq mshr miss latency 827system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8309.522257 # average WriteReq mshr miss latency 828system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8309.522257 # average WriteReq mshr miss latency 829system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64090.909091 # average SoftPFReq mshr miss latency 830system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64090.909091 # average SoftPFReq mshr miss latency 831system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17651.559575 # average overall mshr miss latency 832system.cpu.dcache.demand_avg_mshr_miss_latency::total 17651.559575 # average overall mshr miss latency 833system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17651.890568 # average overall mshr miss latency 834system.cpu.dcache.overall_avg_mshr_miss_latency::total 17651.890568 # average overall mshr miss latency 835system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states 836system.cpu.icache.tags.replacements 725593 # number of replacements 837system.cpu.icache.tags.tagsinuse 511.815316 # Cycle average of tags in use 838system.cpu.icache.tags.total_refs 81471161 # Total number of references to valid blocks. 839system.cpu.icache.tags.sampled_refs 726105 # Sample count of references to valid blocks. 840system.cpu.icache.tags.avg_refs 112.203002 # Average number of references to valid blocks. 841system.cpu.icache.tags.warmup_cycle 334835500 # Cycle when the warmup percentage was hit. 842system.cpu.icache.tags.occ_blocks::cpu.inst 511.815316 # Average occupied blocks per requestor 843system.cpu.icache.tags.occ_percent::cpu.inst 0.999639 # Average percentage of cache occupancy 844system.cpu.icache.tags.occ_percent::total 0.999639 # Average percentage of cache occupancy |
| 845system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 845system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 846system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id | 846system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id |
| 847system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id | 847system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id |
| 848system.cpu.icache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id | 848system.cpu.icache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id |
| 849system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id | 849system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id |
| 850system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id | 850system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id |
| 851system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 851system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 852system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses 853system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses 854system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states 855system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits 856system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits 857system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits 858system.cpu.icache.demand_hits::total 81470529 # number of demand (read+write) hits 859system.cpu.icache.overall_hits::cpu.inst 81470529 # number of overall hits 860system.cpu.icache.overall_hits::total 81470529 # number of overall hits 861system.cpu.icache.ReadReq_misses::cpu.inst 732796 # number of ReadReq misses 862system.cpu.icache.ReadReq_misses::total 732796 # number of ReadReq misses 863system.cpu.icache.demand_misses::cpu.inst 732796 # number of demand (read+write) misses 864system.cpu.icache.demand_misses::total 732796 # number of demand (read+write) misses 865system.cpu.icache.overall_misses::cpu.inst 732796 # number of overall misses 866system.cpu.icache.overall_misses::total 732796 # number of overall misses 867system.cpu.icache.ReadReq_miss_latency::cpu.inst 6565806949 # number of ReadReq miss cycles 868system.cpu.icache.ReadReq_miss_latency::total 6565806949 # number of ReadReq miss cycles 869system.cpu.icache.demand_miss_latency::cpu.inst 6565806949 # number of demand (read+write) miss cycles 870system.cpu.icache.demand_miss_latency::total 6565806949 # number of demand (read+write) miss cycles 871system.cpu.icache.overall_miss_latency::cpu.inst 6565806949 # number of overall miss cycles 872system.cpu.icache.overall_miss_latency::total 6565806949 # number of overall miss cycles 873system.cpu.icache.ReadReq_accesses::cpu.inst 82203325 # number of ReadReq accesses(hits+misses) 874system.cpu.icache.ReadReq_accesses::total 82203325 # number of ReadReq accesses(hits+misses) 875system.cpu.icache.demand_accesses::cpu.inst 82203325 # number of demand (read+write) accesses 876system.cpu.icache.demand_accesses::total 82203325 # number of demand (read+write) accesses 877system.cpu.icache.overall_accesses::cpu.inst 82203325 # number of overall (read+write) accesses 878system.cpu.icache.overall_accesses::total 82203325 # number of overall (read+write) accesses 879system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008914 # miss rate for ReadReq accesses 880system.cpu.icache.ReadReq_miss_rate::total 0.008914 # miss rate for ReadReq accesses 881system.cpu.icache.demand_miss_rate::cpu.inst 0.008914 # miss rate for demand accesses 882system.cpu.icache.demand_miss_rate::total 0.008914 # miss rate for demand accesses 883system.cpu.icache.overall_miss_rate::cpu.inst 0.008914 # miss rate for overall accesses 884system.cpu.icache.overall_miss_rate::total 0.008914 # miss rate for overall accesses 885system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8959.938303 # average ReadReq miss latency 886system.cpu.icache.ReadReq_avg_miss_latency::total 8959.938303 # average ReadReq miss latency 887system.cpu.icache.demand_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency 888system.cpu.icache.demand_avg_miss_latency::total 8959.938303 # average overall miss latency 889system.cpu.icache.overall_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency 890system.cpu.icache.overall_avg_miss_latency::total 8959.938303 # average overall miss latency 891system.cpu.icache.blocked_cycles::no_mshrs 64284 # number of cycles access was blocked 892system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked 893system.cpu.icache.blocked::no_mshrs 3051 # number of cycles access was blocked | 852system.cpu.icache.tags.tag_accesses 165134244 # Number of tag accesses 853system.cpu.icache.tags.data_accesses 165134244 # Number of data accesses 854system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states 855system.cpu.icache.ReadReq_hits::cpu.inst 81471161 # number of ReadReq hits 856system.cpu.icache.ReadReq_hits::total 81471161 # number of ReadReq hits 857system.cpu.icache.demand_hits::cpu.inst 81471161 # number of demand (read+write) hits 858system.cpu.icache.demand_hits::total 81471161 # number of demand (read+write) hits 859system.cpu.icache.overall_hits::cpu.inst 81471161 # number of overall hits 860system.cpu.icache.overall_hits::total 81471161 # number of overall hits 861system.cpu.icache.ReadReq_misses::cpu.inst 732901 # number of ReadReq misses 862system.cpu.icache.ReadReq_misses::total 732901 # number of ReadReq misses 863system.cpu.icache.demand_misses::cpu.inst 732901 # number of demand (read+write) misses 864system.cpu.icache.demand_misses::total 732901 # number of demand (read+write) misses 865system.cpu.icache.overall_misses::cpu.inst 732901 # number of overall misses 866system.cpu.icache.overall_misses::total 732901 # number of overall misses 867system.cpu.icache.ReadReq_miss_latency::cpu.inst 8031652441 # number of ReadReq miss cycles 868system.cpu.icache.ReadReq_miss_latency::total 8031652441 # number of ReadReq miss cycles 869system.cpu.icache.demand_miss_latency::cpu.inst 8031652441 # number of demand (read+write) miss cycles 870system.cpu.icache.demand_miss_latency::total 8031652441 # number of demand (read+write) miss cycles 871system.cpu.icache.overall_miss_latency::cpu.inst 8031652441 # number of overall miss cycles 872system.cpu.icache.overall_miss_latency::total 8031652441 # number of overall miss cycles 873system.cpu.icache.ReadReq_accesses::cpu.inst 82204062 # number of ReadReq accesses(hits+misses) 874system.cpu.icache.ReadReq_accesses::total 82204062 # number of ReadReq accesses(hits+misses) 875system.cpu.icache.demand_accesses::cpu.inst 82204062 # number of demand (read+write) accesses 876system.cpu.icache.demand_accesses::total 82204062 # number of demand (read+write) accesses 877system.cpu.icache.overall_accesses::cpu.inst 82204062 # number of overall (read+write) accesses 878system.cpu.icache.overall_accesses::total 82204062 # number of overall (read+write) accesses 879system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008916 # miss rate for ReadReq accesses 880system.cpu.icache.ReadReq_miss_rate::total 0.008916 # miss rate for ReadReq accesses 881system.cpu.icache.demand_miss_rate::cpu.inst 0.008916 # miss rate for demand accesses 882system.cpu.icache.demand_miss_rate::total 0.008916 # miss rate for demand accesses 883system.cpu.icache.overall_miss_rate::cpu.inst 0.008916 # miss rate for overall accesses 884system.cpu.icache.overall_miss_rate::total 0.008916 # miss rate for overall accesses 885system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10958.713989 # average ReadReq miss latency 886system.cpu.icache.ReadReq_avg_miss_latency::total 10958.713989 # average ReadReq miss latency 887system.cpu.icache.demand_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency 888system.cpu.icache.demand_avg_miss_latency::total 10958.713989 # average overall miss latency 889system.cpu.icache.overall_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency 890system.cpu.icache.overall_avg_miss_latency::total 10958.713989 # average overall miss latency 891system.cpu.icache.blocked_cycles::no_mshrs 128534 # number of cycles access was blocked 892system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked 893system.cpu.icache.blocked::no_mshrs 4274 # number of cycles access was blocked |
| 894system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked | 894system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked |
| 895system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked 896system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked 897system.cpu.icache.writebacks::writebacks 726201 # number of writebacks 898system.cpu.icache.writebacks::total 726201 # number of writebacks 899system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits 900system.cpu.icache.ReadReq_mshr_hits::total 6071 # number of ReadReq MSHR hits 901system.cpu.icache.demand_mshr_hits::cpu.inst 6071 # number of demand (read+write) MSHR hits 902system.cpu.icache.demand_mshr_hits::total 6071 # number of demand (read+write) MSHR hits 903system.cpu.icache.overall_mshr_hits::cpu.inst 6071 # number of overall MSHR hits 904system.cpu.icache.overall_mshr_hits::total 6071 # number of overall MSHR hits 905system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726725 # number of ReadReq MSHR misses 906system.cpu.icache.ReadReq_mshr_misses::total 726725 # number of ReadReq MSHR misses 907system.cpu.icache.demand_mshr_misses::cpu.inst 726725 # number of demand (read+write) MSHR misses 908system.cpu.icache.demand_mshr_misses::total 726725 # number of demand (read+write) MSHR misses 909system.cpu.icache.overall_mshr_misses::cpu.inst 726725 # number of overall MSHR misses 910system.cpu.icache.overall_mshr_misses::total 726725 # number of overall MSHR misses 911system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6109081458 # number of ReadReq MSHR miss cycles 912system.cpu.icache.ReadReq_mshr_miss_latency::total 6109081458 # number of ReadReq MSHR miss cycles 913system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6109081458 # number of demand (read+write) MSHR miss cycles 914system.cpu.icache.demand_mshr_miss_latency::total 6109081458 # number of demand (read+write) MSHR miss cycles 915system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6109081458 # number of overall MSHR miss cycles 916system.cpu.icache.overall_mshr_miss_latency::total 6109081458 # number of overall MSHR miss cycles 917system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for ReadReq accesses 918system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008841 # mshr miss rate for ReadReq accesses 919system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for demand accesses 920system.cpu.icache.demand_mshr_miss_rate::total 0.008841 # mshr miss rate for demand accesses 921system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses 922system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses 923system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency 924system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency 925system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency 926system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency 927system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency 928system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency 929system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states 930system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued 931system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified 932system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue | 895system.cpu.icache.avg_blocked_cycles::no_mshrs 30.073467 # average number of cycles each access was blocked 896system.cpu.icache.avg_blocked_cycles::no_targets 33.333333 # average number of cycles each access was blocked 897system.cpu.icache.writebacks::writebacks 725593 # number of writebacks 898system.cpu.icache.writebacks::total 725593 # number of writebacks 899system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6780 # number of ReadReq MSHR hits 900system.cpu.icache.ReadReq_mshr_hits::total 6780 # number of ReadReq MSHR hits 901system.cpu.icache.demand_mshr_hits::cpu.inst 6780 # number of demand (read+write) MSHR hits 902system.cpu.icache.demand_mshr_hits::total 6780 # number of demand (read+write) MSHR hits 903system.cpu.icache.overall_mshr_hits::cpu.inst 6780 # number of overall MSHR hits 904system.cpu.icache.overall_mshr_hits::total 6780 # number of overall MSHR hits 905system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726121 # number of ReadReq MSHR misses 906system.cpu.icache.ReadReq_mshr_misses::total 726121 # number of ReadReq MSHR misses 907system.cpu.icache.demand_mshr_misses::cpu.inst 726121 # number of demand (read+write) MSHR misses 908system.cpu.icache.demand_mshr_misses::total 726121 # number of demand (read+write) MSHR misses 909system.cpu.icache.overall_mshr_misses::cpu.inst 726121 # number of overall MSHR misses 910system.cpu.icache.overall_mshr_misses::total 726121 # number of overall MSHR misses 911system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7527879949 # number of ReadReq MSHR miss cycles 912system.cpu.icache.ReadReq_mshr_miss_latency::total 7527879949 # number of ReadReq MSHR miss cycles 913system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7527879949 # number of demand (read+write) MSHR miss cycles 914system.cpu.icache.demand_mshr_miss_latency::total 7527879949 # number of demand (read+write) MSHR miss cycles 915system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7527879949 # number of overall MSHR miss cycles 916system.cpu.icache.overall_mshr_miss_latency::total 7527879949 # number of overall MSHR miss cycles 917system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for ReadReq accesses 918system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008833 # mshr miss rate for ReadReq accesses 919system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for demand accesses 920system.cpu.icache.demand_mshr_miss_rate::total 0.008833 # mshr miss rate for demand accesses 921system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for overall accesses 922system.cpu.icache.overall_mshr_miss_rate::total 0.008833 # mshr miss rate for overall accesses 923system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10367.252771 # average ReadReq mshr miss latency 924system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10367.252771 # average ReadReq mshr miss latency 925system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency 926system.cpu.icache.demand_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency 927system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency 928system.cpu.icache.overall_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency 929system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states 930system.cpu.l2cache.prefetcher.num_hwpf_issued 402848 # number of hwpf issued 931system.cpu.l2cache.prefetcher.pfIdentified 402975 # number of prefetch candidates identified 932system.cpu.l2cache.prefetcher.pfBufferHit 113 # number of redundant prefetches already in prefetch queue |
| 933system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 934system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 933system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 934system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 935system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing 936system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states | 935system.cpu.l2cache.prefetcher.pfSpanPage 27937 # number of prefetches not generated due to page crossing 936system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states |
| 937system.cpu.l2cache.tags.replacements 0 # number of replacements | 937system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 938system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use 939system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks. 940system.cpu.l2cache.tags.sampled_refs 6750 # Sample count of references to valid blocks. 941system.cpu.l2cache.tags.avg_refs 450.538222 # Average number of references to valid blocks. | 938system.cpu.l2cache.tags.tagsinuse 5253.562311 # Cycle average of tags in use 939system.cpu.l2cache.tags.total_refs 1811987 # Total number of references to valid blocks. 940system.cpu.l2cache.tags.sampled_refs 6314 # Sample count of references to valid blocks. 941system.cpu.l2cache.tags.avg_refs 286.979252 # Average number of references to valid blocks. |
| 942system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 942system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 943system.cpu.l2cache.tags.occ_blocks::writebacks 5495.535708 # Average occupied blocks per requestor 944system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.642255 # Average occupied blocks per requestor 945system.cpu.l2cache.tags.occ_percent::writebacks 0.335421 # Average percentage of cache occupancy 946system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006570 # Average percentage of cache occupancy 947system.cpu.l2cache.tags.occ_percent::total 0.341991 # Average percentage of cache occupancy 948system.cpu.l2cache.tags.occ_task_id_blocks::1022 497 # Occupied blocks per task id 949system.cpu.l2cache.tags.occ_task_id_blocks::1024 6253 # Occupied blocks per task id 950system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id | 943system.cpu.l2cache.tags.occ_blocks::writebacks 5154.206528 # Average occupied blocks per requestor 944system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 99.355783 # Average occupied blocks per requestor 945system.cpu.l2cache.tags.occ_percent::writebacks 0.314588 # Average percentage of cache occupancy 946system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006064 # Average percentage of cache occupancy 947system.cpu.l2cache.tags.occ_percent::total 0.320652 # Average percentage of cache occupancy 948system.cpu.l2cache.tags.occ_task_id_blocks::1022 192 # Occupied blocks per task id 949system.cpu.l2cache.tags.occ_task_id_blocks::1024 6122 # Occupied blocks per task id 950system.cpu.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id |
| 951system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id | 951system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id |
| 952system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id 953system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id 954system.cpu.l2cache.tags.age_task_id_blocks_1022::4 113 # Occupied blocks per task id 955system.cpu.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 956system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id 957system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id 958system.cpu.l2cache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id 959system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5048 # Occupied blocks per task id 960system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 # Percentage of cache occupancy per task id 961system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381653 # Percentage of cache occupancy per task id 962system.cpu.l2cache.tags.tag_accesses 69530063 # Number of tag accesses 963system.cpu.l2cache.tags.data_accesses 69530063 # Number of data accesses 964system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states 965system.cpu.l2cache.WritebackDirty_hits::writebacks 968360 # number of WritebackDirty hits 966system.cpu.l2cache.WritebackDirty_hits::total 968360 # number of WritebackDirty hits 967system.cpu.l2cache.WritebackClean_hits::writebacks 1046226 # number of WritebackClean hits 968system.cpu.l2cache.WritebackClean_hits::total 1046226 # number of WritebackClean hits | 952system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id 953system.cpu.l2cache.tags.age_task_id_blocks_1022::4 110 # Occupied blocks per task id 954system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id 955system.cpu.l2cache.tags.age_task_id_blocks_1024::1 555 # Occupied blocks per task id 956system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1137 # Occupied blocks per task id 957system.cpu.l2cache.tags.age_task_id_blocks_1024::3 139 # Occupied blocks per task id 958system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4125 # Occupied blocks per task id 959system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011719 # Percentage of cache occupancy per task id 960system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373657 # Percentage of cache occupancy per task id 961system.cpu.l2cache.tags.tag_accesses 70548606 # Number of tag accesses 962system.cpu.l2cache.tags.data_accesses 70548606 # Number of data accesses 963system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states 964system.cpu.l2cache.WritebackDirty_hits::writebacks 968253 # number of WritebackDirty hits 965system.cpu.l2cache.WritebackDirty_hits::total 968253 # number of WritebackDirty hits 966system.cpu.l2cache.WritebackClean_hits::writebacks 1045699 # number of WritebackClean hits 967system.cpu.l2cache.WritebackClean_hits::total 1045699 # number of WritebackClean hits |
| 969system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 970system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits | 968system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 969system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits |
| 971system.cpu.l2cache.ReadExReq_hits::cpu.data 219964 # number of ReadExReq hits 972system.cpu.l2cache.ReadExReq_hits::total 219964 # number of ReadExReq hits 973system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 716938 # number of ReadCleanReq hits 974system.cpu.l2cache.ReadCleanReq_hits::total 716938 # number of ReadCleanReq hits 975system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1251135 # number of ReadSharedReq hits 976system.cpu.l2cache.ReadSharedReq_hits::total 1251135 # number of ReadSharedReq hits 977system.cpu.l2cache.demand_hits::cpu.inst 716938 # number of demand (read+write) hits 978system.cpu.l2cache.demand_hits::cpu.data 1471099 # number of demand (read+write) hits 979system.cpu.l2cache.demand_hits::total 2188037 # number of demand (read+write) hits 980system.cpu.l2cache.overall_hits::cpu.inst 716938 # number of overall hits 981system.cpu.l2cache.overall_hits::cpu.data 1471099 # number of overall hits 982system.cpu.l2cache.overall_hits::total 2188037 # number of overall hits 983system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 984system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 985system.cpu.l2cache.ReadExReq_misses::cpu.data 781 # number of ReadExReq misses 986system.cpu.l2cache.ReadExReq_misses::total 781 # number of ReadExReq misses 987system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9708 # number of ReadCleanReq misses 988system.cpu.l2cache.ReadCleanReq_misses::total 9708 # number of ReadCleanReq misses 989system.cpu.l2cache.ReadSharedReq_misses::cpu.data 71587 # number of ReadSharedReq misses 990system.cpu.l2cache.ReadSharedReq_misses::total 71587 # number of ReadSharedReq misses 991system.cpu.l2cache.demand_misses::cpu.inst 9708 # number of demand (read+write) misses 992system.cpu.l2cache.demand_misses::cpu.data 72368 # number of demand (read+write) misses 993system.cpu.l2cache.demand_misses::total 82076 # number of demand (read+write) misses 994system.cpu.l2cache.overall_misses::cpu.inst 9708 # number of overall misses 995system.cpu.l2cache.overall_misses::cpu.data 72368 # number of overall misses 996system.cpu.l2cache.overall_misses::total 82076 # number of overall misses 997system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 40000 # number of UpgradeReq miss cycles 998system.cpu.l2cache.UpgradeReq_miss_latency::total 40000 # number of UpgradeReq miss cycles 999system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56104500 # number of ReadExReq miss cycles 1000system.cpu.l2cache.ReadExReq_miss_latency::total 56104500 # number of ReadExReq miss cycles 1001system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 688634000 # number of ReadCleanReq miss cycles 1002system.cpu.l2cache.ReadCleanReq_miss_latency::total 688634000 # number of ReadCleanReq miss cycles 1003system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5061315000 # number of ReadSharedReq miss cycles 1004system.cpu.l2cache.ReadSharedReq_miss_latency::total 5061315000 # number of ReadSharedReq miss cycles 1005system.cpu.l2cache.demand_miss_latency::cpu.inst 688634000 # number of demand (read+write) miss cycles 1006system.cpu.l2cache.demand_miss_latency::cpu.data 5117419500 # number of demand (read+write) miss cycles 1007system.cpu.l2cache.demand_miss_latency::total 5806053500 # number of demand (read+write) miss cycles 1008system.cpu.l2cache.overall_miss_latency::cpu.inst 688634000 # number of overall miss cycles 1009system.cpu.l2cache.overall_miss_latency::cpu.data 5117419500 # number of overall miss cycles 1010system.cpu.l2cache.overall_miss_latency::total 5806053500 # number of overall miss cycles 1011system.cpu.l2cache.WritebackDirty_accesses::writebacks 968360 # number of WritebackDirty accesses(hits+misses) 1012system.cpu.l2cache.WritebackDirty_accesses::total 968360 # number of WritebackDirty accesses(hits+misses) 1013system.cpu.l2cache.WritebackClean_accesses::writebacks 1046226 # number of WritebackClean accesses(hits+misses) 1014system.cpu.l2cache.WritebackClean_accesses::total 1046226 # number of WritebackClean accesses(hits+misses) 1015system.cpu.l2cache.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) 1016system.cpu.l2cache.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) 1017system.cpu.l2cache.ReadExReq_accesses::cpu.data 220745 # number of ReadExReq accesses(hits+misses) 1018system.cpu.l2cache.ReadExReq_accesses::total 220745 # number of ReadExReq accesses(hits+misses) 1019system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726646 # number of ReadCleanReq accesses(hits+misses) 1020system.cpu.l2cache.ReadCleanReq_accesses::total 726646 # number of ReadCleanReq accesses(hits+misses) 1021system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322722 # number of ReadSharedReq accesses(hits+misses) 1022system.cpu.l2cache.ReadSharedReq_accesses::total 1322722 # number of ReadSharedReq accesses(hits+misses) 1023system.cpu.l2cache.demand_accesses::cpu.inst 726646 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::cpu.data 1543467 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::total 2270113 # number of demand (read+write) accesses 1026system.cpu.l2cache.overall_accesses::cpu.inst 726646 # number of overall (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.data 1543467 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::total 2270113 # number of overall (read+write) accesses 1029system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.928571 # miss rate for UpgradeReq accesses 1030system.cpu.l2cache.UpgradeReq_miss_rate::total 0.928571 # miss rate for UpgradeReq accesses 1031system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003538 # miss rate for ReadExReq accesses 1032system.cpu.l2cache.ReadExReq_miss_rate::total 0.003538 # miss rate for ReadExReq accesses 1033system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013360 # miss rate for ReadCleanReq accesses 1034system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013360 # miss rate for ReadCleanReq accesses 1035system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.054121 # miss rate for ReadSharedReq accesses 1036system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.054121 # miss rate for ReadSharedReq accesses 1037system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013360 # miss rate for demand accesses 1038system.cpu.l2cache.demand_miss_rate::cpu.data 0.046887 # miss rate for demand accesses 1039system.cpu.l2cache.demand_miss_rate::total 0.036155 # miss rate for demand accesses 1040system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013360 # miss rate for overall accesses 1041system.cpu.l2cache.overall_miss_rate::cpu.data 0.046887 # miss rate for overall accesses 1042system.cpu.l2cache.overall_miss_rate::total 0.036155 # miss rate for overall accesses 1043system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3076.923077 # average UpgradeReq miss latency 1044system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3076.923077 # average UpgradeReq miss latency 1045system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71836.747759 # average ReadExReq miss latency 1046system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71836.747759 # average ReadExReq miss latency 1047system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70934.693037 # average ReadCleanReq miss latency 1048system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70934.693037 # average ReadCleanReq miss latency 1049system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70701.593865 # average ReadSharedReq miss latency 1050system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70701.593865 # average ReadSharedReq miss latency 1051system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70934.693037 # average overall miss latency 1052system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency 1053system.cpu.l2cache.demand_avg_miss_latency::total 70739.966616 # average overall miss latency 1054system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70934.693037 # average overall miss latency 1055system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency 1056system.cpu.l2cache.overall_avg_miss_latency::total 70739.966616 # average overall miss latency | 970system.cpu.l2cache.ReadExReq_hits::cpu.data 219932 # number of ReadExReq hits 971system.cpu.l2cache.ReadExReq_hits::total 219932 # number of ReadExReq hits 972system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696525 # number of ReadCleanReq hits 973system.cpu.l2cache.ReadCleanReq_hits::total 696525 # number of ReadCleanReq hits 974system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094373 # number of ReadSharedReq hits 975system.cpu.l2cache.ReadSharedReq_hits::total 1094373 # number of ReadSharedReq hits 976system.cpu.l2cache.demand_hits::cpu.inst 696525 # number of demand (read+write) hits 977system.cpu.l2cache.demand_hits::cpu.data 1314305 # number of demand (read+write) hits 978system.cpu.l2cache.demand_hits::total 2010830 # number of demand (read+write) hits 979system.cpu.l2cache.overall_hits::cpu.inst 696525 # number of overall hits 980system.cpu.l2cache.overall_hits::cpu.data 1314305 # number of overall hits 981system.cpu.l2cache.overall_hits::total 2010830 # number of overall hits 982system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses 983system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses 984system.cpu.l2cache.ReadExReq_misses::cpu.data 807 # number of ReadExReq misses 985system.cpu.l2cache.ReadExReq_misses::total 807 # number of ReadExReq misses 986system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29515 # number of ReadCleanReq misses 987system.cpu.l2cache.ReadCleanReq_misses::total 29515 # number of ReadCleanReq misses 988system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228207 # number of ReadSharedReq misses 989system.cpu.l2cache.ReadSharedReq_misses::total 228207 # number of ReadSharedReq misses 990system.cpu.l2cache.demand_misses::cpu.inst 29515 # number of demand (read+write) misses 991system.cpu.l2cache.demand_misses::cpu.data 229014 # number of demand (read+write) misses 992system.cpu.l2cache.demand_misses::total 258529 # number of demand (read+write) misses 993system.cpu.l2cache.overall_misses::cpu.inst 29515 # number of overall misses 994system.cpu.l2cache.overall_misses::cpu.data 229014 # number of overall misses 995system.cpu.l2cache.overall_misses::total 258529 # number of overall misses 996system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 43000 # number of UpgradeReq miss cycles 997system.cpu.l2cache.UpgradeReq_miss_latency::total 43000 # number of UpgradeReq miss cycles 998system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59970500 # number of ReadExReq miss cycles 999system.cpu.l2cache.ReadExReq_miss_latency::total 59970500 # number of ReadExReq miss cycles 1000system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2262045500 # number of ReadCleanReq miss cycles 1001system.cpu.l2cache.ReadCleanReq_miss_latency::total 2262045500 # number of ReadCleanReq miss cycles 1002system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16271473000 # number of ReadSharedReq miss cycles 1003system.cpu.l2cache.ReadSharedReq_miss_latency::total 16271473000 # number of ReadSharedReq miss cycles 1004system.cpu.l2cache.demand_miss_latency::cpu.inst 2262045500 # number of demand (read+write) miss cycles 1005system.cpu.l2cache.demand_miss_latency::cpu.data 16331443500 # number of demand (read+write) miss cycles 1006system.cpu.l2cache.demand_miss_latency::total 18593489000 # number of demand (read+write) miss cycles 1007system.cpu.l2cache.overall_miss_latency::cpu.inst 2262045500 # number of overall miss cycles 1008system.cpu.l2cache.overall_miss_latency::cpu.data 16331443500 # number of overall miss cycles 1009system.cpu.l2cache.overall_miss_latency::total 18593489000 # number of overall miss cycles 1010system.cpu.l2cache.WritebackDirty_accesses::writebacks 968253 # number of WritebackDirty accesses(hits+misses) 1011system.cpu.l2cache.WritebackDirty_accesses::total 968253 # number of WritebackDirty accesses(hits+misses) 1012system.cpu.l2cache.WritebackClean_accesses::writebacks 1045699 # number of WritebackClean accesses(hits+misses) 1013system.cpu.l2cache.WritebackClean_accesses::total 1045699 # number of WritebackClean accesses(hits+misses) 1014system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 1015system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 1016system.cpu.l2cache.ReadExReq_accesses::cpu.data 220739 # number of ReadExReq accesses(hits+misses) 1017system.cpu.l2cache.ReadExReq_accesses::total 220739 # number of ReadExReq accesses(hits+misses) 1018system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726040 # number of ReadCleanReq accesses(hits+misses) 1019system.cpu.l2cache.ReadCleanReq_accesses::total 726040 # number of ReadCleanReq accesses(hits+misses) 1020system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322580 # number of ReadSharedReq accesses(hits+misses) 1021system.cpu.l2cache.ReadSharedReq_accesses::total 1322580 # number of ReadSharedReq accesses(hits+misses) 1022system.cpu.l2cache.demand_accesses::cpu.inst 726040 # number of demand (read+write) accesses 1023system.cpu.l2cache.demand_accesses::cpu.data 1543319 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::total 2269359 # number of demand (read+write) accesses 1025system.cpu.l2cache.overall_accesses::cpu.inst 726040 # number of overall (read+write) accesses 1026system.cpu.l2cache.overall_accesses::cpu.data 1543319 # number of overall (read+write) accesses 1027system.cpu.l2cache.overall_accesses::total 2269359 # number of overall (read+write) accesses 1028system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.941176 # miss rate for UpgradeReq accesses 1029system.cpu.l2cache.UpgradeReq_miss_rate::total 0.941176 # miss rate for UpgradeReq accesses 1030system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003656 # miss rate for ReadExReq accesses 1031system.cpu.l2cache.ReadExReq_miss_rate::total 0.003656 # miss rate for ReadExReq accesses 1032system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040652 # miss rate for ReadCleanReq accesses 1033system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040652 # miss rate for ReadCleanReq accesses 1034system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172547 # miss rate for ReadSharedReq accesses 1035system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172547 # miss rate for ReadSharedReq accesses 1036system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040652 # miss rate for demand accesses 1037system.cpu.l2cache.demand_miss_rate::cpu.data 0.148391 # miss rate for demand accesses 1038system.cpu.l2cache.demand_miss_rate::total 0.113922 # miss rate for demand accesses 1039system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040652 # miss rate for overall accesses 1040system.cpu.l2cache.overall_miss_rate::cpu.data 0.148391 # miss rate for overall accesses 1041system.cpu.l2cache.overall_miss_rate::total 0.113922 # miss rate for overall accesses 1042system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2687.500000 # average UpgradeReq miss latency 1043system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2687.500000 # average UpgradeReq miss latency 1044system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74312.887237 # average ReadExReq miss latency 1045system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74312.887237 # average ReadExReq miss latency 1046system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76640.538709 # average ReadCleanReq miss latency 1047system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76640.538709 # average ReadCleanReq miss latency 1048system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 71301.375506 # average ReadSharedReq miss latency 1049system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 71301.375506 # average ReadSharedReq miss latency 1050system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76640.538709 # average overall miss latency 1051system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71311.987477 # average overall miss latency 1052system.cpu.l2cache.demand_avg_miss_latency::total 71920.322285 # average overall miss latency 1053system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76640.538709 # average overall miss latency 1054system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71311.987477 # average overall miss latency 1055system.cpu.l2cache.overall_avg_miss_latency::total 71920.322285 # average overall miss latency |
| 1057system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1058system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1059system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1060system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1061system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1062system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1056system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1057system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1058system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1059system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1060system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1061system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1063system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits 1064system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits 1065system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits 1066system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits 1067system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits 1068system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits 1069system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits 1070system.cpu.l2cache.demand_mshr_hits::cpu.data 85 # number of demand (read+write) MSHR hits 1071system.cpu.l2cache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits 1072system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits 1073system.cpu.l2cache.overall_mshr_hits::cpu.data 85 # number of overall MSHR hits 1074system.cpu.l2cache.overall_mshr_hits::total 97 # number of overall MSHR hits 1075system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51651 # number of HardPFReq MSHR misses 1076system.cpu.l2cache.HardPFReq_mshr_misses::total 51651 # number of HardPFReq MSHR misses 1077system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 1078system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 1079system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 730 # number of ReadExReq MSHR misses 1080system.cpu.l2cache.ReadExReq_mshr_misses::total 730 # number of ReadExReq MSHR misses 1081system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9696 # number of ReadCleanReq MSHR misses 1082system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9696 # number of ReadCleanReq MSHR misses 1083system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 71553 # number of ReadSharedReq MSHR misses 1084system.cpu.l2cache.ReadSharedReq_mshr_misses::total 71553 # number of ReadSharedReq MSHR misses 1085system.cpu.l2cache.demand_mshr_misses::cpu.inst 9696 # number of demand (read+write) MSHR misses 1086system.cpu.l2cache.demand_mshr_misses::cpu.data 72283 # number of demand (read+write) MSHR misses 1087system.cpu.l2cache.demand_mshr_misses::total 81979 # number of demand (read+write) MSHR misses 1088system.cpu.l2cache.overall_mshr_misses::cpu.inst 9696 # number of overall MSHR misses 1089system.cpu.l2cache.overall_mshr_misses::cpu.data 72283 # number of overall MSHR misses 1090system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51651 # number of overall MSHR misses 1091system.cpu.l2cache.overall_mshr_misses::total 133630 # number of overall MSHR misses 1092system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 178131300 # number of HardPFReq MSHR miss cycles 1093system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 178131300 # number of HardPFReq MSHR miss cycles 1094system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 187000 # number of UpgradeReq MSHR miss cycles 1095system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 187000 # number of UpgradeReq MSHR miss cycles 1096system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50303500 # number of ReadExReq MSHR miss cycles 1097system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50303500 # number of ReadExReq MSHR miss cycles 1098system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 629910500 # number of ReadCleanReq MSHR miss cycles 1099system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 629910500 # number of ReadCleanReq MSHR miss cycles 1100system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4630072500 # number of ReadSharedReq MSHR miss cycles 1101system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4630072500 # number of ReadSharedReq MSHR miss cycles 1102system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 629910500 # number of demand (read+write) MSHR miss cycles 1103system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4680376000 # number of demand (read+write) MSHR miss cycles 1104system.cpu.l2cache.demand_mshr_miss_latency::total 5310286500 # number of demand (read+write) MSHR miss cycles 1105system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 629910500 # number of overall MSHR miss cycles 1106system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4680376000 # number of overall MSHR miss cycles 1107system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 178131300 # number of overall MSHR miss cycles 1108system.cpu.l2cache.overall_mshr_miss_latency::total 5488417800 # number of overall MSHR miss cycles | 1062system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 50 # number of ReadExReq MSHR hits 1063system.cpu.l2cache.ReadExReq_mshr_hits::total 50 # number of ReadExReq MSHR hits 1064system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits 1065system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 1066system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 36 # number of ReadSharedReq MSHR hits 1067system.cpu.l2cache.ReadSharedReq_mshr_hits::total 36 # number of ReadSharedReq MSHR hits 1068system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits 1069system.cpu.l2cache.demand_mshr_hits::cpu.data 86 # number of demand (read+write) MSHR hits 1070system.cpu.l2cache.demand_mshr_hits::total 99 # number of demand (read+write) MSHR hits 1071system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits 1072system.cpu.l2cache.overall_mshr_hits::cpu.data 86 # number of overall MSHR hits 1073system.cpu.l2cache.overall_mshr_hits::total 99 # number of overall MSHR hits 1074system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54157 # number of HardPFReq MSHR misses 1075system.cpu.l2cache.HardPFReq_mshr_misses::total 54157 # number of HardPFReq MSHR misses 1076system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses 1077system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses 1078system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 757 # number of ReadExReq MSHR misses 1079system.cpu.l2cache.ReadExReq_mshr_misses::total 757 # number of ReadExReq MSHR misses 1080system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29502 # number of ReadCleanReq MSHR misses 1081system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29502 # number of ReadCleanReq MSHR misses 1082system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228171 # number of ReadSharedReq MSHR misses 1083system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228171 # number of ReadSharedReq MSHR misses 1084system.cpu.l2cache.demand_mshr_misses::cpu.inst 29502 # number of demand (read+write) MSHR misses 1085system.cpu.l2cache.demand_mshr_misses::cpu.data 228928 # number of demand (read+write) MSHR misses 1086system.cpu.l2cache.demand_mshr_misses::total 258430 # number of demand (read+write) MSHR misses 1087system.cpu.l2cache.overall_mshr_misses::cpu.inst 29502 # number of overall MSHR misses 1088system.cpu.l2cache.overall_mshr_misses::cpu.data 228928 # number of overall MSHR misses 1089system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54157 # number of overall MSHR misses 1090system.cpu.l2cache.overall_mshr_misses::total 312587 # number of overall MSHR misses 1091system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of HardPFReq MSHR miss cycles 1092system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 187753381 # number of HardPFReq MSHR miss cycles 1093system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 251000 # number of UpgradeReq MSHR miss cycles 1094system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 251000 # number of UpgradeReq MSHR miss cycles 1095system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53315000 # number of ReadExReq MSHR miss cycles 1096system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53315000 # number of ReadExReq MSHR miss cycles 1097system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2084473500 # number of ReadCleanReq MSHR miss cycles 1098system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2084473500 # number of ReadCleanReq MSHR miss cycles 1099system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14900259000 # number of ReadSharedReq MSHR miss cycles 1100system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14900259000 # number of ReadSharedReq MSHR miss cycles 1101system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2084473500 # number of demand (read+write) MSHR miss cycles 1102system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14953574000 # number of demand (read+write) MSHR miss cycles 1103system.cpu.l2cache.demand_mshr_miss_latency::total 17038047500 # number of demand (read+write) MSHR miss cycles 1104system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2084473500 # number of overall MSHR miss cycles 1105system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14953574000 # number of overall MSHR miss cycles 1106system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of overall MSHR miss cycles 1107system.cpu.l2cache.overall_mshr_miss_latency::total 17225800881 # number of overall MSHR miss cycles |
| 1109system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1110system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1108system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1109system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1111system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.928571 # mshr miss rate for UpgradeReq accesses 1112system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.928571 # mshr miss rate for UpgradeReq accesses 1113system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses 1114system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses 1115system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for ReadCleanReq accesses 1116system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013343 # mshr miss rate for ReadCleanReq accesses 1117system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.054095 # mshr miss rate for ReadSharedReq accesses 1118system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.054095 # mshr miss rate for ReadSharedReq accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for demand accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for demand accesses 1121system.cpu.l2cache.demand_mshr_miss_rate::total 0.036112 # mshr miss rate for demand accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for overall accesses 1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for overall accesses | 1110system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses 1111system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses 1112system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003429 # mshr miss rate for ReadExReq accesses 1113system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003429 # mshr miss rate for ReadExReq accesses 1114system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for ReadCleanReq accesses 1115system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040634 # mshr miss rate for ReadCleanReq accesses 1116system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172520 # mshr miss rate for ReadSharedReq accesses 1117system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172520 # mshr miss rate for ReadSharedReq accesses 1118system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for demand accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for demand accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::total 0.113878 # mshr miss rate for demand accesses 1121system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for overall accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for overall accesses |
| 1124system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1125system.cpu.l2cache.overall_mshr_miss_rate::total 0.058865 # mshr miss rate for overall accesses 1126system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average HardPFReq mshr miss latency 1127system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3448.748330 # average HardPFReq mshr miss latency 1128system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14384.615385 # average UpgradeReq mshr miss latency 1129system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14384.615385 # average UpgradeReq mshr miss latency 1130system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68908.904110 # average ReadExReq mshr miss latency 1131system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68908.904110 # average ReadExReq mshr miss latency 1132system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64966.016914 # average ReadCleanReq mshr miss latency 1133system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64966.016914 # average ReadCleanReq mshr miss latency 1134system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64708.293153 # average ReadSharedReq mshr miss latency 1135system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153 # average ReadSharedReq mshr miss latency 1136system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency 1137system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency 1138system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency 1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency 1143system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter. 1144system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1145system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1146system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. 1147system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1148system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1149system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states 1150system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::CleanEvict 81249 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::HardPFReq 53022 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::ReadExReq 220745 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::ReadExResp 220745 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::ReadCleanReq 726725 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322722 # Transaction distribution 1161system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179572 # Packet count per connected master and slave (bytes) 1162system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629917 # Packet count per connected master and slave (bytes) 1163system.cpu.toL2Bus.pkt_count::total 6809489 # Packet count per connected master and slave (bytes) 1164system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92982208 # Cumulative packet size per connected master and slave (bytes) 1165system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197531008 # Cumulative packet size per connected master and slave (bytes) 1166system.cpu.toL2Bus.pkt_size::total 290513216 # Cumulative packet size per connected master and slave (bytes) 1167system.cpu.toL2Bus.snoops 134350 # Total snoops (count) 1168system.cpu.toL2Bus.snoopTraffic 5056 # Total snoop traffic (bytes) 1169system.cpu.toL2Bus.snoop_fanout::samples 2404477 # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::mean 0.192237 # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::stdev 0.468638 # Request fanout histogram | 1124system.cpu.l2cache.overall_mshr_miss_rate::total 0.137742 # mshr miss rate for overall accesses 1125system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average HardPFReq mshr miss latency 1126system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3466.834961 # average HardPFReq mshr miss latency 1127system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency 1128system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency 1129system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70429.326288 # average ReadExReq mshr miss latency 1130system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70429.326288 # average ReadExReq mshr miss latency 1131system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70655.328452 # average ReadCleanReq mshr miss latency 1132system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70655.328452 # average ReadCleanReq mshr miss latency 1133system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65303.035881 # average ReadSharedReq mshr miss latency 1134system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65303.035881 # average ReadSharedReq mshr miss latency 1135system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency 1136system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency 1137system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65929.062028 # average overall mshr miss latency 1138system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average overall mshr miss latency 1141system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55107.220969 # average overall mshr miss latency 1142system.cpu.toL2Bus.snoop_filter.tot_requests 4537857 # Total number of requests made to the snoop filter. 1143system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268434 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1144system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254467 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1145system.cpu.toL2Bus.snoop_filter.tot_snoops 51535 # Total number of snoops made to the snoop filter. 1146system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51534 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1147system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1148system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states 1149system.cpu.toL2Bus.trans_dist::ReadResp 2048700 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::WritebackDirty 968253 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::WritebackClean 1300147 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::HardPFReq 55525 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::ReadCleanReq 726121 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution 1159system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177753 # Packet count per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629479 # Packet count per connected master and slave (bytes) 1161system.cpu.toL2Bus.pkt_count::total 6807232 # Packet count per connected master and slave (bytes) 1162system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92904448 # Cumulative packet size per connected master and slave (bytes) 1163system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197512064 # Cumulative packet size per connected master and slave (bytes) 1164system.cpu.toL2Bus.pkt_size::total 290416512 # Cumulative packet size per connected master and slave (bytes) 1165system.cpu.toL2Bus.snoops 55606 # Total snoops (count) 1166system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) 1167system.cpu.toL2Bus.snoop_fanout::samples 2324982 # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::mean 0.131629 # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::stdev 0.338088 # Request fanout histogram |
| 1172system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1170system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1173system.cpu.toL2Bus.snoop_fanout::0 2019600 83.99% 83.99% # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::1 307525 12.79% 96.78% # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::2 77352 3.22% 100.00% # Request fanout histogram | 1171system.cpu.toL2Bus.snoop_fanout::0 2018948 86.84% 86.84% # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::1 306033 13.16% 100.00% # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram |
| 1176system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1174system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1179system.cpu.toL2Bus.snoop_fanout::total 2404477 # Request fanout histogram 1180system.cpu.toL2Bus.reqLayer0.occupancy 4538837000 # Layer occupancy (ticks) 1181system.cpu.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%) 1182system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # Layer occupancy (ticks) 1183system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 1184system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks) 1185system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) 1186system.membus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states 1187system.membus.trans_dist::ReadResp 83887 # Transaction distribution 1188system.membus.trans_dist::UpgradeReq 13 # Transaction distribution 1189system.membus.trans_dist::ReadExReq 730 # Transaction distribution 1190system.membus.trans_dist::ReadExResp 730 # Transaction distribution 1191system.membus.trans_dist::ReadSharedReq 83887 # Transaction distribution 1192system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169247 # Packet count per connected master and slave (bytes) 1193system.membus.pkt_count::total 169247 # Packet count per connected master and slave (bytes) 1194system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes) 1195system.membus.pkt_size::total 5415488 # Cumulative packet size per connected master and slave (bytes) | 1177system.cpu.toL2Bus.snoop_fanout::total 2324982 # Request fanout histogram 1178system.cpu.toL2Bus.reqLayer0.occupancy 4537328500 # Layer occupancy (ticks) 1179system.cpu.toL2Bus.reqLayer0.utilization 3.8 # Layer utilization (%) 1180system.cpu.toL2Bus.respLayer0.occupancy 1089458442 # Layer occupancy (ticks) 1181system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) 1182system.cpu.toL2Bus.respLayer1.occupancy 2315007958 # Layer occupancy (ticks) 1183system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) 1184system.membus.snoop_filter.tot_requests 261068 # Total number of requests made to the snoop filter. 1185system.membus.snoop_filter.hit_single_requests 253748 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1186system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1187system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1188system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1189system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1190system.membus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states 1191system.membus.trans_dist::ReadResp 260294 # Transaction distribution 1192system.membus.trans_dist::UpgradeReq 16 # Transaction distribution 1193system.membus.trans_dist::ReadExReq 757 # Transaction distribution 1194system.membus.trans_dist::ReadExResp 757 # Transaction distribution 1195system.membus.trans_dist::ReadSharedReq 260295 # Transaction distribution 1196system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522119 # Packet count per connected master and slave (bytes) 1197system.membus.pkt_count::total 522119 # Packet count per connected master and slave (bytes) 1198system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707264 # Cumulative packet size per connected master and slave (bytes) 1199system.membus.pkt_size::total 16707264 # Cumulative packet size per connected master and slave (bytes) |
| 1196system.membus.snoops 0 # Total snoops (count) 1197system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1200system.membus.snoops 0 # Total snoops (count) 1201system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1198system.membus.snoop_fanout::samples 84630 # Request fanout histogram | 1202system.membus.snoop_fanout::samples 261068 # Request fanout histogram |
| 1199system.membus.snoop_fanout::mean 0 # Request fanout histogram 1200system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1201system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1203system.membus.snoop_fanout::mean 0 # Request fanout histogram 1204system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1205system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1202system.membus.snoop_fanout::0 84630 100.00% 100.00% # Request fanout histogram | 1206system.membus.snoop_fanout::0 261068 100.00% 100.00% # Request fanout histogram |
| 1203system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1204system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1205system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1206system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1207system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1208system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1209system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1210system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1207system.membus.snoop_fanout::total 84630 # Request fanout histogram 1208system.membus.reqLayer0.occupancy 108151910 # Layer occupancy (ticks) 1209system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 1210system.membus.respLayer1.occupancy 445724357 # Layer occupancy (ticks) 1211system.membus.respLayer1.utilization 0.4 # Layer utilization (%) | 1211system.membus.snoop_fanout::total 261068 # Request fanout histogram 1212system.membus.reqLayer0.occupancy 329929457 # Layer occupancy (ticks) 1213system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 1214system.membus.respLayer1.occupancy 1377865586 # Layer occupancy (ticks) 1215system.membus.respLayer1.utilization 1.1 # Layer utilization (%) |
| 1212 1213---------- End Simulation Statistics ---------- | 1216 1217---------- End Simulation Statistics ---------- |