| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.111754 # Number of seconds simulated 4sim_ticks 111753553500 # Number of ticks simulated 5final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.111754 # Number of seconds simulated 4sim_ticks 111753553500 # Number of ticks simulated 5final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 152363 # Simulator instruction rate (inst/s) 8host_op_rate 182928 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 62361670 # Simulator tick rate (ticks/s) 10host_mem_usage 292096 # Number of bytes of host memory used 11host_seconds 1792.02 # Real time elapsed on the host | 7host_inst_rate 153930 # Simulator instruction rate (inst/s) 8host_op_rate 184810 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 63003104 # Simulator tick rate (ticks/s) 10host_mem_usage 292088 # Number of bytes of host memory used 11host_seconds 1773.78 # Real time elapsed on the host |
| 12sim_insts 273037220 # Number of instructions simulated 13sim_ops 327811602 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory 19system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory --- 746 unchanged lines hidden (view full) --- 766system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990 # average overall miss latency 767system.cpu.dcache.overall_avg_miss_latency::total 10271.640990 # average overall miss latency 768system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 769system.cpu.dcache.blocked_cycles::no_targets 1079488 # number of cycles access was blocked 770system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 771system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked 772system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 773system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked | 12sim_insts 273037220 # Number of instructions simulated 13sim_ops 327811602 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory 19system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory --- 746 unchanged lines hidden (view full) --- 766system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990 # average overall miss latency 767system.cpu.dcache.overall_avg_miss_latency::total 10271.640990 # average overall miss latency 768system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 769system.cpu.dcache.blocked_cycles::no_targets 1079488 # number of cycles access was blocked 770system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 771system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked 772system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 773system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked |
| 774system.cpu.dcache.fast_writes 0 # number of fast writes performed 775system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 776system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks 777system.cpu.dcache.writebacks::total 1542955 # number of writebacks 778system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits 779system.cpu.dcache.ReadReq_mshr_hits::total 1460236 # number of ReadReq MSHR hits 780system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911920 # number of WriteReq MSHR hits 781system.cpu.dcache.WriteReq_mshr_hits::total 911920 # number of WriteReq MSHR hits 782system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 783system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 820system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency 821system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency 822system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency 823system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency 824system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency 825system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency 826system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency 827system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency | 774system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks 775system.cpu.dcache.writebacks::total 1542955 # number of writebacks 776system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits 777system.cpu.dcache.ReadReq_mshr_hits::total 1460236 # number of ReadReq MSHR hits 778system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911920 # number of WriteReq MSHR hits 779system.cpu.dcache.WriteReq_mshr_hits::total 911920 # number of WriteReq MSHR hits 780system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 781system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency 819system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency 820system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency 821system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency 822system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency 823system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency 824system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency 825system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency |
| 828system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 829system.cpu.icache.tags.replacements 726201 # number of replacements 830system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use 831system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. 832system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks. 833system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks. 834system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit. 835system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor 836system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 881system.cpu.icache.overall_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency 882system.cpu.icache.overall_avg_miss_latency::total 8959.938303 # average overall miss latency 883system.cpu.icache.blocked_cycles::no_mshrs 64284 # number of cycles access was blocked 884system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked 885system.cpu.icache.blocked::no_mshrs 3051 # number of cycles access was blocked 886system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 887system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked 888system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked | 826system.cpu.icache.tags.replacements 726201 # number of replacements 827system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use 828system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. 829system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks. 830system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks. 831system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit. 832system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor 833system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 878system.cpu.icache.overall_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency 879system.cpu.icache.overall_avg_miss_latency::total 8959.938303 # average overall miss latency 880system.cpu.icache.blocked_cycles::no_mshrs 64284 # number of cycles access was blocked 881system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked 882system.cpu.icache.blocked::no_mshrs 3051 # number of cycles access was blocked 883system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 884system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked 885system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked |
| 889system.cpu.icache.fast_writes 0 # number of fast writes performed 890system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 891system.cpu.icache.writebacks::writebacks 726201 # number of writebacks 892system.cpu.icache.writebacks::total 726201 # number of writebacks 893system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits 894system.cpu.icache.ReadReq_mshr_hits::total 6071 # number of ReadReq MSHR hits 895system.cpu.icache.demand_mshr_hits::cpu.inst 6071 # number of demand (read+write) MSHR hits 896system.cpu.icache.demand_mshr_hits::total 6071 # number of demand (read+write) MSHR hits 897system.cpu.icache.overall_mshr_hits::cpu.inst 6071 # number of overall MSHR hits 898system.cpu.icache.overall_mshr_hits::total 6071 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 915system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses 916system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses 917system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency 918system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency 919system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency 920system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency 921system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency 922system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency | 886system.cpu.icache.writebacks::writebacks 726201 # number of writebacks 887system.cpu.icache.writebacks::total 726201 # number of writebacks 888system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits 889system.cpu.icache.ReadReq_mshr_hits::total 6071 # number of ReadReq MSHR hits 890system.cpu.icache.demand_mshr_hits::cpu.inst 6071 # number of demand (read+write) MSHR hits 891system.cpu.icache.demand_mshr_hits::total 6071 # number of demand (read+write) MSHR hits 892system.cpu.icache.overall_mshr_hits::cpu.inst 6071 # number of overall MSHR hits 893system.cpu.icache.overall_mshr_hits::total 6071 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses 911system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses 912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency 914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency 916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency |
| 923system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 924system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued 925system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified 926system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue 927system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 928system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 929system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing 930system.cpu.l2cache.tags.replacements 0 # number of replacements 931system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use --- 115 unchanged lines hidden (view full) --- 1047system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency 1048system.cpu.l2cache.overall_avg_miss_latency::total 70739.966616 # average overall miss latency 1049system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1050system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1051system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1052system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1053system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1054system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 918system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued 919system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified 920system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue 921system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 922system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 923system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing 924system.cpu.l2cache.tags.replacements 0 # number of replacements 925system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use --- 115 unchanged lines hidden (view full) --- 1041system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency 1042system.cpu.l2cache.overall_avg_miss_latency::total 70739.966616 # average overall miss latency 1043system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1044system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1045system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1046system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1047system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1048system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1055system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1056system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1057system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits 1058system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits 1059system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits 1060system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits 1061system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits 1062system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits 1063system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits 1064system.cpu.l2cache.demand_mshr_hits::cpu.data 85 # number of demand (read+write) MSHR hits --- 64 unchanged lines hidden (view full) --- 1129system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153 # average ReadSharedReq mshr miss latency 1130system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency 1131system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency 1132system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485 # average overall mshr miss latency 1133system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency 1134system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency 1135system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency 1136system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency | 1049system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits 1050system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits 1051system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits 1052system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits 1053system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits 1054system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits 1055system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits 1056system.cpu.l2cache.demand_mshr_hits::cpu.data 85 # number of demand (read+write) MSHR hits --- 64 unchanged lines hidden (view full) --- 1121system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153 # average ReadSharedReq mshr miss latency 1122system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency 1123system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency 1124system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485 # average overall mshr miss latency 1125system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency 1126system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency 1127system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency 1128system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency |
| 1137system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1138system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter. 1139system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1140system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1141system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. 1142system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1143system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1144system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution --- 59 unchanged lines hidden --- | 1129system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter. 1130system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1131system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1132system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. 1133system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1134system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1135system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution 1136system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution --- 59 unchanged lines hidden --- |