| stats.txt (10892:bd37e25fb3b7) | stats.txt (10944:412eb87b1cfc) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.112686 # Number of seconds simulated 4sim_ticks 112686104500 # Number of ticks simulated 5final_tick 112686104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.112687 # Number of seconds simulated 4sim_ticks 112687034500 # Number of ticks simulated 5final_tick 112687034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 125538 # Simulator instruction rate (inst/s) 8host_op_rate 150722 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 51811162 # Simulator tick rate (ticks/s) 10host_mem_usage 327864 # Number of bytes of host memory used 11host_seconds 2174.94 # Real time elapsed on the host | 7host_inst_rate 126437 # Simulator instruction rate (inst/s) 8host_op_rate 151802 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52182660 # Simulator tick rate (ticks/s) 10host_mem_usage 327844 # Number of bytes of host memory used 11host_seconds 2159.47 # Real time elapsed on the host |
| 12sim_insts 273037220 # Number of instructions simulated 13sim_ops 327811602 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory | 12sim_insts 273037220 # Number of instructions simulated 13sim_ops 327811602 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 112896 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 167936 # Number of bytes read from this memory 19system.physmem.bytes_read::total 467904 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 112448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 169152 # Number of bytes read from this memory 19system.physmem.bytes_read::total 468672 # Number of bytes read from this memory |
| 20system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory | 20system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::cpu.data 1764 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 2624 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 7311 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1660116 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 1001863 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 1490299 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 4152278 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 1660116 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 1660116 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 1660116 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 1001863 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 1490299 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 4152278 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 7311 # Number of read requests accepted | 23system.physmem.num_reads::cpu.data 1757 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 2643 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 7323 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1660102 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 997879 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 1501078 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 4159059 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 1660102 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 1660102 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 1660102 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 997879 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 1501078 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 4159059 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 7323 # Number of read requests accepted |
| 37system.physmem.writeReqs 0 # Number of write requests accepted | 37system.physmem.writeReqs 0 # Number of write requests accepted |
| 38system.physmem.readBursts 7311 # Number of DRAM read bursts, including those serviced by the write queue | 38system.physmem.readBursts 7323 # Number of DRAM read bursts, including those serviced by the write queue |
| 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 40system.physmem.bytesReadDRAM 467904 # Total number of bytes read from DRAM | 40system.physmem.bytesReadDRAM 468672 # Total number of bytes read from DRAM |
| 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 43system.physmem.bytesReadSys 467904 # Total read bytes from the system interface side | 43system.physmem.bytesReadSys 468672 # Total read bytes from the system interface side |
| 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 589 # Per bank write bursts 49system.physmem.perBankRdBursts::1 789 # Per bank write bursts 50system.physmem.perBankRdBursts::2 601 # Per bank write bursts 51system.physmem.perBankRdBursts::3 520 # Per bank write bursts 52system.physmem.perBankRdBursts::4 444 # Per bank write bursts 53system.physmem.perBankRdBursts::5 346 # Per bank write bursts 54system.physmem.perBankRdBursts::6 153 # Per bank write bursts | 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 589 # Per bank write bursts 49system.physmem.perBankRdBursts::1 789 # Per bank write bursts 50system.physmem.perBankRdBursts::2 601 # Per bank write bursts 51system.physmem.perBankRdBursts::3 520 # Per bank write bursts 52system.physmem.perBankRdBursts::4 444 # Per bank write bursts 53system.physmem.perBankRdBursts::5 346 # Per bank write bursts 54system.physmem.perBankRdBursts::6 153 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::7 252 # Per bank write bursts | 55system.physmem.perBankRdBursts::7 251 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::8 219 # Per bank write bursts 57system.physmem.perBankRdBursts::9 290 # Per bank write bursts 58system.physmem.perBankRdBursts::10 315 # Per bank write bursts 59system.physmem.perBankRdBursts::11 411 # Per bank write bursts 60system.physmem.perBankRdBursts::12 547 # Per bank write bursts 61system.physmem.perBankRdBursts::13 678 # Per bank write bursts 62system.physmem.perBankRdBursts::14 615 # Per bank write bursts | 56system.physmem.perBankRdBursts::8 219 # Per bank write bursts 57system.physmem.perBankRdBursts::9 290 # Per bank write bursts 58system.physmem.perBankRdBursts::10 315 # Per bank write bursts 59system.physmem.perBankRdBursts::11 411 # Per bank write bursts 60system.physmem.perBankRdBursts::12 547 # Per bank write bursts 61system.physmem.perBankRdBursts::13 678 # Per bank write bursts 62system.physmem.perBankRdBursts::14 615 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::15 542 # Per bank write bursts | 63system.physmem.perBankRdBursts::15 555 # Per bank write bursts |
| 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 82system.physmem.totGap 112685946000 # Total gap between requests | 82system.physmem.totGap 112686876000 # Total gap between requests |
| 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) | 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 89system.physmem.readPktSize::6 7311 # Read request sizes (log2) | 89system.physmem.readPktSize::6 7323 # Read request sizes (log2) |
| 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) | 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 97system.physmem.rdQLenPdf::0 3986 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see | 97system.physmem.rdQLenPdf::0 4012 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 1463 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 466 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 286 # What read queue length does an incoming req see |
| 101system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see |
| 102system.physmem.rdQLenPdf::5 200 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 175 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 198 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 151 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see | 102system.physmem.rdQLenPdf::5 210 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 170 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 170 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 174 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see |
| 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see --- 65 unchanged lines hidden (view full) --- 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see --- 65 unchanged lines hidden (view full) --- 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 193system.physmem.bytesPerActivate::samples 1367 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 340.646672 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 198.022122 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 348.529599 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 486 35.55% 35.55% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 298 21.80% 57.35% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 139 10.17% 67.52% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 76 5.56% 73.08% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 63 4.61% 77.69% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 51 3.73% 81.42% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 27 1.98% 83.39% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 26 1.90% 85.30% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 201 14.70% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 1367 # Bytes accessed per row activation 207system.physmem.totQLat 102208518 # Total ticks spent queuing 208system.physmem.totMemAccLat 239289768 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 36555000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 13980.10 # Average queueing delay per DRAM burst | 193system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 339.932896 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 197.349943 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 349.457617 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 486 35.45% 35.45% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 309 22.54% 57.99% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 132 9.63% 67.61% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 75 5.47% 73.09% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 64 4.67% 77.75% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 48 3.50% 81.25% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 26 1.90% 83.15% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 25 1.82% 84.97% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 206 15.03% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation 207system.physmem.totQLat 95174041 # Total ticks spent queuing 208system.physmem.totMemAccLat 232480291 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 36615000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 12996.59 # Average queueing delay per DRAM burst |
| 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 212system.physmem.avgMemAccLat 32730.10 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 4.15 # Average DRAM read bandwidth in MiByte/s | 212system.physmem.avgMemAccLat 31746.59 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 4.16 # Average DRAM read bandwidth in MiByte/s |
| 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 215system.physmem.avgRdBWSys 4.15 # Average system read bandwidth in MiByte/s | 215system.physmem.avgRdBWSys 4.16 # Average system read bandwidth in MiByte/s |
| 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.physmem.busUtil 0.03 # Data bus utilization in percentage 219system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.physmem.busUtil 0.03 # Data bus utilization in percentage 219system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 221system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing | 221system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing |
| 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 223system.physmem.readRowHits 5935 # Number of row buffer hits during reads | 223system.physmem.readRowHits 5943 # Number of row buffer hits during reads |
| 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 225system.physmem.readRowHitRate 81.18 # Row buffer hit rate for reads | 225system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads |
| 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 227system.physmem.avgGap 15413205.58 # Average gap between requests 228system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined | 227system.physmem.avgGap 15388075.38 # Average gap between requests 228system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined |
| 229system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) | 229system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) |
| 231system.physmem_0.readEnergy 28657200 # Energy for read commands per rank (pJ) | 231system.physmem_0.readEnergy 28641600 # Energy for read commands per rank (pJ) |
| 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) | 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) |
| 234system.physmem_0.actBackEnergy 3231673425 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 64774920750 # Energy for precharge background per rank (pJ) 236system.physmem_0.totalEnergy 75402575040 # Total energy per rank (pJ) 237system.physmem_0.averagePower 669.157389 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 107755851914 # Time in different power states | 234system.physmem_0.actBackEnergy 3233168820 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 64773630750 # Energy for precharge background per rank (pJ) 236system.physmem_0.totalEnergy 75402764835 # Total energy per rank (pJ) 237system.physmem_0.averagePower 669.158858 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 107753956620 # Time in different power states |
| 239system.physmem_0.memoryStateTime::REF 3762720000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 239system.physmem_0.memoryStateTime::REF 3762720000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 241system.physmem_0.memoryStateTime::ACT 1164613086 # Time in different power states | 241system.physmem_0.memoryStateTime::ACT 1166688380 # Time in different power states |
| 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 243system.physmem_1.actEnergy 5496120 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 2998875 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 28064400 # Energy for read commands per rank (pJ) | 243system.physmem_1.actEnergy 5526360 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 3015375 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 28126800 # Energy for read commands per rank (pJ) |
| 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) | 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) |
| 248system.physmem_1.actBackEnergy 3295137510 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 64719250500 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 75410827725 # Total energy per rank (pJ) 251system.physmem_1.averagePower 669.230627 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 107661884129 # Time in different power states | 248system.physmem_1.actBackEnergy 3309876000 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 64706325000 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 75412749855 # Total energy per rank (pJ) 251system.physmem_1.averagePower 669.247655 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 107640832624 # Time in different power states |
| 253system.physmem_1.memoryStateTime::REF 3762720000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 253system.physmem_1.memoryStateTime::REF 3762720000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 255system.physmem_1.memoryStateTime::ACT 1258279621 # Time in different power states | 255system.physmem_1.memoryStateTime::ACT 1279848380 # Time in different power states |
| 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 257system.cpu.branchPred.lookups 37742989 # Number of BP lookups 258system.cpu.branchPred.condPredicted 20164516 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 1746156 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 18663196 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 17299233 # Number of BTB hits | 257system.cpu.branchPred.lookups 37743135 # Number of BP lookups 258system.cpu.branchPred.condPredicted 20164607 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 1746155 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 18663607 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 17299273 # Number of BTB hits |
| 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 263system.cpu.branchPred.BTBHitPct 92.691697 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 7223653 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 3816 # Number of incorrect RAS predictions. | 263system.cpu.branchPred.BTBHitPct 92.689870 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 7223670 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. |
| 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 191 # Number of system calls | 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 191 # Number of system calls |
| 384system.cpu.numCycles 225372210 # number of cpu cycles simulated | 384system.cpu.numCycles 225374070 # number of cpu cycles simulated |
| 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 387system.cpu.fetch.icacheStallCycles 12439138 # Number of cycles fetch is stalled on an Icache miss 388system.cpu.fetch.Insts 334051202 # Number of instructions fetch has processed 389system.cpu.fetch.Branches 37742989 # Number of branches that fetch encountered 390system.cpu.fetch.predictedBranches 24522886 # Number of branches that fetch has predicted taken 391system.cpu.fetch.Cycles 210855691 # Number of cycles fetch has run and was not squashing or blocked 392system.cpu.fetch.SquashCycles 3510707 # Number of cycles fetch has spent squashing 393system.cpu.fetch.MiscStallCycles 1284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 394system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR 395system.cpu.fetch.CacheLines 89092155 # Number of cache lines fetched 396system.cpu.fetch.IcacheSquashes 21708 # Number of outstanding Icache misses that were squashed 397system.cpu.fetch.rateDist::samples 225054059 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::mean 1.800470 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::stdev 1.229417 # Number of instructions fetched each cycle (Total) | 387system.cpu.fetch.icacheStallCycles 12439227 # Number of cycles fetch is stalled on an Icache miss 388system.cpu.fetch.Insts 334051995 # Number of instructions fetch has processed 389system.cpu.fetch.Branches 37743135 # Number of branches that fetch encountered 390system.cpu.fetch.predictedBranches 24522943 # Number of branches that fetch has predicted taken 391system.cpu.fetch.Cycles 210854521 # Number of cycles fetch has run and was not squashing or blocked 392system.cpu.fetch.SquashCycles 3510703 # Number of cycles fetch has spent squashing 393system.cpu.fetch.MiscStallCycles 1310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 394system.cpu.fetch.IcacheWaitRetryStallCycles 2474 # Number of stall cycles due to full MSHR 395system.cpu.fetch.CacheLines 89092353 # Number of cache lines fetched 396system.cpu.fetch.IcacheSquashes 21704 # Number of outstanding Icache misses that were squashed 397system.cpu.fetch.rateDist::samples 225052883 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::mean 1.800484 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::stdev 1.229411 # Number of instructions fetched each cycle (Total) |
| 400system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 400system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 401system.cpu.fetch.rateDist::0 51374086 22.83% 22.83% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::1 42891136 19.06% 41.89% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::2 30054592 13.35% 55.24% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::3 100734245 44.76% 100.00% # Number of instructions fetched each cycle (Total) | 401system.cpu.fetch.rateDist::0 51372314 22.83% 22.83% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::1 42891452 19.06% 41.89% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::2 30054577 13.35% 55.24% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::3 100734540 44.76% 100.00% # Number of instructions fetched each cycle (Total) |
| 405system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 405system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 408system.cpu.fetch.rateDist::total 225054059 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.branchRate 0.167470 # Number of branch fetches per cycle 410system.cpu.fetch.rate 1.482220 # Number of inst fetches per cycle 411system.cpu.decode.IdleCycles 27837229 # Number of cycles decode is idle 412system.cpu.decode.BlockedCycles 63912010 # Number of cycles decode is blocked 413system.cpu.decode.RunCycles 108618315 # Number of cycles decode is running 414system.cpu.decode.UnblockCycles 23065911 # Number of cycles decode is unblocking 415system.cpu.decode.SquashCycles 1620594 # Number of cycles decode is squashing 416system.cpu.decode.BranchResolved 6880048 # Number of times decode resolved a branch 417system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction 418system.cpu.decode.DecodedInsts 363546099 # Number of instructions handled by decode 419system.cpu.decode.SquashedInsts 6169805 # Number of squashed instructions handled by decode 420system.cpu.rename.SquashCycles 1620594 # Number of cycles rename is squashing 421system.cpu.rename.IdleCycles 45200014 # Number of cycles rename is idle 422system.cpu.rename.BlockCycles 17874059 # Number of cycles rename is blocking 423system.cpu.rename.serializeStallCycles 342377 # count of cycles rename stalled for serializing inst 424system.cpu.rename.RunCycles 113380979 # Number of cycles rename is running 425system.cpu.rename.UnblockCycles 46636036 # Number of cycles rename is unblocking 426system.cpu.rename.RenamedInsts 355768136 # Number of instructions processed by rename 427system.cpu.rename.SquashedInsts 2890465 # Number of squashed instructions processed by rename 428system.cpu.rename.ROBFullEvents 6610669 # Number of times rename has blocked due to ROB full | 408system.cpu.fetch.rateDist::total 225052883 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.branchRate 0.167469 # Number of branch fetches per cycle 410system.cpu.fetch.rate 1.482211 # Number of inst fetches per cycle 411system.cpu.decode.IdleCycles 27836779 # Number of cycles decode is idle 412system.cpu.decode.BlockedCycles 63911722 # Number of cycles decode is blocked 413system.cpu.decode.RunCycles 108618516 # Number of cycles decode is running 414system.cpu.decode.UnblockCycles 23065273 # Number of cycles decode is unblocking 415system.cpu.decode.SquashCycles 1620593 # Number of cycles decode is squashing 416system.cpu.decode.BranchResolved 6880055 # Number of times decode resolved a branch 417system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction 418system.cpu.decode.DecodedInsts 363544847 # Number of instructions handled by decode 419system.cpu.decode.SquashedInsts 6170021 # Number of squashed instructions handled by decode 420system.cpu.rename.SquashCycles 1620593 # Number of cycles rename is squashing 421system.cpu.rename.IdleCycles 45199707 # Number of cycles rename is idle 422system.cpu.rename.BlockCycles 17872689 # Number of cycles rename is blocking 423system.cpu.rename.serializeStallCycles 341815 # count of cycles rename stalled for serializing inst 424system.cpu.rename.RunCycles 113380410 # Number of cycles rename is running 425system.cpu.rename.UnblockCycles 46637669 # Number of cycles rename is unblocking 426system.cpu.rename.RenamedInsts 355768309 # Number of instructions processed by rename 427system.cpu.rename.SquashedInsts 2890306 # Number of squashed instructions processed by rename 428system.cpu.rename.ROBFullEvents 6609751 # Number of times rename has blocked due to ROB full |
| 429system.cpu.rename.IQFullEvents 177931 # Number of times rename has blocked due to IQ full | 429system.cpu.rename.IQFullEvents 177931 # Number of times rename has blocked due to IQ full |
| 430system.cpu.rename.LQFullEvents 7803674 # Number of times rename has blocked due to LQ full 431system.cpu.rename.SQFullEvents 21223053 # Number of times rename has blocked due to SQ full 432system.cpu.rename.FullRegisterEvents 2890533 # Number of times there has been no free registers 433system.cpu.rename.RenamedOperands 403406015 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 2534023592 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 350247327 # Number of integer rename lookups 436system.cpu.rename.fp_rename_lookups 194894263 # Number of floating rename lookups | 430system.cpu.rename.LQFullEvents 7804271 # Number of times rename has blocked due to LQ full 431system.cpu.rename.SQFullEvents 21223751 # Number of times rename has blocked due to SQ full 432system.cpu.rename.FullRegisterEvents 2890543 # Number of times there has been no free registers 433system.cpu.rename.RenamedOperands 403406246 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 2534025265 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 350247395 # Number of integer rename lookups 436system.cpu.rename.fp_rename_lookups 194894231 # Number of floating rename lookups |
| 437system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed | 437system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed |
| 438system.cpu.rename.UndoneMaps 31175964 # Number of HB maps that are undone due to squashing | 438system.cpu.rename.UndoneMaps 31176195 # Number of HB maps that are undone due to squashing |
| 439system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed 440system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed | 439system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed 440system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed |
| 441system.cpu.rename.skidInsts 55505783 # count of insts added to the skid buffer 442system.cpu.memDep0.insertedLoads 92416404 # Number of loads inserted to the mem dependence unit. 443system.cpu.memDep0.insertedStores 88498336 # Number of stores inserted to the mem dependence unit. 444system.cpu.memDep0.conflictingLoads 1661010 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 1846418 # Number of conflicting stores. 446system.cpu.iq.iqInstsAdded 353252226 # Number of instructions added to the IQ (excludes non-spec) | 441system.cpu.rename.skidInsts 55506509 # count of insts added to the skid buffer 442system.cpu.memDep0.insertedLoads 92416612 # Number of loads inserted to the mem dependence unit. 443system.cpu.memDep0.insertedStores 88498373 # Number of stores inserted to the mem dependence unit. 444system.cpu.memDep0.conflictingLoads 1661373 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 1847329 # Number of conflicting stores. 446system.cpu.iq.iqInstsAdded 353252571 # Number of instructions added to the IQ (excludes non-spec) |
| 447system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ | 447system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ |
| 448system.cpu.iq.iqInstsIssued 346438238 # Number of instructions issued 449system.cpu.iq.iqSquashedInstsIssued 2301579 # Number of squashed instructions issued 450system.cpu.iq.iqSquashedInstsExamined 25468650 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 73725461 # Number of squashed operands that are examined and possibly removed from graph | 448system.cpu.iq.iqInstsIssued 346438287 # Number of instructions issued 449system.cpu.iq.iqSquashedInstsIssued 2302047 # Number of squashed instructions issued 450system.cpu.iq.iqSquashedInstsExamined 25468995 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 73729207 # Number of squashed operands that are examined and possibly removed from graph |
| 452system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed | 452system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed |
| 453system.cpu.iq.issued_per_cycle::samples 225054059 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 1.539356 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 1.099855 # Number of insts issued each cycle | 453system.cpu.iq.issued_per_cycle::samples 225052883 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 1.539364 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 1.099868 # Number of insts issued each cycle |
| 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 457system.cpu.iq.issued_per_cycle::0 40665072 18.07% 18.07% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 78300215 34.79% 52.86% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 60997700 27.10% 79.96% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 34882254 15.50% 95.46% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::4 9557051 4.25% 99.71% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::5 642945 0.29% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 8822 0.00% 100.00% # Number of insts issued each cycle | 457system.cpu.iq.issued_per_cycle::0 40665148 18.07% 18.07% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 78299865 34.79% 52.86% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 60995131 27.10% 79.96% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 34883362 15.50% 95.46% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::4 9557615 4.25% 99.71% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::5 642958 0.29% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 8804 0.00% 100.00% # Number of insts issued each cycle |
| 464system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle | 464system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle |
| 469system.cpu.iq.issued_per_cycle::total 225054059 # Number of insts issued each cycle | 469system.cpu.iq.issued_per_cycle::total 225052883 # Number of insts issued each cycle |
| 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 471system.cpu.iq.fu_full::IntAlu 9490410 7.63% 7.63% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 7314 0.01% 7.64% # attempts to use FU when none available | 471system.cpu.iq.fu_full::IntAlu 9490613 7.63% 7.63% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 7317 0.01% 7.64% # attempts to use FU when none available |
| 473system.cpu.iq.fu_full::IntDiv 0 0.00% 7.64% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.64% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.64% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.64% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 7.64% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.64% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.64% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.64% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.64% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.64% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.64% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.64% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.64% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 7.64% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.64% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 7.64% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.64% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.64% # attempts to use FU when none available | 473system.cpu.iq.fu_full::IntDiv 0 0.00% 7.64% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.64% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.64% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.64% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 7.64% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.64% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.64% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.64% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.64% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.64% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.64% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.64% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.64% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 7.64% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.64% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 7.64% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.64% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.64% # attempts to use FU when none available |
| 491system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.84% # attempts to use FU when none available | 491system.cpu.iq.fu_full::SimdFloatAdd 255761 0.21% 7.84% # attempts to use FU when none available |
| 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available | 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available |
| 493system.cpu.iq.fu_full::SimdFloatCmp 126866 0.10% 7.95% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 93218 0.07% 8.02% # attempts to use FU when none available | 493system.cpu.iq.fu_full::SimdFloatCmp 126865 0.10% 7.95% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 93219 0.07% 8.02% # attempts to use FU when none available |
| 495system.cpu.iq.fu_full::SimdFloatDiv 68015 0.05% 8.08% # attempts to use FU when none available | 495system.cpu.iq.fu_full::SimdFloatDiv 68015 0.05% 8.08% # attempts to use FU when none available |
| 496system.cpu.iq.fu_full::SimdFloatMisc 721741 0.58% 8.66% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.89% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 683043 0.55% 9.44% # attempts to use FU when none available | 496system.cpu.iq.fu_full::SimdFloatMisc 721837 0.58% 8.66% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.90% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 683044 0.55% 9.44% # attempts to use FU when none available |
| 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available | 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available |
| 500system.cpu.iq.fu_full::MemRead 53642366 43.14% 52.58% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 58960700 47.42% 100.00% # attempts to use FU when none available | 500system.cpu.iq.fu_full::MemRead 53642383 43.14% 52.58% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 58959382 47.42% 100.00% # attempts to use FU when none available |
| 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 505system.cpu.iq.FU_type_0::IntAlu 110655140 31.94% 31.94% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 2148362 0.62% 32.56% # Type of FU issued | 505system.cpu.iq.FU_type_0::IntAlu 110655137 31.94% 31.94% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 2148355 0.62% 32.56% # Type of FU issued |
| 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued | 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued |
| 525system.cpu.iq.FU_type_0::SimdFloatAdd 6798396 1.96% 34.52% # Type of FU issued | 525system.cpu.iq.FU_type_0::SimdFloatAdd 6798397 1.96% 34.52% # Type of FU issued |
| 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued | 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued |
| 527system.cpu.iq.FU_type_0::SimdFloatCmp 8668155 2.50% 37.03% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 3332481 0.96% 37.99% # Type of FU issued | 527system.cpu.iq.FU_type_0::SimdFloatCmp 8668117 2.50% 37.03% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 3332482 0.96% 37.99% # Type of FU issued |
| 529system.cpu.iq.FU_type_0::SimdFloatDiv 1592458 0.46% 38.45% # Type of FU issued | 529system.cpu.iq.FU_type_0::SimdFloatDiv 1592458 0.46% 38.45% # Type of FU issued |
| 530system.cpu.iq.FU_type_0::SimdFloatMisc 20930094 6.04% 44.49% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 7182326 2.07% 46.56% # Type of FU issued | 530system.cpu.iq.FU_type_0::SimdFloatMisc 20930149 6.04% 44.49% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 7182320 2.07% 46.56% # Type of FU issued |
| 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148962 2.06% 48.63% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued | 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148962 2.06% 48.63% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued |
| 534system.cpu.iq.FU_type_0::MemRead 91923219 26.53% 75.21% # Type of FU issued 535system.cpu.iq.FU_type_0::MemWrite 85883359 24.79% 100.00% # Type of FU issued | 534system.cpu.iq.FU_type_0::MemRead 91923270 26.53% 75.21% # Type of FU issued 535system.cpu.iq.FU_type_0::MemWrite 85883354 24.79% 100.00% # Type of FU issued |
| 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 538system.cpu.iq.FU_type_0::total 346438238 # Type of FU issued 539system.cpu.iq.rate 1.537183 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 124346666 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.358929 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 757024395 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 251740362 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 223260150 # Number of integer instruction queue wakeup accesses 545system.cpu.iq.fp_inst_queue_reads 287554385 # Number of floating instruction queue reads 546system.cpu.iq.fp_inst_queue_writes 127018791 # Number of floating instruction queue writes 547system.cpu.iq.fp_inst_queue_wakeup_accesses 117424955 # Number of floating instruction queue wakeup accesses 548system.cpu.iq.int_alu_accesses 303230405 # Number of integer alu accesses 549system.cpu.iq.fp_alu_accesses 167554499 # Number of floating point alu accesses 550system.cpu.iew.lsq.thread0.forwLoads 5064919 # Number of loads that had data forwarded from stores | 538system.cpu.iq.FU_type_0::total 346438287 # Type of FU issued 539system.cpu.iq.rate 1.537170 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 124345667 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.358926 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 757022758 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 251740405 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 223260402 # Number of integer instruction queue wakeup accesses 545system.cpu.iq.fp_inst_queue_reads 287554413 # Number of floating instruction queue reads 546system.cpu.iq.fp_inst_queue_writes 127019437 # Number of floating instruction queue writes 547system.cpu.iq.fp_inst_queue_wakeup_accesses 117424930 # Number of floating instruction queue wakeup accesses 548system.cpu.iq.int_alu_accesses 303229780 # Number of integer alu accesses 549system.cpu.iq.fp_alu_accesses 167554174 # Number of floating point alu accesses 550system.cpu.iew.lsq.thread0.forwLoads 5064825 # Number of loads that had data forwarded from stores |
| 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 552system.cpu.iew.lsq.thread0.squashedLoads 6684129 # Number of loads squashed 553system.cpu.iew.lsq.thread0.ignoredResponses 13573 # Number of memory responses ignored because the instruction is squashed 554system.cpu.iew.lsq.thread0.memOrderViolation 10255 # Number of memory ordering violations 555system.cpu.iew.lsq.thread0.squashedStores 6122719 # Number of stores squashed | 552system.cpu.iew.lsq.thread0.squashedLoads 6684337 # Number of loads squashed 553system.cpu.iew.lsq.thread0.ignoredResponses 13570 # Number of memory responses ignored because the instruction is squashed 554system.cpu.iew.lsq.thread0.memOrderViolation 10254 # Number of memory ordering violations 555system.cpu.iew.lsq.thread0.squashedStores 6122756 # Number of stores squashed |
| 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 558system.cpu.iew.lsq.thread0.rescheduledLoads 155303 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 607776 # Number of times an access to memory failed due to the cache being blocked | 558system.cpu.iew.lsq.thread0.rescheduledLoads 155338 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 607759 # Number of times an access to memory failed due to the cache being blocked |
| 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 561system.cpu.iew.iewSquashCycles 1620594 # Number of cycles IEW is squashing 562system.cpu.iew.iewBlockCycles 2118849 # Number of cycles IEW is blocking 563system.cpu.iew.iewUnblockCycles 332046 # Number of cycles IEW is unblocking 564system.cpu.iew.iewDispatchedInsts 353281117 # Number of instructions dispatched to IQ | 561system.cpu.iew.iewSquashCycles 1620593 # Number of cycles IEW is squashing 562system.cpu.iew.iewBlockCycles 2118874 # Number of cycles IEW is blocking 563system.cpu.iew.iewUnblockCycles 332196 # Number of cycles IEW is unblocking 564system.cpu.iew.iewDispatchedInsts 353281462 # Number of instructions dispatched to IQ |
| 565system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 565system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 566system.cpu.iew.iewDispLoadInsts 92416404 # Number of dispatched load instructions 567system.cpu.iew.iewDispStoreInsts 88498336 # Number of dispatched store instructions | 566system.cpu.iew.iewDispLoadInsts 92416612 # Number of dispatched load instructions 567system.cpu.iew.iewDispStoreInsts 88498373 # Number of dispatched store instructions |
| 568system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall | 568system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall |
| 570system.cpu.iew.iewLSQFullEvents 338505 # Number of times the LSQ has become full, causing a stall 571system.cpu.iew.memOrderViolationEvents 10255 # Number of memory order violations 572system.cpu.iew.predictedTakenIncorrect 1220656 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 439058 # Number of branches that were predicted not taken incorrectly 574system.cpu.iew.branchMispredicts 1659714 # Number of branch mispredicts detected at execute 575system.cpu.iew.iewExecutedInsts 342448377 # Number of executed instructions 576system.cpu.iew.iewExecLoadInsts 90703712 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 3989861 # Number of squashed instructions skipped in execute | 570system.cpu.iew.iewLSQFullEvents 338656 # Number of times the LSQ has become full, causing a stall 571system.cpu.iew.memOrderViolationEvents 10254 # Number of memory order violations 572system.cpu.iew.predictedTakenIncorrect 1220664 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 439075 # Number of branches that were predicted not taken incorrectly 574system.cpu.iew.branchMispredicts 1659739 # Number of branch mispredicts detected at execute 575system.cpu.iew.iewExecutedInsts 342448688 # Number of executed instructions 576system.cpu.iew.iewExecLoadInsts 90703769 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 3989599 # Number of squashed instructions skipped in execute |
| 578system.cpu.iew.exec_swp 0 # number of swp insts executed 579system.cpu.iew.exec_nop 865 # number of nop insts executed | 578system.cpu.iew.exec_swp 0 # number of swp insts executed 579system.cpu.iew.exec_nop 865 # number of nop insts executed |
| 580system.cpu.iew.exec_refs 175291126 # number of memory reference insts executed 581system.cpu.iew.exec_branches 31752707 # Number of branches executed 582system.cpu.iew.exec_stores 84587414 # Number of stores executed 583system.cpu.iew.exec_rate 1.519479 # Inst execution rate 584system.cpu.iew.wb_sent 340943800 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 340685105 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 153662327 # num instructions producing a value 587system.cpu.iew.wb_consumers 266738216 # num instructions consuming a value | 580system.cpu.iew.exec_refs 175291174 # number of memory reference insts executed 581system.cpu.iew.exec_branches 31752726 # Number of branches executed 582system.cpu.iew.exec_stores 84587405 # Number of stores executed 583system.cpu.iew.exec_rate 1.519468 # Inst execution rate 584system.cpu.iew.wb_sent 340944051 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 340685332 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 153662647 # num instructions producing a value 587system.cpu.iew.wb_consumers 266737544 # num instructions consuming a value |
| 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 589system.cpu.iew.wb_rate 1.511655 # insts written-back per cycle 590system.cpu.iew.wb_fanout 0.576079 # average fanout of values written-back | 589system.cpu.iew.wb_rate 1.511644 # insts written-back per cycle 590system.cpu.iew.wb_fanout 0.576082 # average fanout of values written-back |
| 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 592system.cpu.commit.commitSquashedInsts 23082519 # The number of squashed insts skipped by commit | 592system.cpu.commit.commitSquashedInsts 23083260 # The number of squashed insts skipped by commit |
| 593system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 594system.cpu.commit.branchMispredicts 1611397 # The number of times a branch was mispredicted | 593system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 594system.cpu.commit.branchMispredicts 1611397 # The number of times a branch was mispredicted |
| 595system.cpu.commit.committed_per_cycle::samples 221328864 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 1.481109 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 2.050764 # Number of insts commited each cycle | 595system.cpu.commit.committed_per_cycle::samples 221327720 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 1.481117 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 2.050757 # Number of insts commited each cycle |
| 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 599system.cpu.commit.committed_per_cycle::0 87530154 39.55% 39.55% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 70479011 31.84% 71.39% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 20814829 9.40% 80.80% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 13433176 6.07% 86.86% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 8801116 3.98% 90.84% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 4514131 2.04% 92.88% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 2986629 1.35% 94.23% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 2449420 1.11% 95.34% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 10320398 4.66% 100.00% # Number of insts commited each cycle | 599system.cpu.commit.committed_per_cycle::0 87528718 39.55% 39.55% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 70478843 31.84% 71.39% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 20814822 9.40% 80.80% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 13433890 6.07% 86.86% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 8801339 3.98% 90.84% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 4513701 2.04% 92.88% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 2986759 1.35% 94.23% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 2449542 1.11% 95.34% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 10320106 4.66% 100.00% # Number of insts commited each cycle |
| 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 611system.cpu.commit.committed_per_cycle::total 221328864 # Number of insts commited each cycle | 611system.cpu.commit.committed_per_cycle::total 221327720 # Number of insts commited each cycle |
| 612system.cpu.commit.committedInsts 273037832 # Number of instructions committed 613system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 168107892 # Number of memory references committed 616system.cpu.commit.loads 85732275 # Number of loads committed 617system.cpu.commit.membars 11033 # Number of memory barriers committed 618system.cpu.commit.branches 30563526 # Number of branches committed 619system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 649system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction | 612system.cpu.commit.committedInsts 273037832 # Number of instructions committed 613system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 168107892 # Number of memory references committed 616system.cpu.commit.loads 85732275 # Number of loads committed 617system.cpu.commit.membars 11033 # Number of memory barriers committed 618system.cpu.commit.branches 30563526 # Number of branches committed 619system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 649system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction |
| 657system.cpu.commit.bw_lim_events 10320398 # number cycles where commit BW limit reached 658system.cpu.rob.rob_reads 561900676 # The number of ROB reads 659system.cpu.rob.rob_writes 705518580 # The number of ROB writes 660system.cpu.timesIdled 50864 # Number of times that the entire CPU went into an idle state and unscheduled itself 661system.cpu.idleCycles 318151 # Total number of cycles that the CPU has spent unscheduled due to idling | 657system.cpu.commit.bw_lim_events 10320106 # number cycles where commit BW limit reached 658system.cpu.rob.rob_reads 561900565 # The number of ROB reads 659system.cpu.rob.rob_writes 705520050 # The number of ROB writes 660system.cpu.timesIdled 50865 # Number of times that the entire CPU went into an idle state and unscheduled itself 661system.cpu.idleCycles 321187 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 662system.cpu.committedInsts 273037220 # Number of Instructions Simulated 663system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated | 662system.cpu.committedInsts 273037220 # Number of Instructions Simulated 663system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated |
| 664system.cpu.cpi 0.825427 # CPI: Cycles Per Instruction 665system.cpu.cpi_total 0.825427 # CPI: Total CPI of All Threads 666system.cpu.ipc 1.211495 # IPC: Instructions Per Cycle 667system.cpu.ipc_total 1.211495 # IPC: Total IPC of All Threads 668system.cpu.int_regfile_reads 331331443 # number of integer regfile reads 669system.cpu.int_regfile_writes 136939322 # number of integer regfile writes 670system.cpu.fp_regfile_reads 187108010 # number of floating regfile reads 671system.cpu.fp_regfile_writes 132178699 # number of floating regfile writes 672system.cpu.cc_regfile_reads 1297132712 # number of cc regfile reads 673system.cpu.cc_regfile_writes 80241070 # number of cc regfile writes 674system.cpu.misc_regfile_reads 1183128145 # number of misc regfile reads | 664system.cpu.cpi 0.825434 # CPI: Cycles Per Instruction 665system.cpu.cpi_total 0.825434 # CPI: Total CPI of All Threads 666system.cpu.ipc 1.211485 # IPC: Instructions Per Cycle 667system.cpu.ipc_total 1.211485 # IPC: Total IPC of All Threads 668system.cpu.int_regfile_reads 331332035 # number of integer regfile reads 669system.cpu.int_regfile_writes 136939352 # number of integer regfile writes 670system.cpu.fp_regfile_reads 187107868 # number of floating regfile reads 671system.cpu.fp_regfile_writes 132178738 # number of floating regfile writes 672system.cpu.cc_regfile_reads 1297133606 # number of cc regfile reads 673system.cpu.cc_regfile_writes 80241640 # number of cc regfile writes 674system.cpu.misc_regfile_reads 1183127847 # number of misc regfile reads |
| 675system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 676system.cpu.dcache.tags.replacements 1533845 # number of replacements | 675system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 676system.cpu.dcache.tags.replacements 1533845 # number of replacements |
| 677system.cpu.dcache.tags.tagsinuse 511.844014 # Cycle average of tags in use 678system.cpu.dcache.tags.total_refs 163642665 # Total number of references to valid blocks. | 677system.cpu.dcache.tags.tagsinuse 511.843427 # Cycle average of tags in use 678system.cpu.dcache.tags.total_refs 163642817 # Total number of references to valid blocks. |
| 679system.cpu.dcache.tags.sampled_refs 1534357 # Sample count of references to valid blocks. | 679system.cpu.dcache.tags.sampled_refs 1534357 # Sample count of references to valid blocks. |
| 680system.cpu.dcache.tags.avg_refs 106.652275 # Average number of references to valid blocks. 681system.cpu.dcache.tags.warmup_cycle 82317000 # Cycle when the warmup percentage was hit. 682system.cpu.dcache.tags.occ_blocks::cpu.data 511.844014 # Average occupied blocks per requestor 683system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy 684system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy | 680system.cpu.dcache.tags.avg_refs 106.652374 # Average number of references to valid blocks. 681system.cpu.dcache.tags.warmup_cycle 82681000 # Cycle when the warmup percentage was hit. 682system.cpu.dcache.tags.occ_blocks::cpu.data 511.843427 # Average occupied blocks per requestor 683system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy 684system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy |
| 685system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 686system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 687system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id 688system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id 689system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 690system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 685system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 686system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 687system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id 688system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id 689system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 690system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 691system.cpu.dcache.tags.tag_accesses 336636785 # Number of tag accesses 692system.cpu.dcache.tags.data_accesses 336636785 # Number of data accesses 693system.cpu.dcache.ReadReq_hits::cpu.data 82609327 # number of ReadReq hits 694system.cpu.dcache.ReadReq_hits::total 82609327 # number of ReadReq hits 695system.cpu.dcache.WriteReq_hits::cpu.data 80941037 # number of WriteReq hits 696system.cpu.dcache.WriteReq_hits::total 80941037 # number of WriteReq hits 697system.cpu.dcache.SoftPFReq_hits::cpu.data 70495 # number of SoftPFReq hits 698system.cpu.dcache.SoftPFReq_hits::total 70495 # number of SoftPFReq hits | 691system.cpu.dcache.tags.tag_accesses 336637061 # Number of tag accesses 692system.cpu.dcache.tags.data_accesses 336637061 # Number of data accesses 693system.cpu.dcache.ReadReq_hits::cpu.data 82609464 # number of ReadReq hits 694system.cpu.dcache.ReadReq_hits::total 82609464 # number of ReadReq hits 695system.cpu.dcache.WriteReq_hits::cpu.data 80941053 # number of WriteReq hits 696system.cpu.dcache.WriteReq_hits::total 80941053 # number of WriteReq hits 697system.cpu.dcache.SoftPFReq_hits::cpu.data 70494 # number of SoftPFReq hits 698system.cpu.dcache.SoftPFReq_hits::total 70494 # number of SoftPFReq hits |
| 699system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits 700system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits 701system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 702system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits | 699system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits 700system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits 701system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 702system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits |
| 703system.cpu.dcache.demand_hits::cpu.data 163550364 # number of demand (read+write) hits 704system.cpu.dcache.demand_hits::total 163550364 # number of demand (read+write) hits 705system.cpu.dcache.overall_hits::cpu.data 163620859 # number of overall hits 706system.cpu.dcache.overall_hits::total 163620859 # number of overall hits 707system.cpu.dcache.ReadReq_misses::cpu.data 2796866 # number of ReadReq misses 708system.cpu.dcache.ReadReq_misses::total 2796866 # number of ReadReq misses 709system.cpu.dcache.WriteReq_misses::cpu.data 1111662 # number of WriteReq misses 710system.cpu.dcache.WriteReq_misses::total 1111662 # number of WriteReq misses | 703system.cpu.dcache.demand_hits::cpu.data 163550517 # number of demand (read+write) hits 704system.cpu.dcache.demand_hits::total 163550517 # number of demand (read+write) hits 705system.cpu.dcache.overall_hits::cpu.data 163621011 # number of overall hits 706system.cpu.dcache.overall_hits::total 163621011 # number of overall hits 707system.cpu.dcache.ReadReq_misses::cpu.data 2796868 # number of ReadReq misses 708system.cpu.dcache.ReadReq_misses::total 2796868 # number of ReadReq misses 709system.cpu.dcache.WriteReq_misses::cpu.data 1111646 # number of WriteReq misses 710system.cpu.dcache.WriteReq_misses::total 1111646 # number of WriteReq misses |
| 711system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses 712system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses 713system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses 714system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses | 711system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses 712system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses 713system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses 714system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses |
| 715system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses 716system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses 717system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses 718system.cpu.dcache.overall_misses::total 3908546 # number of overall misses 719system.cpu.dcache.ReadReq_miss_latency::cpu.data 22404027000 # number of ReadReq miss cycles 720system.cpu.dcache.ReadReq_miss_latency::total 22404027000 # number of ReadReq miss cycles 721system.cpu.dcache.WriteReq_miss_latency::cpu.data 8967503998 # number of WriteReq miss cycles 722system.cpu.dcache.WriteReq_miss_latency::total 8967503998 # number of WriteReq miss cycles | 715system.cpu.dcache.demand_misses::cpu.data 3908514 # number of demand (read+write) misses 716system.cpu.dcache.demand_misses::total 3908514 # number of demand (read+write) misses 717system.cpu.dcache.overall_misses::cpu.data 3908532 # number of overall misses 718system.cpu.dcache.overall_misses::total 3908532 # number of overall misses 719system.cpu.dcache.ReadReq_miss_latency::cpu.data 22403262000 # number of ReadReq miss cycles 720system.cpu.dcache.ReadReq_miss_latency::total 22403262000 # number of ReadReq miss cycles 721system.cpu.dcache.WriteReq_miss_latency::cpu.data 8965991000 # number of WriteReq miss cycles 722system.cpu.dcache.WriteReq_miss_latency::total 8965991000 # number of WriteReq miss cycles |
| 723system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles 724system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles | 723system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles 724system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles |
| 725system.cpu.dcache.demand_miss_latency::cpu.data 31371530998 # number of demand (read+write) miss cycles 726system.cpu.dcache.demand_miss_latency::total 31371530998 # number of demand (read+write) miss cycles 727system.cpu.dcache.overall_miss_latency::cpu.data 31371530998 # number of overall miss cycles 728system.cpu.dcache.overall_miss_latency::total 31371530998 # number of overall miss cycles 729system.cpu.dcache.ReadReq_accesses::cpu.data 85406193 # number of ReadReq accesses(hits+misses) 730system.cpu.dcache.ReadReq_accesses::total 85406193 # number of ReadReq accesses(hits+misses) | 725system.cpu.dcache.demand_miss_latency::cpu.data 31369253000 # number of demand (read+write) miss cycles 726system.cpu.dcache.demand_miss_latency::total 31369253000 # number of demand (read+write) miss cycles 727system.cpu.dcache.overall_miss_latency::cpu.data 31369253000 # number of overall miss cycles 728system.cpu.dcache.overall_miss_latency::total 31369253000 # number of overall miss cycles 729system.cpu.dcache.ReadReq_accesses::cpu.data 85406332 # number of ReadReq accesses(hits+misses) 730system.cpu.dcache.ReadReq_accesses::total 85406332 # number of ReadReq accesses(hits+misses) |
| 731system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 732system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) | 731system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 732system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) |
| 733system.cpu.dcache.SoftPFReq_accesses::cpu.data 70513 # number of SoftPFReq accesses(hits+misses) 734system.cpu.dcache.SoftPFReq_accesses::total 70513 # number of SoftPFReq accesses(hits+misses) | 733system.cpu.dcache.SoftPFReq_accesses::cpu.data 70512 # number of SoftPFReq accesses(hits+misses) 734system.cpu.dcache.SoftPFReq_accesses::total 70512 # number of SoftPFReq accesses(hits+misses) |
| 735system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) 736system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) 737system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 738system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) | 735system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) 736system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) 737system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 738system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) |
| 739system.cpu.dcache.demand_accesses::cpu.data 167458892 # number of demand (read+write) accesses 740system.cpu.dcache.demand_accesses::total 167458892 # number of demand (read+write) accesses 741system.cpu.dcache.overall_accesses::cpu.data 167529405 # number of overall (read+write) accesses 742system.cpu.dcache.overall_accesses::total 167529405 # number of overall (read+write) accesses | 739system.cpu.dcache.demand_accesses::cpu.data 167459031 # number of demand (read+write) accesses 740system.cpu.dcache.demand_accesses::total 167459031 # number of demand (read+write) accesses 741system.cpu.dcache.overall_accesses::cpu.data 167529543 # number of overall (read+write) accesses 742system.cpu.dcache.overall_accesses::total 167529543 # number of overall (read+write) accesses |
| 743system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032748 # miss rate for ReadReq accesses 744system.cpu.dcache.ReadReq_miss_rate::total 0.032748 # miss rate for ReadReq accesses 745system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses 746system.cpu.dcache.WriteReq_miss_rate::total 0.013548 # miss rate for WriteReq accesses 747system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses 748system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses 749system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses 750system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses 751system.cpu.dcache.demand_miss_rate::cpu.data 0.023340 # miss rate for demand accesses 752system.cpu.dcache.demand_miss_rate::total 0.023340 # miss rate for demand accesses | 743system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032748 # miss rate for ReadReq accesses 744system.cpu.dcache.ReadReq_miss_rate::total 0.032748 # miss rate for ReadReq accesses 745system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses 746system.cpu.dcache.WriteReq_miss_rate::total 0.013548 # miss rate for WriteReq accesses 747system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses 748system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses 749system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses 750system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses 751system.cpu.dcache.demand_miss_rate::cpu.data 0.023340 # miss rate for demand accesses 752system.cpu.dcache.demand_miss_rate::total 0.023340 # miss rate for demand accesses |
| 753system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses 754system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses 755system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.404145 # average ReadReq miss latency 756system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.404145 # average ReadReq miss latency 757system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8066.754102 # average WriteReq miss latency 758system.cpu.dcache.WriteReq_avg_miss_latency::total 8066.754102 # average WriteReq miss latency | 753system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses 754system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses 755system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.124897 # average ReadReq miss latency 756system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.124897 # average ReadReq miss latency 757system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8065.509164 # average WriteReq miss latency 758system.cpu.dcache.WriteReq_avg_miss_latency::total 8065.509164 # average WriteReq miss latency |
| 759system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency 760system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency | 759system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency 760system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency |
| 761system.cpu.dcache.demand_avg_miss_latency::cpu.data 8026.431178 # average overall miss latency 762system.cpu.dcache.demand_avg_miss_latency::total 8026.431178 # average overall miss latency 763system.cpu.dcache.overall_avg_miss_latency::cpu.data 8026.394214 # average overall miss latency 764system.cpu.dcache.overall_avg_miss_latency::total 8026.394214 # average overall miss latency | 761system.cpu.dcache.demand_avg_miss_latency::cpu.data 8025.877098 # average overall miss latency 762system.cpu.dcache.demand_avg_miss_latency::total 8025.877098 # average overall miss latency 763system.cpu.dcache.overall_avg_miss_latency::cpu.data 8025.840136 # average overall miss latency 764system.cpu.dcache.overall_avg_miss_latency::total 8025.840136 # average overall miss latency |
| 765system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 765system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 766system.cpu.dcache.blocked_cycles::no_targets 1059827 # number of cycles access was blocked | 766system.cpu.dcache.blocked_cycles::no_targets 1060412 # number of cycles access was blocked |
| 767system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked | 767system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 768system.cpu.dcache.blocked::no_targets 134751 # number of cycles access was blocked | 768system.cpu.dcache.blocked::no_targets 134750 # number of cycles access was blocked |
| 769system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 769system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 770system.cpu.dcache.avg_blocked_cycles::no_targets 7.865077 # average number of cycles each access was blocked | 770system.cpu.dcache.avg_blocked_cycles::no_targets 7.869477 # average number of cycles each access was blocked |
| 771system.cpu.dcache.fast_writes 0 # number of fast writes performed 772system.cpu.dcache.cache_copies 0 # number of cache copies performed 773system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks 774system.cpu.dcache.writebacks::total 966339 # number of writebacks | 771system.cpu.dcache.fast_writes 0 # number of fast writes performed 772system.cpu.dcache.cache_copies 0 # number of cache copies performed 773system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks 774system.cpu.dcache.writebacks::total 966339 # number of writebacks |
| 775system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483173 # number of ReadReq MSHR hits 776system.cpu.dcache.ReadReq_mshr_hits::total 1483173 # number of ReadReq MSHR hits 777system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891007 # number of WriteReq MSHR hits 778system.cpu.dcache.WriteReq_mshr_hits::total 891007 # number of WriteReq MSHR hits | 775system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483175 # number of ReadReq MSHR hits 776system.cpu.dcache.ReadReq_mshr_hits::total 1483175 # number of ReadReq MSHR hits 777system.cpu.dcache.WriteReq_mshr_hits::cpu.data 890991 # number of WriteReq MSHR hits 778system.cpu.dcache.WriteReq_mshr_hits::total 890991 # number of WriteReq MSHR hits |
| 779system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits 780system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits | 779system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits 780system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits |
| 781system.cpu.dcache.demand_mshr_hits::cpu.data 2374180 # number of demand (read+write) MSHR hits 782system.cpu.dcache.demand_mshr_hits::total 2374180 # number of demand (read+write) MSHR hits 783system.cpu.dcache.overall_mshr_hits::cpu.data 2374180 # number of overall MSHR hits 784system.cpu.dcache.overall_mshr_hits::total 2374180 # number of overall MSHR hits | 781system.cpu.dcache.demand_mshr_hits::cpu.data 2374166 # number of demand (read+write) MSHR hits 782system.cpu.dcache.demand_mshr_hits::total 2374166 # number of demand (read+write) MSHR hits 783system.cpu.dcache.overall_mshr_hits::cpu.data 2374166 # number of overall MSHR hits 784system.cpu.dcache.overall_mshr_hits::total 2374166 # number of overall MSHR hits |
| 785system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313693 # number of ReadReq MSHR misses 786system.cpu.dcache.ReadReq_mshr_misses::total 1313693 # number of ReadReq MSHR misses 787system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses 788system.cpu.dcache.WriteReq_mshr_misses::total 220655 # number of WriteReq MSHR misses 789system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 790system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses 791system.cpu.dcache.demand_mshr_misses::cpu.data 1534348 # number of demand (read+write) MSHR misses 792system.cpu.dcache.demand_mshr_misses::total 1534348 # number of demand (read+write) MSHR misses 793system.cpu.dcache.overall_mshr_misses::cpu.data 1534359 # number of overall MSHR misses 794system.cpu.dcache.overall_mshr_misses::total 1534359 # number of overall MSHR misses | 785system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313693 # number of ReadReq MSHR misses 786system.cpu.dcache.ReadReq_mshr_misses::total 1313693 # number of ReadReq MSHR misses 787system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses 788system.cpu.dcache.WriteReq_mshr_misses::total 220655 # number of WriteReq MSHR misses 789system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 790system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses 791system.cpu.dcache.demand_mshr_misses::cpu.data 1534348 # number of demand (read+write) MSHR misses 792system.cpu.dcache.demand_mshr_misses::total 1534348 # number of demand (read+write) MSHR misses 793system.cpu.dcache.overall_mshr_misses::cpu.data 1534359 # number of overall MSHR misses 794system.cpu.dcache.overall_mshr_misses::total 1534359 # number of overall MSHR misses |
| 795system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10622731000 # number of ReadReq MSHR miss cycles 796system.cpu.dcache.ReadReq_mshr_miss_latency::total 10622731000 # number of ReadReq MSHR miss cycles 797system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1827670779 # number of WriteReq MSHR miss cycles 798system.cpu.dcache.WriteReq_mshr_miss_latency::total 1827670779 # number of WriteReq MSHR miss cycles | 795system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10623648000 # number of ReadReq MSHR miss cycles 796system.cpu.dcache.ReadReq_mshr_miss_latency::total 10623648000 # number of ReadReq MSHR miss cycles 797system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1826747781 # number of WriteReq MSHR miss cycles 798system.cpu.dcache.WriteReq_mshr_miss_latency::total 1826747781 # number of WriteReq MSHR miss cycles |
| 799system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681000 # number of SoftPFReq MSHR miss cycles 800system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681000 # number of SoftPFReq MSHR miss cycles | 799system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681000 # number of SoftPFReq MSHR miss cycles 800system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681000 # number of SoftPFReq MSHR miss cycles |
| 801system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450401779 # number of demand (read+write) MSHR miss cycles 802system.cpu.dcache.demand_mshr_miss_latency::total 12450401779 # number of demand (read+write) MSHR miss cycles 803system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451082779 # number of overall MSHR miss cycles 804system.cpu.dcache.overall_mshr_miss_latency::total 12451082779 # number of overall MSHR miss cycles | 801system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450395781 # number of demand (read+write) MSHR miss cycles 802system.cpu.dcache.demand_mshr_miss_latency::total 12450395781 # number of demand (read+write) MSHR miss cycles 803system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451076781 # number of overall MSHR miss cycles 804system.cpu.dcache.overall_mshr_miss_latency::total 12451076781 # number of overall MSHR miss cycles |
| 805system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses 806system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses 807system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses 808system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses 809system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses 810system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses 811system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses 812system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses 813system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses 814system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses | 805system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses 806system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses 807system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses 808system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses 809system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses 810system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses 811system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses 812system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses 813system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses 814system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses |
| 815system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.159399 # average ReadReq mshr miss latency 816system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.159399 # average ReadReq mshr miss latency 817system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8282.933897 # average WriteReq mshr miss latency 818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8282.933897 # average WriteReq mshr miss latency | 815system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.857432 # average ReadReq mshr miss latency 816system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.857432 # average ReadReq mshr miss latency 817system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8278.750905 # average WriteReq mshr miss latency 818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8278.750905 # average WriteReq mshr miss latency |
| 819system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909 # average SoftPFReq mshr miss latency 820system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909 # average SoftPFReq mshr miss latency | 819system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909 # average SoftPFReq mshr miss latency 820system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909 # average SoftPFReq mshr miss latency |
| 821system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.457593 # average overall mshr miss latency 822system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.457593 # average overall mshr miss latency 823system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.843253 # average overall mshr miss latency 824system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.843253 # average overall mshr miss latency | 821system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.453684 # average overall mshr miss latency 822system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.453684 # average overall mshr miss latency 823system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.839344 # average overall mshr miss latency 824system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.839344 # average overall mshr miss latency |
| 825system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 825system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 826system.cpu.icache.tags.replacements 715634 # number of replacements 827system.cpu.icache.tags.tagsinuse 511.830268 # Cycle average of tags in use 828system.cpu.icache.tags.total_refs 88370349 # Total number of references to valid blocks. 829system.cpu.icache.tags.sampled_refs 716146 # Sample count of references to valid blocks. 830system.cpu.icache.tags.avg_refs 123.397113 # Average number of references to valid blocks. 831system.cpu.icache.tags.warmup_cycle 324802500 # Cycle when the warmup percentage was hit. 832system.cpu.icache.tags.occ_blocks::cpu.inst 511.830268 # Average occupied blocks per requestor 833system.cpu.icache.tags.occ_percent::cpu.inst 0.999668 # Average percentage of cache occupancy 834system.cpu.icache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy | 826system.cpu.icache.tags.replacements 715635 # number of replacements 827system.cpu.icache.tags.tagsinuse 511.829472 # Cycle average of tags in use 828system.cpu.icache.tags.total_refs 88370544 # Total number of references to valid blocks. 829system.cpu.icache.tags.sampled_refs 716147 # Sample count of references to valid blocks. 830system.cpu.icache.tags.avg_refs 123.397213 # Average number of references to valid blocks. 831system.cpu.icache.tags.warmup_cycle 326419500 # Cycle when the warmup percentage was hit. 832system.cpu.icache.tags.occ_blocks::cpu.inst 511.829472 # Average occupied blocks per requestor 833system.cpu.icache.tags.occ_percent::cpu.inst 0.999667 # Average percentage of cache occupancy 834system.cpu.icache.tags.occ_percent::total 0.999667 # Average percentage of cache occupancy |
| 835system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 836system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id 840system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id 841system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 835system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 836system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id 840system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id 841system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 842system.cpu.icache.tags.tag_accesses 178900425 # Number of tag accesses 843system.cpu.icache.tags.data_accesses 178900425 # Number of data accesses 844system.cpu.icache.ReadReq_hits::cpu.inst 88370349 # number of ReadReq hits 845system.cpu.icache.ReadReq_hits::total 88370349 # number of ReadReq hits 846system.cpu.icache.demand_hits::cpu.inst 88370349 # number of demand (read+write) hits 847system.cpu.icache.demand_hits::total 88370349 # number of demand (read+write) hits 848system.cpu.icache.overall_hits::cpu.inst 88370349 # number of overall hits 849system.cpu.icache.overall_hits::total 88370349 # number of overall hits 850system.cpu.icache.ReadReq_misses::cpu.inst 721790 # number of ReadReq misses 851system.cpu.icache.ReadReq_misses::total 721790 # number of ReadReq misses 852system.cpu.icache.demand_misses::cpu.inst 721790 # number of demand (read+write) misses 853system.cpu.icache.demand_misses::total 721790 # number of demand (read+write) misses 854system.cpu.icache.overall_misses::cpu.inst 721790 # number of overall misses 855system.cpu.icache.overall_misses::total 721790 # number of overall misses 856system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973224944 # number of ReadReq miss cycles 857system.cpu.icache.ReadReq_miss_latency::total 5973224944 # number of ReadReq miss cycles 858system.cpu.icache.demand_miss_latency::cpu.inst 5973224944 # number of demand (read+write) miss cycles 859system.cpu.icache.demand_miss_latency::total 5973224944 # number of demand (read+write) miss cycles 860system.cpu.icache.overall_miss_latency::cpu.inst 5973224944 # number of overall miss cycles 861system.cpu.icache.overall_miss_latency::total 5973224944 # number of overall miss cycles 862system.cpu.icache.ReadReq_accesses::cpu.inst 89092139 # number of ReadReq accesses(hits+misses) 863system.cpu.icache.ReadReq_accesses::total 89092139 # number of ReadReq accesses(hits+misses) 864system.cpu.icache.demand_accesses::cpu.inst 89092139 # number of demand (read+write) accesses 865system.cpu.icache.demand_accesses::total 89092139 # number of demand (read+write) accesses 866system.cpu.icache.overall_accesses::cpu.inst 89092139 # number of overall (read+write) accesses 867system.cpu.icache.overall_accesses::total 89092139 # number of overall (read+write) accesses | 842system.cpu.icache.tags.tag_accesses 178900820 # Number of tag accesses 843system.cpu.icache.tags.data_accesses 178900820 # Number of data accesses 844system.cpu.icache.ReadReq_hits::cpu.inst 88370544 # number of ReadReq hits 845system.cpu.icache.ReadReq_hits::total 88370544 # number of ReadReq hits 846system.cpu.icache.demand_hits::cpu.inst 88370544 # number of demand (read+write) hits 847system.cpu.icache.demand_hits::total 88370544 # number of demand (read+write) hits 848system.cpu.icache.overall_hits::cpu.inst 88370544 # number of overall hits 849system.cpu.icache.overall_hits::total 88370544 # number of overall hits 850system.cpu.icache.ReadReq_misses::cpu.inst 721792 # number of ReadReq misses 851system.cpu.icache.ReadReq_misses::total 721792 # number of ReadReq misses 852system.cpu.icache.demand_misses::cpu.inst 721792 # number of demand (read+write) misses 853system.cpu.icache.demand_misses::total 721792 # number of demand (read+write) misses 854system.cpu.icache.overall_misses::cpu.inst 721792 # number of overall misses 855system.cpu.icache.overall_misses::total 721792 # number of overall misses 856system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973239447 # number of ReadReq miss cycles 857system.cpu.icache.ReadReq_miss_latency::total 5973239447 # number of ReadReq miss cycles 858system.cpu.icache.demand_miss_latency::cpu.inst 5973239447 # number of demand (read+write) miss cycles 859system.cpu.icache.demand_miss_latency::total 5973239447 # number of demand (read+write) miss cycles 860system.cpu.icache.overall_miss_latency::cpu.inst 5973239447 # number of overall miss cycles 861system.cpu.icache.overall_miss_latency::total 5973239447 # number of overall miss cycles 862system.cpu.icache.ReadReq_accesses::cpu.inst 89092336 # number of ReadReq accesses(hits+misses) 863system.cpu.icache.ReadReq_accesses::total 89092336 # number of ReadReq accesses(hits+misses) 864system.cpu.icache.demand_accesses::cpu.inst 89092336 # number of demand (read+write) accesses 865system.cpu.icache.demand_accesses::total 89092336 # number of demand (read+write) accesses 866system.cpu.icache.overall_accesses::cpu.inst 89092336 # number of overall (read+write) accesses 867system.cpu.icache.overall_accesses::total 89092336 # number of overall (read+write) accesses |
| 868system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008102 # miss rate for ReadReq accesses 869system.cpu.icache.ReadReq_miss_rate::total 0.008102 # miss rate for ReadReq accesses 870system.cpu.icache.demand_miss_rate::cpu.inst 0.008102 # miss rate for demand accesses 871system.cpu.icache.demand_miss_rate::total 0.008102 # miss rate for demand accesses 872system.cpu.icache.overall_miss_rate::cpu.inst 0.008102 # miss rate for overall accesses 873system.cpu.icache.overall_miss_rate::total 0.008102 # miss rate for overall accesses | 868system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008102 # miss rate for ReadReq accesses 869system.cpu.icache.ReadReq_miss_rate::total 0.008102 # miss rate for ReadReq accesses 870system.cpu.icache.demand_miss_rate::cpu.inst 0.008102 # miss rate for demand accesses 871system.cpu.icache.demand_miss_rate::total 0.008102 # miss rate for demand accesses 872system.cpu.icache.overall_miss_rate::cpu.inst 0.008102 # miss rate for overall accesses 873system.cpu.icache.overall_miss_rate::total 0.008102 # miss rate for overall accesses |
| 874system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.571765 # average ReadReq miss latency 875system.cpu.icache.ReadReq_avg_miss_latency::total 8275.571765 # average ReadReq miss latency 876system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency 877system.cpu.icache.demand_avg_miss_latency::total 8275.571765 # average overall miss latency 878system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency 879system.cpu.icache.overall_avg_miss_latency::total 8275.571765 # average overall miss latency 880system.cpu.icache.blocked_cycles::no_mshrs 62134 # number of cycles access was blocked | 874system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.568927 # average ReadReq miss latency 875system.cpu.icache.ReadReq_avg_miss_latency::total 8275.568927 # average ReadReq miss latency 876system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency 877system.cpu.icache.demand_avg_miss_latency::total 8275.568927 # average overall miss latency 878system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency 879system.cpu.icache.overall_avg_miss_latency::total 8275.568927 # average overall miss latency 880system.cpu.icache.blocked_cycles::no_mshrs 62302 # number of cycles access was blocked |
| 881system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked | 881system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked |
| 882system.cpu.icache.blocked::no_mshrs 2178 # number of cycles access was blocked | 882system.cpu.icache.blocked::no_mshrs 2158 # number of cycles access was blocked |
| 883system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked | 883system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked |
| 884system.cpu.icache.avg_blocked_cycles::no_mshrs 28.528007 # average number of cycles each access was blocked | 884system.cpu.icache.avg_blocked_cycles::no_mshrs 28.870250 # average number of cycles each access was blocked |
| 885system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked 886system.cpu.icache.fast_writes 0 # number of fast writes performed 887system.cpu.icache.cache_copies 0 # number of cache copies performed | 885system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked 886system.cpu.icache.fast_writes 0 # number of fast writes performed 887system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 888system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5643 # number of ReadReq MSHR hits 889system.cpu.icache.ReadReq_mshr_hits::total 5643 # number of ReadReq MSHR hits 890system.cpu.icache.demand_mshr_hits::cpu.inst 5643 # number of demand (read+write) MSHR hits 891system.cpu.icache.demand_mshr_hits::total 5643 # number of demand (read+write) MSHR hits 892system.cpu.icache.overall_mshr_hits::cpu.inst 5643 # number of overall MSHR hits 893system.cpu.icache.overall_mshr_hits::total 5643 # number of overall MSHR hits 894system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716147 # number of ReadReq MSHR misses 895system.cpu.icache.ReadReq_mshr_misses::total 716147 # number of ReadReq MSHR misses 896system.cpu.icache.demand_mshr_misses::cpu.inst 716147 # number of demand (read+write) MSHR misses 897system.cpu.icache.demand_mshr_misses::total 716147 # number of demand (read+write) MSHR misses 898system.cpu.icache.overall_mshr_misses::cpu.inst 716147 # number of overall MSHR misses 899system.cpu.icache.overall_mshr_misses::total 716147 # number of overall MSHR misses 900system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5549831453 # number of ReadReq MSHR miss cycles 901system.cpu.icache.ReadReq_mshr_miss_latency::total 5549831453 # number of ReadReq MSHR miss cycles 902system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5549831453 # number of demand (read+write) MSHR miss cycles 903system.cpu.icache.demand_mshr_miss_latency::total 5549831453 # number of demand (read+write) MSHR miss cycles 904system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5549831453 # number of overall MSHR miss cycles 905system.cpu.icache.overall_mshr_miss_latency::total 5549831453 # number of overall MSHR miss cycles | 888system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5644 # number of ReadReq MSHR hits 889system.cpu.icache.ReadReq_mshr_hits::total 5644 # number of ReadReq MSHR hits 890system.cpu.icache.demand_mshr_hits::cpu.inst 5644 # number of demand (read+write) MSHR hits 891system.cpu.icache.demand_mshr_hits::total 5644 # number of demand (read+write) MSHR hits 892system.cpu.icache.overall_mshr_hits::cpu.inst 5644 # number of overall MSHR hits 893system.cpu.icache.overall_mshr_hits::total 5644 # number of overall MSHR hits 894system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716148 # number of ReadReq MSHR misses 895system.cpu.icache.ReadReq_mshr_misses::total 716148 # number of ReadReq MSHR misses 896system.cpu.icache.demand_mshr_misses::cpu.inst 716148 # number of demand (read+write) MSHR misses 897system.cpu.icache.demand_mshr_misses::total 716148 # number of demand (read+write) MSHR misses 898system.cpu.icache.overall_mshr_misses::cpu.inst 716148 # number of overall MSHR misses 899system.cpu.icache.overall_mshr_misses::total 716148 # number of overall MSHR misses 900system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5551358955 # number of ReadReq MSHR miss cycles 901system.cpu.icache.ReadReq_mshr_miss_latency::total 5551358955 # number of ReadReq MSHR miss cycles 902system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5551358955 # number of demand (read+write) MSHR miss cycles 903system.cpu.icache.demand_mshr_miss_latency::total 5551358955 # number of demand (read+write) MSHR miss cycles 904system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5551358955 # number of overall MSHR miss cycles 905system.cpu.icache.overall_mshr_miss_latency::total 5551358955 # number of overall MSHR miss cycles |
| 906system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for ReadReq accesses 907system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008038 # mshr miss rate for ReadReq accesses 908system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for demand accesses 909system.cpu.icache.demand_mshr_miss_rate::total 0.008038 # mshr miss rate for demand accesses 910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for overall accesses 911system.cpu.icache.overall_mshr_miss_rate::total 0.008038 # mshr miss rate for overall accesses | 906system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for ReadReq accesses 907system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008038 # mshr miss rate for ReadReq accesses 908system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for demand accesses 909system.cpu.icache.demand_mshr_miss_rate::total 0.008038 # mshr miss rate for demand accesses 910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for overall accesses 911system.cpu.icache.overall_mshr_miss_rate::total 0.008038 # mshr miss rate for overall accesses |
| 912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7749.570204 # average ReadReq mshr miss latency 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7749.570204 # average ReadReq mshr miss latency 914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency 916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency | 912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7751.692325 # average ReadReq mshr miss latency 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7751.692325 # average ReadReq mshr miss latency 914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7751.692325 # average overall mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::total 7751.692325 # average overall mshr miss latency 916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7751.692325 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::total 7751.692325 # average overall mshr miss latency |
| 918system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 918system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 919system.cpu.l2cache.prefetcher.num_hwpf_issued 404667 # number of hwpf issued 920system.cpu.l2cache.prefetcher.pfIdentified 404963 # number of prefetch candidates identified 921system.cpu.l2cache.prefetcher.pfBufferHit 238 # number of redundant prefetches already in prefetch queue | 919system.cpu.l2cache.prefetcher.num_hwpf_issued 405270 # number of hwpf issued 920system.cpu.l2cache.prefetcher.pfIdentified 405390 # number of prefetch candidates identified 921system.cpu.l2cache.prefetcher.pfBufferHit 107 # number of redundant prefetches already in prefetch queue |
| 922system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 923system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 922system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 923system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 924system.cpu.l2cache.prefetcher.pfSpanPage 28037 # number of prefetches not generated due to page crossing | 924system.cpu.l2cache.prefetcher.pfSpanPage 28146 # number of prefetches not generated due to page crossing |
| 925system.cpu.l2cache.tags.replacements 0 # number of replacements | 925system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 926system.cpu.l2cache.tags.tagsinuse 5979.453401 # Cycle average of tags in use 927system.cpu.l2cache.tags.total_refs 3840411 # Total number of references to valid blocks. 928system.cpu.l2cache.tags.sampled_refs 7285 # Sample count of references to valid blocks. 929system.cpu.l2cache.tags.avg_refs 527.166918 # Average number of references to valid blocks. | 926system.cpu.l2cache.tags.tagsinuse 5987.985640 # Cycle average of tags in use 927system.cpu.l2cache.tags.total_refs 3840429 # Total number of references to valid blocks. 928system.cpu.l2cache.tags.sampled_refs 7297 # Sample count of references to valid blocks. 929system.cpu.l2cache.tags.avg_refs 526.302453 # Average number of references to valid blocks. |
| 930system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 930system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 931system.cpu.l2cache.tags.occ_blocks::writebacks 2575.206017 # Average occupied blocks per requestor 932system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.661219 # Average occupied blocks per requestor 933system.cpu.l2cache.tags.occ_blocks::cpu.data 617.502494 # Average occupied blocks per requestor 934system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 106.083671 # Average occupied blocks per requestor 935system.cpu.l2cache.tags.occ_percent::writebacks 0.157178 # Average percentage of cache occupancy 936system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163615 # Average percentage of cache occupancy 937system.cpu.l2cache.tags.occ_percent::cpu.data 0.037689 # Average percentage of cache occupancy 938system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006475 # Average percentage of cache occupancy 939system.cpu.l2cache.tags.occ_percent::total 0.364957 # Average percentage of cache occupancy 940system.cpu.l2cache.tags.occ_task_id_blocks::1022 494 # Occupied blocks per task id | 931system.cpu.l2cache.tags.occ_blocks::writebacks 2575.177185 # Average occupied blocks per requestor 932system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.633084 # Average occupied blocks per requestor 933system.cpu.l2cache.tags.occ_blocks::cpu.data 617.470420 # Average occupied blocks per requestor 934system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 114.704950 # Average occupied blocks per requestor 935system.cpu.l2cache.tags.occ_percent::writebacks 0.157176 # Average percentage of cache occupancy 936system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163613 # Average percentage of cache occupancy 937system.cpu.l2cache.tags.occ_percent::cpu.data 0.037687 # Average percentage of cache occupancy 938system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007001 # Average percentage of cache occupancy 939system.cpu.l2cache.tags.occ_percent::total 0.365478 # Average percentage of cache occupancy 940system.cpu.l2cache.tags.occ_task_id_blocks::1022 506 # Occupied blocks per task id |
| 941system.cpu.l2cache.tags.occ_task_id_blocks::1024 6791 # Occupied blocks per task id 942system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id 943system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id 944system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id | 941system.cpu.l2cache.tags.occ_task_id_blocks::1024 6791 # Occupied blocks per task id 942system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id 943system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id 944system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id |
| 945system.cpu.l2cache.tags.age_task_id_blocks_1022::4 112 # Occupied blocks per task id | 945system.cpu.l2cache.tags.age_task_id_blocks_1022::4 124 # Occupied blocks per task id |
| 946system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 947system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id | 946system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 947system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id |
| 948system.cpu.l2cache.tags.age_task_id_blocks_1024::2 772 # Occupied blocks per task id 949system.cpu.l2cache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id | 948system.cpu.l2cache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id 949system.cpu.l2cache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id |
| 950system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5749 # Occupied blocks per task id | 950system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5749 # Occupied blocks per task id |
| 951system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030151 # Percentage of cache occupancy per task id | 951system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030884 # Percentage of cache occupancy per task id |
| 952system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414490 # Percentage of cache occupancy per task id | 952system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414490 # Percentage of cache occupancy per task id |
| 953system.cpu.l2cache.tags.tag_accesses 68225284 # Number of tag accesses 954system.cpu.l2cache.tags.data_accesses 68225284 # Number of data accesses | 953system.cpu.l2cache.tags.tag_accesses 68225328 # Number of tag accesses 954system.cpu.l2cache.tags.data_accesses 68225328 # Number of data accesses |
| 955system.cpu.l2cache.Writeback_hits::writebacks 966339 # number of Writeback hits 956system.cpu.l2cache.Writeback_hits::total 966339 # number of Writeback hits 957system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 958system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits | 955system.cpu.l2cache.Writeback_hits::writebacks 966339 # number of Writeback hits 956system.cpu.l2cache.Writeback_hits::total 966339 # number of Writeback hits 957system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 958system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits |
| 959system.cpu.l2cache.ReadExReq_hits::cpu.data 219856 # number of ReadExReq hits 960system.cpu.l2cache.ReadExReq_hits::total 219856 # number of ReadExReq hits 961system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 712305 # number of ReadCleanReq hits 962system.cpu.l2cache.ReadCleanReq_hits::total 712305 # number of ReadCleanReq hits 963system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1312647 # number of ReadSharedReq hits 964system.cpu.l2cache.ReadSharedReq_hits::total 1312647 # number of ReadSharedReq hits 965system.cpu.l2cache.demand_hits::cpu.inst 712305 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.data 1532503 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::total 2244808 # number of demand (read+write) hits 968system.cpu.l2cache.overall_hits::cpu.inst 712305 # number of overall hits 969system.cpu.l2cache.overall_hits::cpu.data 1532503 # number of overall hits 970system.cpu.l2cache.overall_hits::total 2244808 # number of overall hits | 959system.cpu.l2cache.ReadExReq_hits::cpu.data 219874 # number of ReadExReq hits 960system.cpu.l2cache.ReadExReq_hits::total 219874 # number of ReadExReq hits 961system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 712306 # number of ReadCleanReq hits 962system.cpu.l2cache.ReadCleanReq_hits::total 712306 # number of ReadCleanReq hits 963system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1312645 # number of ReadSharedReq hits 964system.cpu.l2cache.ReadSharedReq_hits::total 1312645 # number of ReadSharedReq hits 965system.cpu.l2cache.demand_hits::cpu.inst 712306 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.data 1532519 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::total 2244825 # number of demand (read+write) hits 968system.cpu.l2cache.overall_hits::cpu.inst 712306 # number of overall hits 969system.cpu.l2cache.overall_hits::cpu.data 1532519 # number of overall hits 970system.cpu.l2cache.overall_hits::total 2244825 # number of overall hits |
| 971system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 972system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses | 971system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 972system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses |
| 973system.cpu.l2cache.ReadExReq_misses::cpu.data 797 # number of ReadExReq misses 974system.cpu.l2cache.ReadExReq_misses::total 797 # number of ReadExReq misses | 973system.cpu.l2cache.ReadExReq_misses::cpu.data 779 # number of ReadExReq misses 974system.cpu.l2cache.ReadExReq_misses::total 779 # number of ReadExReq misses |
| 975system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2936 # number of ReadCleanReq misses 976system.cpu.l2cache.ReadCleanReq_misses::total 2936 # number of ReadCleanReq misses | 975system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2936 # number of ReadCleanReq misses 976system.cpu.l2cache.ReadCleanReq_misses::total 2936 # number of ReadCleanReq misses |
| 977system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1057 # number of ReadSharedReq misses 978system.cpu.l2cache.ReadSharedReq_misses::total 1057 # number of ReadSharedReq misses | 977system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1059 # number of ReadSharedReq misses 978system.cpu.l2cache.ReadSharedReq_misses::total 1059 # number of ReadSharedReq misses |
| 979system.cpu.l2cache.demand_misses::cpu.inst 2936 # number of demand (read+write) misses | 979system.cpu.l2cache.demand_misses::cpu.inst 2936 # number of demand (read+write) misses |
| 980system.cpu.l2cache.demand_misses::cpu.data 1854 # number of demand (read+write) misses 981system.cpu.l2cache.demand_misses::total 4790 # number of demand (read+write) misses | 980system.cpu.l2cache.demand_misses::cpu.data 1838 # number of demand (read+write) misses 981system.cpu.l2cache.demand_misses::total 4774 # number of demand (read+write) misses |
| 982system.cpu.l2cache.overall_misses::cpu.inst 2936 # number of overall misses | 982system.cpu.l2cache.overall_misses::cpu.inst 2936 # number of overall misses |
| 983system.cpu.l2cache.overall_misses::cpu.data 1854 # number of overall misses 984system.cpu.l2cache.overall_misses::total 4790 # number of overall misses | 983system.cpu.l2cache.overall_misses::cpu.data 1838 # number of overall misses 984system.cpu.l2cache.overall_misses::total 4774 # number of overall misses |
| 985system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles 986system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles | 985system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles 986system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles |
| 987system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57082000 # number of ReadExReq miss cycles 988system.cpu.l2cache.ReadExReq_miss_latency::total 57082000 # number of ReadExReq miss cycles 989system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 199290000 # number of ReadCleanReq miss cycles 990system.cpu.l2cache.ReadCleanReq_miss_latency::total 199290000 # number of ReadCleanReq miss cycles 991system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 76381000 # number of ReadSharedReq miss cycles 992system.cpu.l2cache.ReadSharedReq_miss_latency::total 76381000 # number of ReadSharedReq miss cycles 993system.cpu.l2cache.demand_miss_latency::cpu.inst 199290000 # number of demand (read+write) miss cycles 994system.cpu.l2cache.demand_miss_latency::cpu.data 133463000 # number of demand (read+write) miss cycles 995system.cpu.l2cache.demand_miss_latency::total 332753000 # number of demand (read+write) miss cycles 996system.cpu.l2cache.overall_miss_latency::cpu.inst 199290000 # number of overall miss cycles 997system.cpu.l2cache.overall_miss_latency::cpu.data 133463000 # number of overall miss cycles 998system.cpu.l2cache.overall_miss_latency::total 332753000 # number of overall miss cycles | 987system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56035500 # number of ReadExReq miss cycles 988system.cpu.l2cache.ReadExReq_miss_latency::total 56035500 # number of ReadExReq miss cycles 989system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 200811500 # number of ReadCleanReq miss cycles 990system.cpu.l2cache.ReadCleanReq_miss_latency::total 200811500 # number of ReadCleanReq miss cycles 991system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 77311000 # number of ReadSharedReq miss cycles 992system.cpu.l2cache.ReadSharedReq_miss_latency::total 77311000 # number of ReadSharedReq miss cycles 993system.cpu.l2cache.demand_miss_latency::cpu.inst 200811500 # number of demand (read+write) miss cycles 994system.cpu.l2cache.demand_miss_latency::cpu.data 133346500 # number of demand (read+write) miss cycles 995system.cpu.l2cache.demand_miss_latency::total 334158000 # number of demand (read+write) miss cycles 996system.cpu.l2cache.overall_miss_latency::cpu.inst 200811500 # number of overall miss cycles 997system.cpu.l2cache.overall_miss_latency::cpu.data 133346500 # number of overall miss cycles 998system.cpu.l2cache.overall_miss_latency::total 334158000 # number of overall miss cycles |
| 999system.cpu.l2cache.Writeback_accesses::writebacks 966339 # number of Writeback accesses(hits+misses) 1000system.cpu.l2cache.Writeback_accesses::total 966339 # number of Writeback accesses(hits+misses) 1001system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 1002system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 1003system.cpu.l2cache.ReadExReq_accesses::cpu.data 220653 # number of ReadExReq accesses(hits+misses) 1004system.cpu.l2cache.ReadExReq_accesses::total 220653 # number of ReadExReq accesses(hits+misses) | 999system.cpu.l2cache.Writeback_accesses::writebacks 966339 # number of Writeback accesses(hits+misses) 1000system.cpu.l2cache.Writeback_accesses::total 966339 # number of Writeback accesses(hits+misses) 1001system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 1002system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 1003system.cpu.l2cache.ReadExReq_accesses::cpu.data 220653 # number of ReadExReq accesses(hits+misses) 1004system.cpu.l2cache.ReadExReq_accesses::total 220653 # number of ReadExReq accesses(hits+misses) |
| 1005system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 715241 # number of ReadCleanReq accesses(hits+misses) 1006system.cpu.l2cache.ReadCleanReq_accesses::total 715241 # number of ReadCleanReq accesses(hits+misses) | 1005system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 715242 # number of ReadCleanReq accesses(hits+misses) 1006system.cpu.l2cache.ReadCleanReq_accesses::total 715242 # number of ReadCleanReq accesses(hits+misses) |
| 1007system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1313704 # number of ReadSharedReq accesses(hits+misses) 1008system.cpu.l2cache.ReadSharedReq_accesses::total 1313704 # number of ReadSharedReq accesses(hits+misses) | 1007system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1313704 # number of ReadSharedReq accesses(hits+misses) 1008system.cpu.l2cache.ReadSharedReq_accesses::total 1313704 # number of ReadSharedReq accesses(hits+misses) |
| 1009system.cpu.l2cache.demand_accesses::cpu.inst 715241 # number of demand (read+write) accesses | 1009system.cpu.l2cache.demand_accesses::cpu.inst 715242 # number of demand (read+write) accesses |
| 1010system.cpu.l2cache.demand_accesses::cpu.data 1534357 # number of demand (read+write) accesses | 1010system.cpu.l2cache.demand_accesses::cpu.data 1534357 # number of demand (read+write) accesses |
| 1011system.cpu.l2cache.demand_accesses::total 2249598 # number of demand (read+write) accesses 1012system.cpu.l2cache.overall_accesses::cpu.inst 715241 # number of overall (read+write) accesses | 1011system.cpu.l2cache.demand_accesses::total 2249599 # number of demand (read+write) accesses 1012system.cpu.l2cache.overall_accesses::cpu.inst 715242 # number of overall (read+write) accesses |
| 1013system.cpu.l2cache.overall_accesses::cpu.data 1534357 # number of overall (read+write) accesses | 1013system.cpu.l2cache.overall_accesses::cpu.data 1534357 # number of overall (read+write) accesses |
| 1014system.cpu.l2cache.overall_accesses::total 2249598 # number of overall (read+write) accesses | 1014system.cpu.l2cache.overall_accesses::total 2249599 # number of overall (read+write) accesses |
| 1015system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses 1016system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses | 1015system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses 1016system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses |
| 1017system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003612 # miss rate for ReadExReq accesses 1018system.cpu.l2cache.ReadExReq_miss_rate::total 0.003612 # miss rate for ReadExReq accesses | 1017system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003530 # miss rate for ReadExReq accesses 1018system.cpu.l2cache.ReadExReq_miss_rate::total 0.003530 # miss rate for ReadExReq accesses |
| 1019system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004105 # miss rate for ReadCleanReq accesses 1020system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004105 # miss rate for ReadCleanReq accesses | 1019system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004105 # miss rate for ReadCleanReq accesses 1020system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004105 # miss rate for ReadCleanReq accesses |
| 1021system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000805 # miss rate for ReadSharedReq accesses 1022system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000805 # miss rate for ReadSharedReq accesses | 1021system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000806 # miss rate for ReadSharedReq accesses 1022system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000806 # miss rate for ReadSharedReq accesses |
| 1023system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004105 # miss rate for demand accesses | 1023system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004105 # miss rate for demand accesses |
| 1024system.cpu.l2cache.demand_miss_rate::cpu.data 0.001208 # miss rate for demand accesses 1025system.cpu.l2cache.demand_miss_rate::total 0.002129 # miss rate for demand accesses | 1024system.cpu.l2cache.demand_miss_rate::cpu.data 0.001198 # miss rate for demand accesses 1025system.cpu.l2cache.demand_miss_rate::total 0.002122 # miss rate for demand accesses |
| 1026system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004105 # miss rate for overall accesses | 1026system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004105 # miss rate for overall accesses |
| 1027system.cpu.l2cache.overall_miss_rate::cpu.data 0.001208 # miss rate for overall accesses 1028system.cpu.l2cache.overall_miss_rate::total 0.002129 # miss rate for overall accesses | 1027system.cpu.l2cache.overall_miss_rate::cpu.data 0.001198 # miss rate for overall accesses 1028system.cpu.l2cache.overall_miss_rate::total 0.002122 # miss rate for overall accesses |
| 1029system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23000 # average UpgradeReq miss latency 1030system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23000 # average UpgradeReq miss latency | 1029system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23000 # average UpgradeReq miss latency 1030system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23000 # average UpgradeReq miss latency |
| 1031system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71621.079046 # average ReadExReq miss latency 1032system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71621.079046 # average ReadExReq miss latency 1033system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67878.065395 # average ReadCleanReq miss latency 1034system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67878.065395 # average ReadCleanReq miss latency 1035system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72262.062441 # average ReadSharedReq miss latency 1036system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72262.062441 # average ReadSharedReq miss latency 1037system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67878.065395 # average overall miss latency 1038system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71986.515642 # average overall miss latency 1039system.cpu.l2cache.demand_avg_miss_latency::total 69468.267223 # average overall miss latency 1040system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67878.065395 # average overall miss latency 1041system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71986.515642 # average overall miss latency 1042system.cpu.l2cache.overall_avg_miss_latency::total 69468.267223 # average overall miss latency | 1031system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71932.605905 # average ReadExReq miss latency 1032system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71932.605905 # average ReadExReq miss latency 1033system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68396.287466 # average ReadCleanReq miss latency 1034system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68396.287466 # average ReadCleanReq miss latency 1035system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73003.777148 # average ReadSharedReq miss latency 1036system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73003.777148 # average ReadSharedReq miss latency 1037system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68396.287466 # average overall miss latency 1038system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72549.782372 # average overall miss latency 1039system.cpu.l2cache.demand_avg_miss_latency::total 69995.391705 # average overall miss latency 1040system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68396.287466 # average overall miss latency 1041system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72549.782372 # average overall miss latency 1042system.cpu.l2cache.overall_avg_miss_latency::total 69995.391705 # average overall miss latency |
| 1043system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1044system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1045system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1046system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1047system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1048system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1049system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1050system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1043system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1044system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1045system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1046system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1047system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1048system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1049system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1050system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1051system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 57 # number of ReadExReq MSHR hits 1052system.cpu.l2cache.ReadExReq_mshr_hits::total 57 # number of ReadExReq MSHR hits | 1051system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 48 # number of ReadExReq MSHR hits 1052system.cpu.l2cache.ReadExReq_mshr_hits::total 48 # number of ReadExReq MSHR hits |
| 1053system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits 1054system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 1055system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 33 # number of ReadSharedReq MSHR hits 1056system.cpu.l2cache.ReadSharedReq_mshr_hits::total 33 # number of ReadSharedReq MSHR hits 1057system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits | 1053system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits 1054system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 1055system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 33 # number of ReadSharedReq MSHR hits 1056system.cpu.l2cache.ReadSharedReq_mshr_hits::total 33 # number of ReadSharedReq MSHR hits 1057system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits |
| 1058system.cpu.l2cache.demand_mshr_hits::cpu.data 90 # number of demand (read+write) MSHR hits 1059system.cpu.l2cache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits | 1058system.cpu.l2cache.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits 1059system.cpu.l2cache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits |
| 1060system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits | 1060system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits |
| 1061system.cpu.l2cache.overall_mshr_hits::cpu.data 90 # number of overall MSHR hits 1062system.cpu.l2cache.overall_mshr_hits::total 103 # number of overall MSHR hits 1063system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30350 # number of HardPFReq MSHR misses 1064system.cpu.l2cache.HardPFReq_mshr_misses::total 30350 # number of HardPFReq MSHR misses | 1061system.cpu.l2cache.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits 1062system.cpu.l2cache.overall_mshr_hits::total 94 # number of overall MSHR hits 1063system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30427 # number of HardPFReq MSHR misses 1064system.cpu.l2cache.HardPFReq_mshr_misses::total 30427 # number of HardPFReq MSHR misses |
| 1065system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 1066system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses | 1065system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 1066system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses |
| 1067system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 740 # number of ReadExReq MSHR misses 1068system.cpu.l2cache.ReadExReq_mshr_misses::total 740 # number of ReadExReq MSHR misses | 1067system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 731 # number of ReadExReq MSHR misses 1068system.cpu.l2cache.ReadExReq_mshr_misses::total 731 # number of ReadExReq MSHR misses |
| 1069system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2923 # number of ReadCleanReq MSHR misses 1070system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2923 # number of ReadCleanReq MSHR misses | 1069system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2923 # number of ReadCleanReq MSHR misses 1070system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2923 # number of ReadCleanReq MSHR misses |
| 1071system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1024 # number of ReadSharedReq MSHR misses 1072system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1024 # number of ReadSharedReq MSHR misses | 1071system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1026 # number of ReadSharedReq MSHR misses 1072system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1026 # number of ReadSharedReq MSHR misses |
| 1073system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses | 1073system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses |
| 1074system.cpu.l2cache.demand_mshr_misses::cpu.data 1764 # number of demand (read+write) MSHR misses 1075system.cpu.l2cache.demand_mshr_misses::total 4687 # number of demand (read+write) MSHR misses | 1074system.cpu.l2cache.demand_mshr_misses::cpu.data 1757 # number of demand (read+write) MSHR misses 1075system.cpu.l2cache.demand_mshr_misses::total 4680 # number of demand (read+write) MSHR misses |
| 1076system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses | 1076system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses |
| 1077system.cpu.l2cache.overall_mshr_misses::cpu.data 1764 # number of overall MSHR misses 1078system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30350 # number of overall MSHR misses 1079system.cpu.l2cache.overall_mshr_misses::total 35037 # number of overall MSHR misses 1080system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of HardPFReq MSHR miss cycles 1081system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 188993302 # number of HardPFReq MSHR miss cycles | 1077system.cpu.l2cache.overall_mshr_misses::cpu.data 1757 # number of overall MSHR misses 1078system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30427 # number of overall MSHR misses 1079system.cpu.l2cache.overall_mshr_misses::total 35107 # number of overall MSHR misses 1080system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 180653766 # number of HardPFReq MSHR miss cycles 1081system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 180653766 # number of HardPFReq MSHR miss cycles |
| 1082system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 17000 # number of UpgradeReq MSHR miss cycles 1083system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 17000 # number of UpgradeReq MSHR miss cycles | 1082system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 17000 # number of UpgradeReq MSHR miss cycles 1083system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 17000 # number of UpgradeReq MSHR miss cycles |
| 1084system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50613500 # number of ReadExReq MSHR miss cycles 1085system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50613500 # number of ReadExReq MSHR miss cycles 1086system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181139000 # number of ReadCleanReq MSHR miss cycles 1087system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181139000 # number of ReadCleanReq MSHR miss cycles 1088system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 68370000 # number of ReadSharedReq MSHR miss cycles 1089system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 68370000 # number of ReadSharedReq MSHR miss cycles 1090system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181139000 # number of demand (read+write) MSHR miss cycles 1091system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118983500 # number of demand (read+write) MSHR miss cycles 1092system.cpu.l2cache.demand_mshr_miss_latency::total 300122500 # number of demand (read+write) MSHR miss cycles 1093system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181139000 # number of overall MSHR miss cycles 1094system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118983500 # number of overall MSHR miss cycles 1095system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of overall MSHR miss cycles 1096system.cpu.l2cache.overall_mshr_miss_latency::total 489115802 # number of overall MSHR miss cycles | 1084system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49936000 # number of ReadExReq MSHR miss cycles 1085system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49936000 # number of ReadExReq MSHR miss cycles 1086system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182660500 # number of ReadCleanReq MSHR miss cycles 1087system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182660500 # number of ReadCleanReq MSHR miss cycles 1088system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69288000 # number of ReadSharedReq MSHR miss cycles 1089system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69288000 # number of ReadSharedReq MSHR miss cycles 1090system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182660500 # number of demand (read+write) MSHR miss cycles 1091system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119224000 # number of demand (read+write) MSHR miss cycles 1092system.cpu.l2cache.demand_mshr_miss_latency::total 301884500 # number of demand (read+write) MSHR miss cycles 1093system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182660500 # number of overall MSHR miss cycles 1094system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119224000 # number of overall MSHR miss cycles 1095system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 180653766 # number of overall MSHR miss cycles 1096system.cpu.l2cache.overall_mshr_miss_latency::total 482538266 # number of overall MSHR miss cycles |
| 1097system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1098system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1099system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 1100system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses | 1097system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1098system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1099system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 1100system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses |
| 1101system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003354 # mshr miss rate for ReadExReq accesses 1102system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003354 # mshr miss rate for ReadExReq accesses | 1101system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003313 # mshr miss rate for ReadExReq accesses 1102system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003313 # mshr miss rate for ReadExReq accesses |
| 1103system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for ReadCleanReq accesses 1104system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004087 # mshr miss rate for ReadCleanReq accesses | 1103system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for ReadCleanReq accesses 1104system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004087 # mshr miss rate for ReadCleanReq accesses |
| 1105system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000779 # mshr miss rate for ReadSharedReq accesses 1106system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadSharedReq accesses | 1105system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadSharedReq accesses 1106system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadSharedReq accesses |
| 1107system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for demand accesses | 1107system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for demand accesses |
| 1108system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for demand accesses 1109system.cpu.l2cache.demand_mshr_miss_rate::total 0.002083 # mshr miss rate for demand accesses | 1108system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001145 # mshr miss rate for demand accesses 1109system.cpu.l2cache.demand_mshr_miss_rate::total 0.002080 # mshr miss rate for demand accesses |
| 1110system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for overall accesses | 1110system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for overall accesses |
| 1111system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for overall accesses | 1111system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001145 # mshr miss rate for overall accesses |
| 1112system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1112system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1113system.cpu.l2cache.overall_mshr_miss_rate::total 0.015575 # mshr miss rate for overall accesses 1114system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average HardPFReq mshr miss latency 1115system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6227.126919 # average HardPFReq mshr miss latency | 1113system.cpu.l2cache.overall_mshr_miss_rate::total 0.015606 # mshr miss rate for overall accesses 1114system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average HardPFReq mshr miss latency 1115system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5937.284846 # average HardPFReq mshr miss latency |
| 1116system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17000 # average UpgradeReq mshr miss latency 1117system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17000 # average UpgradeReq mshr miss latency | 1116system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17000 # average UpgradeReq mshr miss latency 1117system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17000 # average UpgradeReq mshr miss latency |
| 1118system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68396.621622 # average ReadExReq mshr miss latency 1119system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68396.621622 # average ReadExReq mshr miss latency 1120system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61970.236059 # average ReadCleanReq mshr miss latency 1121system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61970.236059 # average ReadCleanReq mshr miss latency 1122system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66767.578125 # average ReadSharedReq mshr miss latency 1123system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66767.578125 # average ReadSharedReq mshr miss latency 1124system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency 1125system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency 1126system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64032.963516 # average overall mshr miss latency 1127system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency 1128system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency 1129system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average overall mshr miss latency 1130system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13959.979507 # average overall mshr miss latency | 1118system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68311.901505 # average ReadExReq mshr miss latency 1119system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68311.901505 # average ReadExReq mshr miss latency 1120system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62490.762915 # average ReadCleanReq mshr miss latency 1121system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62490.762915 # average ReadCleanReq mshr miss latency 1122system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67532.163743 # average ReadSharedReq mshr miss latency 1123system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67532.163743 # average ReadSharedReq mshr miss latency 1124system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency 1125system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency 1126system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64505.235043 # average overall mshr miss latency 1127system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency 1128system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency 1129system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average overall mshr miss latency 1130system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13744.787820 # average overall mshr miss latency |
| 1131system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1131system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1132system.cpu.toL2Bus.trans_dist::ReadResp 2029851 # Transaction distribution | 1132system.cpu.toL2Bus.trans_dist::ReadResp 2029852 # Transaction distribution |
| 1133system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution | 1133system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution |
| 1134system.cpu.toL2Bus.trans_dist::CleanEvict 1033895 # Transaction distribution 1135system.cpu.toL2Bus.trans_dist::HardPFReq 31761 # Transaction distribution | 1134system.cpu.toL2Bus.trans_dist::CleanEvict 1033896 # Transaction distribution 1135system.cpu.toL2Bus.trans_dist::HardPFReq 31809 # Transaction distribution |
| 1136system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 1137system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 1138system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution 1139system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution | 1136system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 1137system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 1138system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution 1139system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution |
| 1140system.cpu.toL2Bus.trans_dist::ReadCleanReq 716147 # Transaction distribution | 1140system.cpu.toL2Bus.trans_dist::ReadCleanReq 716148 # Transaction distribution |
| 1141system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313704 # Transaction distribution | 1141system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313704 # Transaction distribution |
| 1142system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122577 # Packet count per connected master and slave (bytes) | 1142system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122580 # Packet count per connected master and slave (bytes) |
| 1143system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377763 # Packet count per connected master and slave (bytes) | 1143system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377763 # Packet count per connected master and slave (bytes) |
| 1144system.cpu.toL2Bus.pkt_count::total 6500340 # Packet count per connected master and slave (bytes) 1145system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775424 # Cumulative packet size per connected master and slave (bytes) | 1144system.cpu.toL2Bus.pkt_count::total 6500343 # Packet count per connected master and slave (bytes) 1145system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775488 # Cumulative packet size per connected master and slave (bytes) |
| 1146system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044544 # Cumulative packet size per connected master and slave (bytes) | 1146system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044544 # Cumulative packet size per connected master and slave (bytes) |
| 1147system.cpu.toL2Bus.pkt_size::total 205819968 # Cumulative packet size per connected master and slave (bytes) 1148system.cpu.toL2Bus.snoops 32667 # Total snoops (count) 1149system.cpu.toL2Bus.snoop_fanout::samples 4531746 # Request fanout histogram 1150system.cpu.toL2Bus.snoop_fanout::mean 1.007009 # Request fanout histogram 1151system.cpu.toL2Bus.snoop_fanout::stdev 0.083423 # Request fanout histogram | 1147system.cpu.toL2Bus.pkt_size::total 205820032 # Cumulative packet size per connected master and slave (bytes) 1148system.cpu.toL2Bus.snoops 32715 # Total snoops (count) 1149system.cpu.toL2Bus.snoop_fanout::samples 4531796 # Request fanout histogram 1150system.cpu.toL2Bus.snoop_fanout::mean 1.007019 # Request fanout histogram 1151system.cpu.toL2Bus.snoop_fanout::stdev 0.083485 # Request fanout histogram |
| 1152system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1153system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1152system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1153system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1154system.cpu.toL2Bus.snoop_fanout::1 4499985 99.30% 99.30% # Request fanout histogram 1155system.cpu.toL2Bus.snoop_fanout::2 31761 0.70% 100.00% # Request fanout histogram | 1154system.cpu.toL2Bus.snoop_fanout::1 4499987 99.30% 99.30% # Request fanout histogram 1155system.cpu.toL2Bus.snoop_fanout::2 31809 0.70% 100.00% # Request fanout histogram |
| 1156system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1156system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1159system.cpu.toL2Bus.snoop_fanout::total 4531746 # Request fanout histogram 1160system.cpu.toL2Bus.reqLayer0.occupancy 3216331500 # Layer occupancy (ticks) | 1159system.cpu.toL2Bus.snoop_fanout::total 4531796 # Request fanout histogram 1160system.cpu.toL2Bus.reqLayer0.occupancy 3216332500 # Layer occupancy (ticks) |
| 1161system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) | 1161system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) |
| 1162system.cpu.toL2Bus.respLayer0.occupancy 1074485469 # Layer occupancy (ticks) | 1162system.cpu.toL2Bus.respLayer0.occupancy 1074486969 # Layer occupancy (ticks) |
| 1163system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) | 1163system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) |
| 1164system.cpu.toL2Bus.respLayer1.occupancy 2301553965 # Layer occupancy (ticks) | 1164system.cpu.toL2Bus.respLayer1.occupancy 2301554963 # Layer occupancy (ticks) |
| 1165system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) | 1165system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) |
| 1166system.membus.trans_dist::ReadResp 6571 # Transaction distribution | 1166system.membus.trans_dist::ReadResp 6592 # Transaction distribution |
| 1167system.membus.trans_dist::UpgradeReq 1 # Transaction distribution 1168system.membus.trans_dist::UpgradeResp 1 # Transaction distribution | 1167system.membus.trans_dist::UpgradeReq 1 # Transaction distribution 1168system.membus.trans_dist::UpgradeResp 1 # Transaction distribution |
| 1169system.membus.trans_dist::ReadExReq 740 # Transaction distribution 1170system.membus.trans_dist::ReadExResp 740 # Transaction distribution 1171system.membus.trans_dist::ReadSharedReq 6571 # Transaction distribution 1172system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14624 # Packet count per connected master and slave (bytes) 1173system.membus.pkt_count::total 14624 # Packet count per connected master and slave (bytes) 1174system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467904 # Cumulative packet size per connected master and slave (bytes) 1175system.membus.pkt_size::total 467904 # Cumulative packet size per connected master and slave (bytes) | 1169system.membus.trans_dist::ReadExReq 731 # Transaction distribution 1170system.membus.trans_dist::ReadExResp 731 # Transaction distribution 1171system.membus.trans_dist::ReadSharedReq 6592 # Transaction distribution 1172system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14648 # Packet count per connected master and slave (bytes) 1173system.membus.pkt_count::total 14648 # Packet count per connected master and slave (bytes) 1174system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468672 # Cumulative packet size per connected master and slave (bytes) 1175system.membus.pkt_size::total 468672 # Cumulative packet size per connected master and slave (bytes) |
| 1176system.membus.snoops 0 # Total snoops (count) | 1176system.membus.snoops 0 # Total snoops (count) |
| 1177system.membus.snoop_fanout::samples 7312 # Request fanout histogram | 1177system.membus.snoop_fanout::samples 7324 # Request fanout histogram |
| 1178system.membus.snoop_fanout::mean 0 # Request fanout histogram 1179system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1180system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1178system.membus.snoop_fanout::mean 0 # Request fanout histogram 1179system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1180system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1181system.membus.snoop_fanout::0 7312 100.00% 100.00% # Request fanout histogram | 1181system.membus.snoop_fanout::0 7324 100.00% 100.00% # Request fanout histogram |
| 1182system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1183system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1184system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1185system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1182system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1183system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1184system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1185system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1186system.membus.snoop_fanout::total 7312 # Request fanout histogram 1187system.membus.reqLayer0.occupancy 9348857 # Layer occupancy (ticks) | 1186system.membus.snoop_fanout::total 7324 # Request fanout histogram 1187system.membus.reqLayer0.occupancy 9437390 # Layer occupancy (ticks) |
| 1188system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1188system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1189system.membus.respLayer1.occupancy 38261400 # Layer occupancy (ticks) | 1189system.membus.respLayer1.occupancy 38347412 # Layer occupancy (ticks) |
| 1190system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1191 1192---------- End Simulation Statistics ---------- | 1190system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1191 1192---------- End Simulation Statistics ---------- |