| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.112541 # Number of seconds simulated 4sim_ticks 112540655000 # Number of ticks simulated 5final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.112624 # Number of seconds simulated 4sim_ticks 112623767500 # Number of ticks simulated 5final_tick 112623767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 132153 # Simulator instruction rate (inst/s) 8host_op_rate 158665 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 54470958 # Simulator tick rate (ticks/s) 10host_mem_usage 270904 # Number of bytes of host memory used 11host_seconds 2066.07 # Real time elapsed on the host | 7host_inst_rate 123996 # Simulator instruction rate (inst/s) 8host_op_rate 148871 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 51146556 # Simulator tick rate (ticks/s) 10host_mem_usage 325020 # Number of bytes of host memory used 11host_seconds 2201.98 # Real time elapsed on the host |
| 12sim_insts 273037219 # Number of instructions simulated 13sim_ops 327811601 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 273037219 # Number of instructions simulated 13sim_ops 327811601 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory 19system.physmem.bytes_read::total 623680 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 9745 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 9745 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 169856 # Number of bytes read from this memory 19system.physmem.bytes_read::total 469120 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 2654 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 7330 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1661035 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 996166 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 1508172 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 4165373 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 1661035 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 1661035 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 1661035 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 996166 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 1508172 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 4165373 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 7330 # Number of read requests accepted |
| 37system.physmem.writeReqs 0 # Number of write requests accepted | 37system.physmem.writeReqs 0 # Number of write requests accepted |
| 38system.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue | 38system.physmem.readBursts 7330 # Number of DRAM read bursts, including those serviced by the write queue |
| 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 40system.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM | 40system.physmem.bytesReadDRAM 469120 # Total number of bytes read from DRAM |
| 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 43system.physmem.bytesReadSys 623680 # Total read bytes from the system interface side | 43system.physmem.bytesReadSys 469120 # Total read bytes from the system interface side |
| 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write | 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write |
| 48system.physmem.perBankRdBursts::0 803 # Per bank write bursts 49system.physmem.perBankRdBursts::1 999 # Per bank write bursts 50system.physmem.perBankRdBursts::2 769 # Per bank write bursts 51system.physmem.perBankRdBursts::3 645 # Per bank write bursts 52system.physmem.perBankRdBursts::4 618 # Per bank write bursts 53system.physmem.perBankRdBursts::5 484 # Per bank write bursts 54system.physmem.perBankRdBursts::6 251 # Per bank write bursts 55system.physmem.perBankRdBursts::7 363 # Per bank write bursts 56system.physmem.perBankRdBursts::8 300 # Per bank write bursts 57system.physmem.perBankRdBursts::9 432 # Per bank write bursts 58system.physmem.perBankRdBursts::10 486 # Per bank write bursts 59system.physmem.perBankRdBursts::11 534 # Per bank write bursts 60system.physmem.perBankRdBursts::12 696 # Per bank write bursts 61system.physmem.perBankRdBursts::13 850 # Per bank write bursts 62system.physmem.perBankRdBursts::14 782 # Per bank write bursts 63system.physmem.perBankRdBursts::15 733 # Per bank write bursts | 48system.physmem.perBankRdBursts::0 589 # Per bank write bursts 49system.physmem.perBankRdBursts::1 789 # Per bank write bursts 50system.physmem.perBankRdBursts::2 601 # Per bank write bursts 51system.physmem.perBankRdBursts::3 519 # Per bank write bursts 52system.physmem.perBankRdBursts::4 444 # Per bank write bursts 53system.physmem.perBankRdBursts::5 346 # Per bank write bursts 54system.physmem.perBankRdBursts::6 153 # Per bank write bursts 55system.physmem.perBankRdBursts::7 257 # Per bank write bursts 56system.physmem.perBankRdBursts::8 219 # Per bank write bursts 57system.physmem.perBankRdBursts::9 291 # Per bank write bursts 58system.physmem.perBankRdBursts::10 316 # Per bank write bursts 59system.physmem.perBankRdBursts::11 411 # Per bank write bursts 60system.physmem.perBankRdBursts::12 547 # Per bank write bursts 61system.physmem.perBankRdBursts::13 678 # Per bank write bursts 62system.physmem.perBankRdBursts::14 615 # Per bank write bursts 63system.physmem.perBankRdBursts::15 555 # Per bank write bursts |
| 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 82system.physmem.totGap 112540488500 # Total gap between requests | 82system.physmem.totGap 112623613500 # Total gap between requests |
| 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) | 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 89system.physmem.readPktSize::6 9745 # Read request sizes (log2) | 89system.physmem.readPktSize::6 7330 # Read request sizes (log2) |
| 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) | 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 97system.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see | 97system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 1454 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 242 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 199 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 176 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 139 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 109 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 64 unchanged lines hidden (view full) --- 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 64 unchanged lines hidden (view full) --- 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 193system.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation 207system.physmem.totQLat 248191131 # Total ticks spent queuing 208system.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 48725000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst | 193system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 340.446389 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 197.878789 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 348.729899 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 488 35.59% 35.59% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 298 21.74% 57.33% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 137 9.99% 67.32% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 90 6.56% 73.89% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 49 3.57% 77.46% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 55 4.01% 81.47% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 23 1.68% 83.15% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 26 1.90% 85.05% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 205 14.95% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation 207system.physmem.totQLat 100359280 # Total ticks spent queuing 208system.physmem.totMemAccLat 237796780 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 36650000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 13691.58 # Average queueing delay per DRAM burst |
| 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 212system.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s | 212system.physmem.avgMemAccLat 32441.58 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s |
| 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 215system.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s | 215system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s |
| 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 218system.physmem.busUtil 0.04 # Data bus utilization in percentage 219system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads | 218system.physmem.busUtil 0.03 # Data bus utilization in percentage 219system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads |
| 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 221system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing | 221system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing |
| 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 223system.physmem.readRowHits 8500 # Number of row buffer hits during reads | 223system.physmem.readRowHits 5950 # Number of row buffer hits during reads |
| 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 225system.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads | 225system.physmem.readRowHitRate 81.17 # Row buffer hit rate for reads |
| 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 227system.physmem.avgGap 11548536.53 # Average gap between requests 228system.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined 229system.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states 230system.physmem.memoryStateTime::REF 3757780000 # Time in different power states 231system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 232system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states 233system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 234system.physmem.actEnergy::0 4460400 # Energy for activate commands per rank (pJ) 235system.physmem.actEnergy::1 4845960 # Energy for activate commands per rank (pJ) 236system.physmem.preEnergy::0 2433750 # Energy for precharge commands per rank (pJ) 237system.physmem.preEnergy::1 2644125 # Energy for precharge commands per rank (pJ) 238system.physmem.readEnergy::0 38220000 # Energy for read commands per rank (pJ) 239system.physmem.readEnergy::1 37221600 # Energy for read commands per rank (pJ) 240system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 241system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 242system.physmem.refreshEnergy::0 7350217680 # Energy for refresh commands per rank (pJ) 243system.physmem.refreshEnergy::1 7350217680 # Energy for refresh commands per rank (pJ) 244system.physmem.actBackEnergy::0 3071428470 # Energy for active background per rank (pJ) 245system.physmem.actBackEnergy::1 3094710975 # Energy for active background per rank (pJ) 246system.physmem.preBackEnergy::0 64826723250 # Energy for precharge background per rank (pJ) 247system.physmem.preBackEnergy::1 64806300000 # Energy for precharge background per rank (pJ) 248system.physmem.totalEnergy::0 75293483550 # Total energy per rank (pJ) 249system.physmem.totalEnergy::1 75295940340 # Total energy per rank (pJ) 250system.physmem.averagePower::0 669.067664 # Core power per rank (mW) 251system.physmem.averagePower::1 669.089495 # Core power per rank (mW) 252system.membus.trans_dist::ReadReq 9170 # Transaction distribution 253system.membus.trans_dist::ReadResp 9170 # Transaction distribution 254system.membus.trans_dist::UpgradeReq 1 # Transaction distribution 255system.membus.trans_dist::UpgradeResp 1 # Transaction distribution 256system.membus.trans_dist::ReadExReq 575 # Transaction distribution 257system.membus.trans_dist::ReadExResp 575 # Transaction distribution 258system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes) 259system.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes) 260system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes) 261system.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes) 262system.membus.snoops 0 # Total snoops (count) 263system.membus.snoop_fanout::samples 9746 # Request fanout histogram 264system.membus.snoop_fanout::mean 0 # Request fanout histogram 265system.membus.snoop_fanout::stdev 0 # Request fanout histogram 266system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 267system.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram 268system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 269system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 270system.membus.snoop_fanout::min_value 0 # Request fanout histogram 271system.membus.snoop_fanout::max_value 0 # Request fanout histogram 272system.membus.snoop_fanout::total 9746 # Request fanout histogram 273system.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks) 274system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 275system.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks) 276system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 277system.cpu_clk_domain.clock 500 # Clock period in ticks 278system.cpu.branchPred.lookups 37763717 # Number of BP lookups 279system.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted 280system.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect 281system.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups 282system.cpu.branchPred.BTBHits 17302092 # Number of BTB hits | 227system.physmem.avgGap 15364749.45 # Average gap between requests 228system.physmem.pageHitRate 81.17 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) 234system.physmem_0.actBackEnergy 3232257390 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 64737034500 # Energy for precharge background per rank (pJ) 236system.physmem_0.totalEnergy 75361375695 # Total energy per rank (pJ) 237system.physmem_0.averagePower 669.161673 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 107692958200 # Time in different power states 239system.physmem_0.memoryStateTime::REF 3760640000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 241system.physmem_0.memoryStateTime::ACT 1167342300 # Time in different power states 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.physmem_1.actEnergy 5435640 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 2965875 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 28165800 # Energy for read commands per rank (pJ) 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) 248system.physmem_1.actBackEnergy 3291484950 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 64685080500 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 75368944605 # Total energy per rank (pJ) 251system.physmem_1.averagePower 669.228880 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 107605030400 # Time in different power states 253system.physmem_1.memoryStateTime::REF 3760640000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.physmem_1.memoryStateTime::ACT 1254923350 # Time in different power states 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 37762202 # Number of BP lookups 258system.cpu.branchPred.condPredicted 20178978 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 1746186 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 18669843 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 17301885 # Number of BTB hits |
| 283system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 284system.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage 285system.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target. 286system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. | 263system.cpu.branchPred.BTBHitPct 92.672900 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 7228775 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 3814 # Number of incorrect RAS predictions. 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| 287system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 288system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 289system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 290system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 291system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 292system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 293system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 294system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 300system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 301system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 302system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 303system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 304system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 305system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 306system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 307system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 275system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 276system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 277system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 278system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 279system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 280system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 296system.cpu.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 308system.cpu.dtb.inst_hits 0 # ITB inst hits 309system.cpu.dtb.inst_misses 0 # ITB inst misses 310system.cpu.dtb.read_hits 0 # DTB read hits 311system.cpu.dtb.read_misses 0 # DTB read misses 312system.cpu.dtb.write_hits 0 # DTB write hits 313system.cpu.dtb.write_misses 0 # DTB write misses 314system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 315system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses | 304system.cpu.dtb.inst_hits 0 # ITB inst hits 305system.cpu.dtb.inst_misses 0 # ITB inst misses 306system.cpu.dtb.read_hits 0 # DTB read hits 307system.cpu.dtb.read_misses 0 # DTB read misses 308system.cpu.dtb.write_hits 0 # DTB write hits 309system.cpu.dtb.write_misses 0 # DTB write misses 310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses |
| 325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 329system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 330system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 331system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 332system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 333system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 334system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 335system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 336system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 342system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 343system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 344system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 345system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 346system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 347system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 348system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 349system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 354system.cpu.itb.walker.walks 0 # Table walker walks requested 355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 350system.cpu.itb.inst_hits 0 # ITB inst hits 351system.cpu.itb.inst_misses 0 # ITB inst misses 352system.cpu.itb.read_hits 0 # DTB read hits 353system.cpu.itb.read_misses 0 # DTB read misses 354system.cpu.itb.write_hits 0 # DTB write hits 355system.cpu.itb.write_misses 0 # DTB write misses 356system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 357system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 364system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 365system.cpu.itb.read_accesses 0 # DTB read accesses 366system.cpu.itb.write_accesses 0 # DTB write accesses 367system.cpu.itb.inst_accesses 0 # ITB inst accesses 368system.cpu.itb.hits 0 # DTB hits 369system.cpu.itb.misses 0 # DTB misses 370system.cpu.itb.accesses 0 # DTB accesses 371system.cpu.workload.num_syscalls 191 # Number of system calls | 362system.cpu.itb.inst_hits 0 # ITB inst hits 363system.cpu.itb.inst_misses 0 # ITB inst misses 364system.cpu.itb.read_hits 0 # DTB read hits 365system.cpu.itb.read_misses 0 # DTB read misses 366system.cpu.itb.write_hits 0 # DTB write hits 367system.cpu.itb.write_misses 0 # DTB write misses 368system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 191 # Number of system calls |
| 372system.cpu.numCycles 225081311 # number of cpu cycles simulated | 384system.cpu.numCycles 225247536 # number of cpu cycles simulated |
| 373system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 374system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 375system.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss 376system.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed 377system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered 378system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken 379system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked 380system.cpu.fetch.SquashCycles 3511517 # Number of cycles fetch has spent squashing 381system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 382system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps 383system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR 384system.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched 385system.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed 386system.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total) | 387system.cpu.fetch.icacheStallCycles 12260997 # Number of cycles fetch is stalled on an Icache miss 388system.cpu.fetch.Insts 334142837 # Number of instructions fetch has processed 389system.cpu.fetch.Branches 37762202 # Number of branches that fetch encountered 390system.cpu.fetch.predictedBranches 24530660 # Number of branches that fetch has predicted taken 391system.cpu.fetch.Cycles 210950106 # Number of cycles fetch has run and was not squashing or blocked 392system.cpu.fetch.SquashCycles 3511423 # Number of cycles fetch has spent squashing 393system.cpu.fetch.MiscStallCycles 1112 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 394system.cpu.fetch.IcacheWaitRetryStallCycles 2317 # Number of stall cycles due to full MSHR 395system.cpu.fetch.CacheLines 89109626 # Number of cache lines fetched 396system.cpu.fetch.IcacheSquashes 21670 # Number of outstanding Icache misses that were squashed 397system.cpu.fetch.rateDist::samples 224970243 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::mean 1.801560 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::stdev 1.228501 # Number of instructions fetched each cycle (Total) |
| 389system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 400system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 390system.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total) | 401system.cpu.fetch.rateDist::0 51235855 22.77% 22.77% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::1 42807602 19.03% 41.80% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::2 30290628 13.46% 55.27% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::3 100636158 44.73% 100.00% # Number of instructions fetched each cycle (Total) |
| 394system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 405system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 397system.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle 399system.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle 400system.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle 401system.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked 402system.cpu.decode.RunCycles 108311612 # Number of cycles decode is running 403system.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking 404system.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing 405system.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch 406system.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction 407system.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode 408system.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode 409system.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing 410system.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle 411system.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking 412system.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst 413system.cpu.rename.RunCycles 113472399 # Number of cycles rename is running 414system.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking 415system.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename 416system.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename 417system.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full 418system.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full 419system.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full 420system.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full 421system.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers 422system.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed 423system.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made 424system.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups 425system.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups | 408system.cpu.fetch.rateDist::total 224970243 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.branchRate 0.167648 # Number of branch fetches per cycle 410system.cpu.fetch.rate 1.483447 # Number of inst fetches per cycle 411system.cpu.decode.IdleCycles 27756041 # Number of cycles decode is idle 412system.cpu.decode.BlockedCycles 64007493 # Number of cycles decode is blocked 413system.cpu.decode.RunCycles 108311444 # Number of cycles decode is running 414system.cpu.decode.UnblockCycles 23274289 # Number of cycles decode is unblocking 415system.cpu.decode.SquashCycles 1620976 # Number of cycles decode is squashing 416system.cpu.decode.BranchResolved 6880269 # Number of times decode resolved a branch 417system.cpu.decode.BranchMispred 135184 # Number of times decode detected a branch misprediction 418system.cpu.decode.DecodedInsts 363488172 # Number of instructions handled by decode 419system.cpu.decode.SquashedInsts 6272061 # Number of squashed instructions handled by decode 420system.cpu.rename.SquashCycles 1620976 # Number of cycles rename is squashing 421system.cpu.rename.IdleCycles 45214868 # Number of cycles rename is idle 422system.cpu.rename.BlockCycles 13194135 # Number of cycles rename is blocking 423system.cpu.rename.serializeStallCycles 339970 # count of cycles rename stalled for serializing inst 424system.cpu.rename.RunCycles 113472539 # Number of cycles rename is running 425system.cpu.rename.UnblockCycles 51127755 # Number of cycles rename is unblocking 426system.cpu.rename.RenamedInsts 355731319 # Number of instructions processed by rename 427system.cpu.rename.SquashedInsts 2913591 # Number of squashed instructions processed by rename 428system.cpu.rename.ROBFullEvents 6682784 # Number of times rename has blocked due to ROB full 429system.cpu.rename.IQFullEvents 150888 # Number of times rename has blocked due to IQ full 430system.cpu.rename.LQFullEvents 7653578 # Number of times rename has blocked due to LQ full 431system.cpu.rename.SQFullEvents 21157029 # Number of times rename has blocked due to SQ full 432system.cpu.rename.FullRegisterEvents 7934488 # Number of times there has been no free registers 433system.cpu.rename.RenamedOperands 403383639 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 2533813915 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 350195205 # Number of integer rename lookups 436system.cpu.rename.fp_rename_lookups 194873173 # Number of floating rename lookups |
| 426system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed | 437system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed |
| 427system.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing 428system.cpu.rename.serializingInsts 17017 # count of serializing insts renamed 429system.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed 430system.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer 431system.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit. 432system.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit. 433system.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads. 434system.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores. 435system.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec) 436system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ 437system.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued 438system.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued 439system.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling 440system.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph 441system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed 442system.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle | 438system.cpu.rename.UndoneMaps 31153588 # Number of HB maps that are undone due to squashing 439system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed 440system.cpu.rename.tempSerializingInsts 17052 # count of temporary serializing insts renamed 441system.cpu.rename.skidInsts 55396743 # count of insts added to the skid buffer 442system.cpu.memDep0.insertedLoads 92428788 # Number of loads inserted to the mem dependence unit. 443system.cpu.memDep0.insertedStores 88464605 # Number of stores inserted to the mem dependence unit. 444system.cpu.memDep0.conflictingLoads 1673696 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 1845347 # Number of conflicting stores. 446system.cpu.iq.iqInstsAdded 353205084 # Number of instructions added to the IQ (excludes non-spec) 447system.cpu.iq.iqNonSpecInstsAdded 28025 # Number of non-speculative instructions added to the IQ 448system.cpu.iq.iqInstsIssued 346266425 # Number of instructions issued 449system.cpu.iq.iqSquashedInstsIssued 2344670 # Number of squashed instructions issued 450system.cpu.iq.iqSquashedInstsExamined 24805703 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 73566871 # Number of squashed operands that are examined and possibly removed from graph 452system.cpu.iq.iqSquashedNonSpecRemoved 5905 # Number of squashed non-spec instructions that were removed 453system.cpu.iq.issued_per_cycle::samples 224970243 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 1.539165 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 1.101848 # Number of insts issued each cycle |
| 445system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 446system.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle | 457system.cpu.iq.issued_per_cycle::0 40745402 18.11% 18.11% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 78348887 34.83% 52.94% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 60751762 27.00% 79.94% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 34737500 15.44% 95.38% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::4 9740629 4.33% 99.71% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::5 637380 0.28% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 8683 0.00% 100.00% # Number of insts issued each cycle |
| 453system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle | 464system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle |
| 458system.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle | 469system.cpu.iq.issued_per_cycle::total 224970243 # Number of insts issued each cycle |
| 459system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 460system.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available 461system.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available | 471system.cpu.iq.fu_full::IntAlu 9315798 7.51% 7.51% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 7337 0.01% 7.52% # attempts to use FU when none available |
| 462system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available 463system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available 464system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available 465system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available 466system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available 467system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available 468system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available | 473system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available |
| 480system.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available | 491system.cpu.iq.fu_full::SimdFloatAdd 233455 0.19% 7.70% # attempts to use FU when none available |
| 481system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available | 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available |
| 482system.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available | 493system.cpu.iq.fu_full::SimdFloatCmp 152510 0.12% 7.83% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 103371 0.08% 7.91% # attempts to use FU when none available |
| 484system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available | 495system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available |
| 485system.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available | 496system.cpu.iq.fu_full::SimdFloatMisc 820015 0.66% 8.60% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 318375 0.26% 8.86% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 687813 0.55% 9.41% # attempts to use FU when none available |
| 488system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available | 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available |
| 489system.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available 490system.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available | 500system.cpu.iq.fu_full::MemRead 53407928 43.05% 52.46% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 58972553 47.54% 100.00% # attempts to use FU when none available |
| 491system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 492system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 493system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 494system.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued 495system.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued | 505system.cpu.iq.FU_type_0::IntAlu 110648263 31.95% 31.95% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 2148166 0.62% 32.58% # Type of FU issued |
| 496system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued 497system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued 498system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued 499system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued 500system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued 501system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued 502system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued | 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued |
| 514system.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued | 525system.cpu.iq.FU_type_0::SimdFloatAdd 6796965 1.96% 34.54% # Type of FU issued |
| 515system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued | 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued |
| 516system.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued | 527system.cpu.iq.FU_type_0::SimdFloatCmp 8667386 2.50% 37.04% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 3331882 0.96% 38.00% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatDiv 1592439 0.46% 38.46% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMisc 20937021 6.05% 44.51% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 7180792 2.07% 46.58% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147105 2.06% 48.65% # Type of FU issued |
| 522system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued | 533system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued |
| 523system.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued 524system.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued | 534system.cpu.iq.FU_type_0::MemRead 91783076 26.51% 75.20% # Type of FU issued 535system.cpu.iq.FU_type_0::MemWrite 85858044 24.80% 100.00% # Type of FU issued |
| 525system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 526system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 527system.cpu.iq.FU_type_0::total 346267862 # Type of FU issued 528system.cpu.iq.rate 1.538412 # Inst issue rate 529system.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested 530system.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst) 531system.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads 532system.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes 533system.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses 534system.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads 535system.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes 536system.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses 537system.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses 538system.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses 539system.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores | 538system.cpu.iq.FU_type_0::total 346266425 # Type of FU issued 539system.cpu.iq.rate 1.537271 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 124056335 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.358268 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 756639732 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 251256110 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 223226406 # Number of integer instruction queue wakeup accesses 545system.cpu.iq.fp_inst_queue_reads 287264366 # Number of floating instruction queue reads 546system.cpu.iq.fp_inst_queue_writes 126793395 # Number of floating instruction queue writes 547system.cpu.iq.fp_inst_queue_wakeup_accesses 117417412 # Number of floating instruction queue wakeup accesses 548system.cpu.iq.int_alu_accesses 302952760 # Number of integer alu accesses 549system.cpu.iq.fp_alu_accesses 167370000 # Number of floating point alu accesses 550system.cpu.iew.lsq.thread0.forwLoads 5033832 # Number of loads that had data forwarded from stores |
| 540system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 541system.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed 542system.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed 543system.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations 544system.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed | 552system.cpu.iew.lsq.thread0.squashedLoads 6696513 # Number of loads squashed 553system.cpu.iew.lsq.thread0.ignoredResponses 13646 # Number of memory responses ignored because the instruction is squashed 554system.cpu.iew.lsq.thread0.memOrderViolation 10697 # Number of memory ordering violations 555system.cpu.iew.lsq.thread0.squashedStores 6088988 # Number of stores squashed |
| 545system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 546system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 547system.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled 548system.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked | 558system.cpu.iew.lsq.thread0.rescheduledLoads 151171 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 488903 # Number of times an access to memory failed due to the cache being blocked |
| 549system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 550system.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing 551system.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking 552system.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking 553system.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ | 561system.cpu.iew.iewSquashCycles 1620976 # Number of cycles IEW is squashing 562system.cpu.iew.iewBlockCycles 2121777 # Number of cycles IEW is blocking 563system.cpu.iew.iewUnblockCycles 321028 # Number of cycles IEW is unblocking 564system.cpu.iew.iewDispatchedInsts 353233977 # Number of instructions dispatched to IQ |
| 554system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 565system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 555system.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions 556system.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions 557system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions 558system.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall 559system.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall 560system.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations 561system.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly 562system.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly 563system.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute 564system.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions 565system.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed 566system.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute | 566system.cpu.iew.iewDispLoadInsts 92428788 # Number of dispatched load instructions 567system.cpu.iew.iewDispStoreInsts 88464605 # Number of dispatched store instructions 568system.cpu.iew.iewDispNonSpecInsts 16992 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 8078 # Number of times the IQ has become full, causing a stall 570system.cpu.iew.iewLSQFullEvents 328775 # Number of times the LSQ has become full, causing a stall 571system.cpu.iew.memOrderViolationEvents 10697 # Number of memory order violations 572system.cpu.iew.predictedTakenIncorrect 1220281 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 438299 # Number of branches that were predicted not taken incorrectly 574system.cpu.iew.branchMispredicts 1658580 # Number of branch mispredicts detected at execute 575system.cpu.iew.iewExecutedInsts 342303629 # Number of executed instructions 576system.cpu.iew.iewExecLoadInsts 90585110 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 3962796 # Number of squashed instructions skipped in execute |
| 567system.cpu.iew.exec_swp 0 # number of swp insts executed | 578system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 568system.cpu.iew.exec_nop 864 # number of nop insts executed 569system.cpu.iew.exec_refs 175168098 # number of memory reference insts executed 570system.cpu.iew.exec_branches 31752179 # Number of branches executed 571system.cpu.iew.exec_stores 84582729 # Number of stores executed 572system.cpu.iew.exec_rate 1.520806 # Inst execution rate 573system.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit 574system.cpu.iew.wb_count 340645195 # cumulative count of insts written-back 575system.cpu.iew.wb_producers 153543382 # num instructions producing a value 576system.cpu.iew.wb_consumers 265817565 # num instructions consuming a value | 579system.cpu.iew.exec_nop 868 # number of nop insts executed 580system.cpu.iew.exec_refs 175167602 # number of memory reference insts executed 581system.cpu.iew.exec_branches 31752029 # Number of branches executed 582system.cpu.iew.exec_stores 84582492 # Number of stores executed 583system.cpu.iew.exec_rate 1.519678 # Inst execution rate 584system.cpu.iew.wb_sent 340903564 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 340643818 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 153542130 # num instructions producing a value 587system.cpu.iew.wb_consumers 265815285 # num instructions consuming a value |
| 577system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 578system.cpu.iew.wb_rate 1.513432 # insts written-back per cycle | 589system.cpu.iew.wb_rate 1.512309 # insts written-back per cycle |
| 579system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back 580system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 590system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 581system.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit | 592system.cpu.commit.commitSquashedInsts 22999072 # The number of squashed insts skipped by commit |
| 582system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards | 593system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards |
| 583system.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted 584system.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle | 594system.cpu.commit.branchMispredicts 1611451 # The number of times a branch was mispredicted 595system.cpu.commit.committed_per_cycle::samples 221242338 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 1.481688 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 2.053337 # Number of insts commited each cycle |
| 587system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 588system.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle | 599system.cpu.commit.committed_per_cycle::0 87860442 39.71% 39.71% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 69868164 31.58% 71.29% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 20927833 9.46% 80.75% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 13474111 6.09% 86.84% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 8800250 3.98% 90.82% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 4584845 2.07% 92.89% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 2913190 1.32% 94.21% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 2446339 1.11% 95.31% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 10367164 4.69% 100.00% # Number of insts commited each cycle |
| 597system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 600system.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle | 611system.cpu.commit.committed_per_cycle::total 221242338 # Number of insts commited each cycle |
| 601system.cpu.commit.committedInsts 273037831 # Number of instructions committed 602system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed 603system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 604system.cpu.commit.refs 168107892 # Number of memory references committed 605system.cpu.commit.loads 85732275 # Number of loads committed 606system.cpu.commit.membars 11033 # Number of memory barriers committed 607system.cpu.commit.branches 30563525 # Number of branches committed 608system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 638system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 641system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 642system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 643system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 644system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 645system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction | 612system.cpu.commit.committedInsts 273037831 # Number of instructions committed 613system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 168107892 # Number of memory references committed 616system.cpu.commit.loads 85732275 # Number of loads committed 617system.cpu.commit.membars 11033 # Number of memory barriers committed 618system.cpu.commit.branches 30563525 # Number of branches committed 619system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 649system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction |
| 646system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached | 657system.cpu.commit.bw_lim_events 10367164 # number cycles where commit BW limit reached |
| 647system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 658system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 648system.cpu.rob.rob_reads 561656707 # The number of ROB reads 649system.cpu.rob.rob_writes 705358339 # The number of ROB writes 650system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself 651system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling | 659system.cpu.rob.rob_reads 561683936 # The number of ROB reads 660system.cpu.rob.rob_writes 705354391 # The number of ROB writes 661system.cpu.timesIdled 50923 # Number of times that the entire CPU went into an idle state and unscheduled itself 662system.cpu.idleCycles 277293 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 652system.cpu.committedInsts 273037219 # Number of Instructions Simulated 653system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated | 663system.cpu.committedInsts 273037219 # Number of Instructions Simulated 664system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated |
| 654system.cpu.cpi 0.824361 # CPI: Cycles Per Instruction 655system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads 656system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle 657system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads 658system.cpu.int_regfile_reads 331187240 # number of integer regfile reads 659system.cpu.int_regfile_writes 136909181 # number of integer regfile writes 660system.cpu.fp_regfile_reads 187100304 # number of floating regfile reads 661system.cpu.fp_regfile_writes 132166714 # number of floating regfile writes 662system.cpu.cc_regfile_reads 1296661589 # number of cc regfile reads 663system.cpu.cc_regfile_writes 80246596 # number of cc regfile writes 664system.cpu.misc_regfile_reads 1182269483 # number of misc regfile reads | 665system.cpu.cpi 0.824970 # CPI: Cycles Per Instruction 666system.cpu.cpi_total 0.824970 # CPI: Total CPI of All Threads 667system.cpu.ipc 1.212165 # IPC: Instructions Per Cycle 668system.cpu.ipc_total 1.212165 # IPC: Total IPC of All Threads 669system.cpu.int_regfile_reads 331186150 # number of integer regfile reads 670system.cpu.int_regfile_writes 136908474 # number of integer regfile writes 671system.cpu.fp_regfile_reads 187099872 # number of floating regfile reads 672system.cpu.fp_regfile_writes 132166295 # number of floating regfile writes 673system.cpu.cc_regfile_reads 1296656595 # number of cc regfile reads 674system.cpu.cc_regfile_writes 80246016 # number of cc regfile writes 675system.cpu.misc_regfile_reads 1182266137 # number of misc regfile reads |
| 665system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes | 676system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes |
| 666system.cpu.toL2Bus.trans_dist::ReadReq 2029653 # Transaction distribution 667system.cpu.toL2Bus.trans_dist::ReadResp 2029653 # Transaction distribution 668system.cpu.toL2Bus.trans_dist::Writeback 966282 # Transaction distribution 669system.cpu.toL2Bus.trans_dist::HardPFReq 49309 # Transaction distribution 670system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 671system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 672system.cpu.toL2Bus.trans_dist::ReadExReq 220486 # Transaction distribution 673system.cpu.toL2Bus.trans_dist::ReadExResp 220486 # Transaction distribution 674system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430858 # Packet count per connected master and slave (bytes) 675system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034802 # Packet count per connected master and slave (bytes) 676system.cpu.toL2Bus.pkt_count::total 5465660 # Packet count per connected master and slave (bytes) 677system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45758528 # Cumulative packet size per connected master and slave (bytes) 678system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034560 # Cumulative packet size per connected master and slave (bytes) 679system.cpu.toL2Bus.pkt_size::total 205793088 # Cumulative packet size per connected master and slave (bytes) 680system.cpu.toL2Bus.snoops 50213 # Total snoops (count) 681system.cpu.toL2Bus.snoop_fanout::samples 3265775 # Request fanout histogram 682system.cpu.toL2Bus.snoop_fanout::mean 5.015099 # Request fanout histogram 683system.cpu.toL2Bus.snoop_fanout::stdev 0.121946 # Request fanout histogram 684system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 685system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 686system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 687system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 688system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 689system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 690system.cpu.toL2Bus.snoop_fanout::5 3216466 98.49% 98.49% # Request fanout histogram 691system.cpu.toL2Bus.snoop_fanout::6 49309 1.51% 100.00% # Request fanout histogram 692system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 693system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 694system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 695system.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram 696system.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks) 697system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) 698system.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks) 699system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 700system.cpu.toL2Bus.respLayer1.occupancy 2301537734 # Layer occupancy (ticks) 701system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) 702system.cpu.icache.tags.replacements 715368 # number of replacements 703system.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use 704system.cpu.icache.tags.total_refs 88391816 # Total number of references to valid blocks. 705system.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks. 706system.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks. 707system.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit. 708system.cpu.icache.tags.occ_blocks::cpu.inst 511.871967 # Average occupied blocks per requestor 709system.cpu.icache.tags.occ_percent::cpu.inst 0.999750 # Average percentage of cache occupancy 710system.cpu.icache.tags.occ_percent::total 0.999750 # Average percentage of cache occupancy 711system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 712system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 713system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 714system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id 715system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 716system.cpu.icache.tags.age_task_id_blocks_1024::4 66 # Occupied blocks per task id 717system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 718system.cpu.icache.tags.tag_accesses 178939093 # Number of tag accesses 719system.cpu.icache.tags.data_accesses 178939093 # Number of data accesses 720system.cpu.icache.ReadReq_hits::cpu.inst 88391816 # number of ReadReq hits 721system.cpu.icache.ReadReq_hits::total 88391816 # number of ReadReq hits 722system.cpu.icache.demand_hits::cpu.inst 88391816 # number of demand (read+write) hits 723system.cpu.icache.demand_hits::total 88391816 # number of demand (read+write) hits 724system.cpu.icache.overall_hits::cpu.inst 88391816 # number of overall hits 725system.cpu.icache.overall_hits::total 88391816 # number of overall hits 726system.cpu.icache.ReadReq_misses::cpu.inst 719790 # number of ReadReq misses 727system.cpu.icache.ReadReq_misses::total 719790 # number of ReadReq misses 728system.cpu.icache.demand_misses::cpu.inst 719790 # number of demand (read+write) misses 729system.cpu.icache.demand_misses::total 719790 # number of demand (read+write) misses 730system.cpu.icache.overall_misses::cpu.inst 719790 # number of overall misses 731system.cpu.icache.overall_misses::total 719790 # number of overall misses 732system.cpu.icache.ReadReq_miss_latency::cpu.inst 5791847611 # number of ReadReq miss cycles 733system.cpu.icache.ReadReq_miss_latency::total 5791847611 # number of ReadReq miss cycles 734system.cpu.icache.demand_miss_latency::cpu.inst 5791847611 # number of demand (read+write) miss cycles 735system.cpu.icache.demand_miss_latency::total 5791847611 # number of demand (read+write) miss cycles 736system.cpu.icache.overall_miss_latency::cpu.inst 5791847611 # number of overall miss cycles 737system.cpu.icache.overall_miss_latency::total 5791847611 # number of overall miss cycles 738system.cpu.icache.ReadReq_accesses::cpu.inst 89111606 # number of ReadReq accesses(hits+misses) 739system.cpu.icache.ReadReq_accesses::total 89111606 # number of ReadReq accesses(hits+misses) 740system.cpu.icache.demand_accesses::cpu.inst 89111606 # number of demand (read+write) accesses 741system.cpu.icache.demand_accesses::total 89111606 # number of demand (read+write) accesses 742system.cpu.icache.overall_accesses::cpu.inst 89111606 # number of overall (read+write) accesses 743system.cpu.icache.overall_accesses::total 89111606 # number of overall (read+write) accesses 744system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008077 # miss rate for ReadReq accesses 745system.cpu.icache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses 746system.cpu.icache.demand_miss_rate::cpu.inst 0.008077 # miss rate for demand accesses 747system.cpu.icache.demand_miss_rate::total 0.008077 # miss rate for demand accesses 748system.cpu.icache.overall_miss_rate::cpu.inst 0.008077 # miss rate for overall accesses 749system.cpu.icache.overall_miss_rate::total 0.008077 # miss rate for overall accesses 750system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8046.579712 # average ReadReq miss latency 751system.cpu.icache.ReadReq_avg_miss_latency::total 8046.579712 # average ReadReq miss latency 752system.cpu.icache.demand_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency 753system.cpu.icache.demand_avg_miss_latency::total 8046.579712 # average overall miss latency 754system.cpu.icache.overall_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency 755system.cpu.icache.overall_avg_miss_latency::total 8046.579712 # average overall miss latency 756system.cpu.icache.blocked_cycles::no_mshrs 12631 # number of cycles access was blocked 757system.cpu.icache.blocked_cycles::no_targets 17 # number of cycles access was blocked 758system.cpu.icache.blocked::no_mshrs 1514 # number of cycles access was blocked 759system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 760system.cpu.icache.avg_blocked_cycles::no_mshrs 8.342801 # average number of cycles each access was blocked 761system.cpu.icache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked 762system.cpu.icache.fast_writes 0 # number of fast writes performed 763system.cpu.icache.cache_copies 0 # number of cache copies performed 764system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3909 # number of ReadReq MSHR hits 765system.cpu.icache.ReadReq_mshr_hits::total 3909 # number of ReadReq MSHR hits 766system.cpu.icache.demand_mshr_hits::cpu.inst 3909 # number of demand (read+write) MSHR hits 767system.cpu.icache.demand_mshr_hits::total 3909 # number of demand (read+write) MSHR hits 768system.cpu.icache.overall_mshr_hits::cpu.inst 3909 # number of overall MSHR hits 769system.cpu.icache.overall_mshr_hits::total 3909 # number of overall MSHR hits 770system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715881 # number of ReadReq MSHR misses 771system.cpu.icache.ReadReq_mshr_misses::total 715881 # number of ReadReq MSHR misses 772system.cpu.icache.demand_mshr_misses::cpu.inst 715881 # number of demand (read+write) MSHR misses 773system.cpu.icache.demand_mshr_misses::total 715881 # number of demand (read+write) MSHR misses 774system.cpu.icache.overall_mshr_misses::cpu.inst 715881 # number of overall MSHR misses 775system.cpu.icache.overall_mshr_misses::total 715881 # number of overall MSHR misses 776system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4688303087 # number of ReadReq MSHR miss cycles 777system.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles 778system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4688303087 # number of demand (read+write) MSHR miss cycles 779system.cpu.icache.demand_mshr_miss_latency::total 4688303087 # number of demand (read+write) MSHR miss cycles 780system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4688303087 # number of overall MSHR miss cycles 781system.cpu.icache.overall_mshr_miss_latency::total 4688303087 # number of overall MSHR miss cycles 782system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for ReadReq accesses 783system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses 784system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for demand accesses 785system.cpu.icache.demand_mshr_miss_rate::total 0.008034 # mshr miss rate for demand accesses 786system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for overall accesses 787system.cpu.icache.overall_mshr_miss_rate::total 0.008034 # mshr miss rate for overall accesses 788system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6548.997790 # average ReadReq mshr miss latency 789system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6548.997790 # average ReadReq mshr miss latency 790system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency 791system.cpu.icache.demand_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency 792system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency 793system.cpu.icache.overall_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency 794system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 795system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 6641923 # number of hwpf identified 796system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 7386 # number of hwpf that were already in mshr 797system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6574564 # number of hwpf that were already in the cache 798system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 13578 # number of hwpf that were already in the prefetch queue 799system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 800system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated 801system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 44298 # number of hwpf issued 802system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 135685 # number of hwpf spanning a virtual page 803system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 804system.cpu.l2cache.tags.replacements 0 # number of replacements 805system.cpu.l2cache.tags.tagsinuse 8320.579960 # Cycle average of tags in use 806system.cpu.l2cache.tags.total_refs 2794148 # Total number of references to valid blocks. 807system.cpu.l2cache.tags.sampled_refs 9718 # Sample count of references to valid blocks. 808system.cpu.l2cache.tags.avg_refs 287.522947 # Average number of references to valid blocks. 809system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 810system.cpu.l2cache.tags.occ_blocks::writebacks 2574.248018 # Average occupied blocks per requestor 811system.cpu.l2cache.tags.occ_blocks::cpu.inst 441.129211 # Average occupied blocks per requestor 812system.cpu.l2cache.tags.occ_blocks::cpu.data 367.415546 # Average occupied blocks per requestor 813system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4937.787185 # Average occupied blocks per requestor 814system.cpu.l2cache.tags.occ_percent::writebacks 0.157120 # Average percentage of cache occupancy 815system.cpu.l2cache.tags.occ_percent::cpu.inst 0.026924 # Average percentage of cache occupancy 816system.cpu.l2cache.tags.occ_percent::cpu.data 0.022425 # Average percentage of cache occupancy 817system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.301379 # Average percentage of cache occupancy 818system.cpu.l2cache.tags.occ_percent::total 0.507848 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_task_id_blocks::1022 5676 # Occupied blocks per task id 820system.cpu.l2cache.tags.occ_task_id_blocks::1024 4042 # Occupied blocks per task id 821system.cpu.l2cache.tags.age_task_id_blocks_1022::0 59 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1022::1 84 # Occupied blocks per task id 823system.cpu.l2cache.tags.age_task_id_blocks_1022::2 572 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4961 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 827system.cpu.l2cache.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id 828system.cpu.l2cache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id 829system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3234 # Occupied blocks per task id 830system.cpu.l2cache.tags.occ_task_id_percent::1022 0.346436 # Percentage of cache occupancy per task id 831system.cpu.l2cache.tags.occ_task_id_percent::1024 0.246704 # Percentage of cache occupancy per task id 832system.cpu.l2cache.tags.tag_accesses 51678510 # Number of tag accesses 833system.cpu.l2cache.tags.data_accesses 51678510 # Number of data accesses 834system.cpu.l2cache.ReadReq_hits::cpu.inst 714431 # number of ReadReq hits 835system.cpu.l2cache.ReadReq_hits::cpu.data 1313042 # number of ReadReq hits 836system.cpu.l2cache.ReadReq_hits::total 2027473 # number of ReadReq hits 837system.cpu.l2cache.Writeback_hits::writebacks 966282 # number of Writeback hits 838system.cpu.l2cache.Writeback_hits::total 966282 # number of Writeback hits 839system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 840system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 841system.cpu.l2cache.ReadExReq_hits::cpu.data 219797 # number of ReadExReq hits 842system.cpu.l2cache.ReadExReq_hits::total 219797 # number of ReadExReq hits 843system.cpu.l2cache.demand_hits::cpu.inst 714431 # number of demand (read+write) hits 844system.cpu.l2cache.demand_hits::cpu.data 1532839 # number of demand (read+write) hits 845system.cpu.l2cache.demand_hits::total 2247270 # number of demand (read+write) hits 846system.cpu.l2cache.overall_hits::cpu.inst 714431 # number of overall hits 847system.cpu.l2cache.overall_hits::cpu.data 1532839 # number of overall hits 848system.cpu.l2cache.overall_hits::total 2247270 # number of overall hits 849system.cpu.l2cache.ReadReq_misses::cpu.inst 546 # number of ReadReq misses 850system.cpu.l2cache.ReadReq_misses::cpu.data 730 # number of ReadReq misses 851system.cpu.l2cache.ReadReq_misses::total 1276 # number of ReadReq misses 852system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 853system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 854system.cpu.l2cache.ReadExReq_misses::cpu.data 689 # number of ReadExReq misses 855system.cpu.l2cache.ReadExReq_misses::total 689 # number of ReadExReq misses 856system.cpu.l2cache.demand_misses::cpu.inst 546 # number of demand (read+write) misses 857system.cpu.l2cache.demand_misses::cpu.data 1419 # number of demand (read+write) misses 858system.cpu.l2cache.demand_misses::total 1965 # number of demand (read+write) misses 859system.cpu.l2cache.overall_misses::cpu.inst 546 # number of overall misses 860system.cpu.l2cache.overall_misses::cpu.data 1419 # number of overall misses 861system.cpu.l2cache.overall_misses::total 1965 # number of overall misses 862system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38998499 # number of ReadReq miss cycles 863system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50021748 # number of ReadReq miss cycles 864system.cpu.l2cache.ReadReq_miss_latency::total 89020247 # number of ReadReq miss cycles 865system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles 866system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles 867system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41954499 # number of ReadExReq miss cycles 868system.cpu.l2cache.ReadExReq_miss_latency::total 41954499 # number of ReadExReq miss cycles 869system.cpu.l2cache.demand_miss_latency::cpu.inst 38998499 # number of demand (read+write) miss cycles 870system.cpu.l2cache.demand_miss_latency::cpu.data 91976247 # number of demand (read+write) miss cycles 871system.cpu.l2cache.demand_miss_latency::total 130974746 # number of demand (read+write) miss cycles 872system.cpu.l2cache.overall_miss_latency::cpu.inst 38998499 # number of overall miss cycles 873system.cpu.l2cache.overall_miss_latency::cpu.data 91976247 # number of overall miss cycles 874system.cpu.l2cache.overall_miss_latency::total 130974746 # number of overall miss cycles 875system.cpu.l2cache.ReadReq_accesses::cpu.inst 714977 # number of ReadReq accesses(hits+misses) 876system.cpu.l2cache.ReadReq_accesses::cpu.data 1313772 # number of ReadReq accesses(hits+misses) 877system.cpu.l2cache.ReadReq_accesses::total 2028749 # number of ReadReq accesses(hits+misses) 878system.cpu.l2cache.Writeback_accesses::writebacks 966282 # number of Writeback accesses(hits+misses) 879system.cpu.l2cache.Writeback_accesses::total 966282 # number of Writeback accesses(hits+misses) 880system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 881system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 882system.cpu.l2cache.ReadExReq_accesses::cpu.data 220486 # number of ReadExReq accesses(hits+misses) 883system.cpu.l2cache.ReadExReq_accesses::total 220486 # number of ReadExReq accesses(hits+misses) 884system.cpu.l2cache.demand_accesses::cpu.inst 714977 # number of demand (read+write) accesses 885system.cpu.l2cache.demand_accesses::cpu.data 1534258 # number of demand (read+write) accesses 886system.cpu.l2cache.demand_accesses::total 2249235 # number of demand (read+write) accesses 887system.cpu.l2cache.overall_accesses::cpu.inst 714977 # number of overall (read+write) accesses 888system.cpu.l2cache.overall_accesses::cpu.data 1534258 # number of overall (read+write) accesses 889system.cpu.l2cache.overall_accesses::total 2249235 # number of overall (read+write) accesses 890system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000764 # miss rate for ReadReq accesses 891system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000556 # miss rate for ReadReq accesses 892system.cpu.l2cache.ReadReq_miss_rate::total 0.000629 # miss rate for ReadReq accesses 893system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses 894system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses 895system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003125 # miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadExReq_miss_rate::total 0.003125 # miss rate for ReadExReq accesses 897system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000764 # miss rate for demand accesses 898system.cpu.l2cache.demand_miss_rate::cpu.data 0.000925 # miss rate for demand accesses 899system.cpu.l2cache.demand_miss_rate::total 0.000874 # miss rate for demand accesses 900system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000764 # miss rate for overall accesses 901system.cpu.l2cache.overall_miss_rate::cpu.data 0.000925 # miss rate for overall accesses 902system.cpu.l2cache.overall_miss_rate::total 0.000874 # miss rate for overall accesses 903system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71425.822344 # average ReadReq miss latency 904system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68522.942466 # average ReadReq miss latency 905system.cpu.l2cache.ReadReq_avg_miss_latency::total 69765.083856 # average ReadReq miss latency 906system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency 907system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency 908system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60891.870827 # average ReadExReq miss latency 909system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60891.870827 # average ReadExReq miss latency 910system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency 911system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency 912system.cpu.l2cache.demand_avg_miss_latency::total 66653.814758 # average overall miss latency 913system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency 914system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency 915system.cpu.l2cache.overall_avg_miss_latency::total 66653.814758 # average overall miss latency 916system.cpu.l2cache.blocked_cycles::no_mshrs 6173 # number of cycles access was blocked 917system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 918system.cpu.l2cache.blocked::no_mshrs 209 # number of cycles access was blocked 919system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 920system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.535885 # average number of cycles each access was blocked 921system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 922system.cpu.l2cache.fast_writes 0 # number of fast writes performed 923system.cpu.l2cache.cache_copies 0 # number of cache copies performed 924system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 925system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits 926system.cpu.l2cache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits 927system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 114 # number of ReadExReq MSHR hits 928system.cpu.l2cache.ReadExReq_mshr_hits::total 114 # number of ReadExReq MSHR hits 929system.cpu.l2cache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 930system.cpu.l2cache.demand_mshr_hits::cpu.data 157 # number of demand (read+write) MSHR hits 931system.cpu.l2cache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits 932system.cpu.l2cache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 933system.cpu.l2cache.overall_mshr_hits::cpu.data 157 # number of overall MSHR hits 934system.cpu.l2cache.overall_mshr_hits::total 225 # number of overall MSHR hits 935system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 478 # number of ReadReq MSHR misses 936system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 687 # number of ReadReq MSHR misses 937system.cpu.l2cache.ReadReq_mshr_misses::total 1165 # number of ReadReq MSHR misses 938system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 44298 # number of HardPFReq MSHR misses 939system.cpu.l2cache.HardPFReq_mshr_misses::total 44298 # number of HardPFReq MSHR misses 940system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 941system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 942system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 575 # number of ReadExReq MSHR misses 943system.cpu.l2cache.ReadExReq_mshr_misses::total 575 # number of ReadExReq MSHR misses 944system.cpu.l2cache.demand_mshr_misses::cpu.inst 478 # number of demand (read+write) MSHR misses 945system.cpu.l2cache.demand_mshr_misses::cpu.data 1262 # number of demand (read+write) MSHR misses 946system.cpu.l2cache.demand_mshr_misses::total 1740 # number of demand (read+write) MSHR misses 947system.cpu.l2cache.overall_mshr_misses::cpu.inst 478 # number of overall MSHR misses 948system.cpu.l2cache.overall_mshr_misses::cpu.data 1262 # number of overall MSHR misses 949system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 44298 # number of overall MSHR misses 950system.cpu.l2cache.overall_mshr_misses::total 46038 # number of overall MSHR misses 951system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32592250 # number of ReadReq MSHR miss cycles 952system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42691498 # number of ReadReq MSHR miss cycles 953system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75283748 # number of ReadReq MSHR miss cycles 954system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of HardPFReq MSHR miss cycles 955system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 669707182 # number of HardPFReq MSHR miss cycles 956system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles 957system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles 958system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34465750 # number of ReadExReq MSHR miss cycles 959system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34465750 # number of ReadExReq MSHR miss cycles 960system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32592250 # number of demand (read+write) MSHR miss cycles 961system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77157248 # number of demand (read+write) MSHR miss cycles 962system.cpu.l2cache.demand_mshr_miss_latency::total 109749498 # number of demand (read+write) MSHR miss cycles 963system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32592250 # number of overall MSHR miss cycles 964system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77157248 # number of overall MSHR miss cycles 965system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of overall MSHR miss cycles 966system.cpu.l2cache.overall_mshr_miss_latency::total 779456680 # number of overall MSHR miss cycles 967system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for ReadReq accesses 968system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000523 # mshr miss rate for ReadReq accesses 969system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses 970system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 971system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 972system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 973system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 974system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.002608 # mshr miss rate for ReadExReq accesses 975system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.002608 # mshr miss rate for ReadExReq accesses 976system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for demand accesses 977system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for demand accesses 978system.cpu.l2cache.demand_mshr_miss_rate::total 0.000774 # mshr miss rate for demand accesses 979system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for overall accesses 980system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for overall accesses 981system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 982system.cpu.l2cache.overall_mshr_miss_rate::total 0.020468 # mshr miss rate for overall accesses 983system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68184.623431 # average ReadReq mshr miss latency 984system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62141.918486 # average ReadReq mshr miss latency 985system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64621.242918 # average ReadReq mshr miss latency 986system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average HardPFReq mshr miss latency 987system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 15118.226150 # average HardPFReq mshr miss latency 988system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 989system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency 990system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59940.434783 # average ReadExReq mshr miss latency 991system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59940.434783 # average ReadExReq mshr miss latency 992system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency 993system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency 994system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63074.424138 # average overall mshr miss latency 995system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency 996system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency 997system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average overall mshr miss latency 998system.cpu.l2cache.overall_avg_mshr_miss_latency::total 16930.724184 # average overall mshr miss latency 999system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1000system.cpu.dcache.tags.replacements 1533746 # number of replacements 1001system.cpu.dcache.tags.tagsinuse 511.875745 # Cycle average of tags in use 1002system.cpu.dcache.tags.total_refs 163803379 # Total number of references to valid blocks. 1003system.cpu.dcache.tags.sampled_refs 1534258 # Sample count of references to valid blocks. 1004system.cpu.dcache.tags.avg_refs 106.763907 # Average number of references to valid blocks. 1005system.cpu.dcache.tags.warmup_cycle 61007500 # Cycle when the warmup percentage was hit. 1006system.cpu.dcache.tags.occ_blocks::cpu.data 511.875745 # Average occupied blocks per requestor 1007system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy 1008system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy | 677system.cpu.dcache.tags.replacements 1533739 # number of replacements 678system.cpu.dcache.tags.tagsinuse 511.852624 # Cycle average of tags in use 679system.cpu.dcache.tags.total_refs 163803903 # Total number of references to valid blocks. 680system.cpu.dcache.tags.sampled_refs 1534251 # Sample count of references to valid blocks. 681system.cpu.dcache.tags.avg_refs 106.764736 # Average number of references to valid blocks. 682system.cpu.dcache.tags.warmup_cycle 77087500 # Cycle when the warmup percentage was hit. 683system.cpu.dcache.tags.occ_blocks::cpu.data 511.852624 # Average occupied blocks per requestor 684system.cpu.dcache.tags.occ_percent::cpu.data 0.999712 # Average percentage of cache occupancy 685system.cpu.dcache.tags.occ_percent::total 0.999712 # Average percentage of cache occupancy |
| 1009system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 686system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1010system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 1011system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id 1012system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id | 687system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 688system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 689system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id |
| 1013system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 1014system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 690system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 691system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1015system.cpu.dcache.tags.tag_accesses 336684382 # Number of tag accesses 1016system.cpu.dcache.tags.data_accesses 336684382 # Number of data accesses 1017system.cpu.dcache.ReadReq_hits::cpu.data 82726080 # number of ReadReq hits 1018system.cpu.dcache.ReadReq_hits::total 82726080 # number of ReadReq hits 1019system.cpu.dcache.WriteReq_hits::cpu.data 80985064 # number of WriteReq hits 1020system.cpu.dcache.WriteReq_hits::total 80985064 # number of WriteReq hits | 692system.cpu.dcache.tags.tag_accesses 336684823 # Number of tag accesses 693system.cpu.dcache.tags.data_accesses 336684823 # Number of data accesses 694system.cpu.dcache.ReadReq_hits::cpu.data 82726313 # number of ReadReq hits 695system.cpu.dcache.ReadReq_hits::total 82726313 # number of ReadReq hits 696system.cpu.dcache.WriteReq_hits::cpu.data 80985354 # number of WriteReq hits 697system.cpu.dcache.WriteReq_hits::total 80985354 # number of WriteReq hits |
| 1021system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits 1022system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits | 698system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits 699system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits |
| 1023system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits 1024system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits | 700system.cpu.dcache.LoadLockedReq_hits::cpu.data 10910 # number of LoadLockedReq hits 701system.cpu.dcache.LoadLockedReq_hits::total 10910 # number of LoadLockedReq hits |
| 1025system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 1026system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits | 702system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 703system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits |
| 1027system.cpu.dcache.demand_hits::cpu.data 163711144 # number of demand (read+write) hits 1028system.cpu.dcache.demand_hits::total 163711144 # number of demand (read+write) hits 1029system.cpu.dcache.overall_hits::cpu.data 163781573 # number of overall hits 1030system.cpu.dcache.overall_hits::total 163781573 # number of overall hits 1031system.cpu.dcache.ReadReq_misses::cpu.data 2704026 # number of ReadReq misses 1032system.cpu.dcache.ReadReq_misses::total 2704026 # number of ReadReq misses 1033system.cpu.dcache.WriteReq_misses::cpu.data 1067635 # number of WriteReq misses 1034system.cpu.dcache.WriteReq_misses::total 1067635 # number of WriteReq misses | 704system.cpu.dcache.demand_hits::cpu.data 163711667 # number of demand (read+write) hits 705system.cpu.dcache.demand_hits::total 163711667 # number of demand (read+write) hits 706system.cpu.dcache.overall_hits::cpu.data 163782096 # number of overall hits 707system.cpu.dcache.overall_hits::total 163782096 # number of overall hits 708system.cpu.dcache.ReadReq_misses::cpu.data 2704016 # number of ReadReq misses 709system.cpu.dcache.ReadReq_misses::total 2704016 # number of ReadReq misses 710system.cpu.dcache.WriteReq_misses::cpu.data 1067345 # number of WriteReq misses 711system.cpu.dcache.WriteReq_misses::total 1067345 # number of WriteReq misses |
| 1035system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses 1036system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses 1037system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses 1038system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses | 712system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses 713system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses 714system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses 715system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses |
| 1039system.cpu.dcache.demand_misses::cpu.data 3771661 # number of demand (read+write) misses 1040system.cpu.dcache.demand_misses::total 3771661 # number of demand (read+write) misses 1041system.cpu.dcache.overall_misses::cpu.data 3771680 # number of overall misses 1042system.cpu.dcache.overall_misses::total 3771680 # number of overall misses 1043system.cpu.dcache.ReadReq_miss_latency::cpu.data 21403617484 # number of ReadReq miss cycles 1044system.cpu.dcache.ReadReq_miss_latency::total 21403617484 # number of ReadReq miss cycles 1045system.cpu.dcache.WriteReq_miss_latency::cpu.data 8344449821 # number of WriteReq miss cycles 1046system.cpu.dcache.WriteReq_miss_latency::total 8344449821 # number of WriteReq miss cycles 1047system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 164500 # number of LoadLockedReq miss cycles 1048system.cpu.dcache.LoadLockedReq_miss_latency::total 164500 # number of LoadLockedReq miss cycles 1049system.cpu.dcache.demand_miss_latency::cpu.data 29748067305 # number of demand (read+write) miss cycles 1050system.cpu.dcache.demand_miss_latency::total 29748067305 # number of demand (read+write) miss cycles 1051system.cpu.dcache.overall_miss_latency::cpu.data 29748067305 # number of overall miss cycles 1052system.cpu.dcache.overall_miss_latency::total 29748067305 # number of overall miss cycles 1053system.cpu.dcache.ReadReq_accesses::cpu.data 85430106 # number of ReadReq accesses(hits+misses) 1054system.cpu.dcache.ReadReq_accesses::total 85430106 # number of ReadReq accesses(hits+misses) | 716system.cpu.dcache.demand_misses::cpu.data 3771361 # number of demand (read+write) misses 717system.cpu.dcache.demand_misses::total 3771361 # number of demand (read+write) misses 718system.cpu.dcache.overall_misses::cpu.data 3771380 # number of overall misses 719system.cpu.dcache.overall_misses::total 3771380 # number of overall misses 720system.cpu.dcache.ReadReq_miss_latency::cpu.data 21429430210 # number of ReadReq miss cycles 721system.cpu.dcache.ReadReq_miss_latency::total 21429430210 # number of ReadReq miss cycles 722system.cpu.dcache.WriteReq_miss_latency::cpu.data 8382362067 # number of WriteReq miss cycles 723system.cpu.dcache.WriteReq_miss_latency::total 8382362067 # number of WriteReq miss cycles 724system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 174750 # number of LoadLockedReq miss cycles 725system.cpu.dcache.LoadLockedReq_miss_latency::total 174750 # number of LoadLockedReq miss cycles 726system.cpu.dcache.demand_miss_latency::cpu.data 29811792277 # number of demand (read+write) miss cycles 727system.cpu.dcache.demand_miss_latency::total 29811792277 # number of demand (read+write) miss cycles 728system.cpu.dcache.overall_miss_latency::cpu.data 29811792277 # number of overall miss cycles 729system.cpu.dcache.overall_miss_latency::total 29811792277 # number of overall miss cycles 730system.cpu.dcache.ReadReq_accesses::cpu.data 85430329 # number of ReadReq accesses(hits+misses) 731system.cpu.dcache.ReadReq_accesses::total 85430329 # number of ReadReq accesses(hits+misses) |
| 1055system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 1056system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) 1057system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) 1058system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) | 732system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 733system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) 734system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) 735system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) |
| 1059system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) 1060system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) | 736system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10915 # number of LoadLockedReq accesses(hits+misses) 737system.cpu.dcache.LoadLockedReq_accesses::total 10915 # number of LoadLockedReq accesses(hits+misses) |
| 1061system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 1062system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) | 738system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 739system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) |
| 1063system.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses 1064system.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses 1065system.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses 1066system.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses | 740system.cpu.dcache.demand_accesses::cpu.data 167483028 # number of demand (read+write) accesses 741system.cpu.dcache.demand_accesses::total 167483028 # number of demand (read+write) accesses 742system.cpu.dcache.overall_accesses::cpu.data 167553476 # number of overall (read+write) accesses 743system.cpu.dcache.overall_accesses::total 167553476 # number of overall (read+write) accesses |
| 1067system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses 1068system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses | 744system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses 745system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses |
| 1069system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses 1070system.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses | 746system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013008 # miss rate for WriteReq accesses 747system.cpu.dcache.WriteReq_miss_rate::total 0.013008 # miss rate for WriteReq accesses |
| 1071system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses 1072system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses 1073system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses 1074system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses | 748system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses 749system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses 750system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses 751system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses |
| 1075system.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses 1076system.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses 1077system.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses 1078system.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses 1079system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency 1080system.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency 1081system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency 1082system.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency 1083system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency 1084system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency 1085system.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency 1086system.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency 1087system.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency 1088system.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency 1089system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked 1090system.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked 1091system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 1092system.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked 1093system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked 1094system.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked | 752system.cpu.dcache.demand_miss_rate::cpu.data 0.022518 # miss rate for demand accesses 753system.cpu.dcache.demand_miss_rate::total 0.022518 # miss rate for demand accesses 754system.cpu.dcache.overall_miss_rate::cpu.data 0.022509 # miss rate for overall accesses 755system.cpu.dcache.overall_miss_rate::total 0.022509 # miss rate for overall accesses 756system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7925.038243 # average ReadReq miss latency 757system.cpu.dcache.ReadReq_avg_miss_latency::total 7925.038243 # average ReadReq miss latency 758system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7853.470122 # average WriteReq miss latency 759system.cpu.dcache.WriteReq_avg_miss_latency::total 7853.470122 # average WriteReq miss latency 760system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34950 # average LoadLockedReq miss latency 761system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34950 # average LoadLockedReq miss latency 762system.cpu.dcache.demand_avg_miss_latency::cpu.data 7904.783519 # average overall miss latency 763system.cpu.dcache.demand_avg_miss_latency::total 7904.783519 # average overall miss latency 764system.cpu.dcache.overall_avg_miss_latency::cpu.data 7904.743695 # average overall miss latency 765system.cpu.dcache.overall_avg_miss_latency::total 7904.743695 # average overall miss latency 766system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 767system.cpu.dcache.blocked_cycles::no_targets 768686 # number of cycles access was blocked 768system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 769system.cpu.dcache.blocked::no_targets 111802 # number of cycles access was blocked 770system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 771system.cpu.dcache.avg_blocked_cycles::no_targets 6.875423 # average number of cycles each access was blocked |
| 1095system.cpu.dcache.fast_writes 0 # number of fast writes performed 1096system.cpu.dcache.cache_copies 0 # number of cache copies performed | 772system.cpu.dcache.fast_writes 0 # number of fast writes performed 773system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1097system.cpu.dcache.writebacks::writebacks 966282 # number of writebacks 1098system.cpu.dcache.writebacks::total 966282 # number of writebacks 1099system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits 1100system.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits 1101system.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits 1102system.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits | 774system.cpu.dcache.writebacks::writebacks 966281 # number of writebacks 775system.cpu.dcache.writebacks::total 966281 # number of writebacks 776system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390263 # number of ReadReq MSHR hits 777system.cpu.dcache.ReadReq_mshr_hits::total 1390263 # number of ReadReq MSHR hits 778system.cpu.dcache.WriteReq_mshr_hits::cpu.data 846856 # number of WriteReq MSHR hits 779system.cpu.dcache.WriteReq_mshr_hits::total 846856 # number of WriteReq MSHR hits |
| 1103system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits 1104system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits | 780system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits 781system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits |
| 1105system.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits 1106system.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits 1107system.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits 1108system.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits 1109system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses 1110system.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses 1111system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses 1112system.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses | 782system.cpu.dcache.demand_mshr_hits::cpu.data 2237119 # number of demand (read+write) MSHR hits 783system.cpu.dcache.demand_mshr_hits::total 2237119 # number of demand (read+write) MSHR hits 784system.cpu.dcache.overall_mshr_hits::cpu.data 2237119 # number of overall MSHR hits 785system.cpu.dcache.overall_mshr_hits::total 2237119 # number of overall MSHR hits 786system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313753 # number of ReadReq MSHR misses 787system.cpu.dcache.ReadReq_mshr_misses::total 1313753 # number of ReadReq MSHR misses 788system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220489 # number of WriteReq MSHR misses 789system.cpu.dcache.WriteReq_mshr_misses::total 220489 # number of WriteReq MSHR misses |
| 1113system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 1114system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses | 790system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 791system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses |
| 1115system.cpu.dcache.demand_mshr_misses::cpu.data 1534249 # number of demand (read+write) MSHR misses 1116system.cpu.dcache.demand_mshr_misses::total 1534249 # number of demand (read+write) MSHR misses 1117system.cpu.dcache.overall_mshr_misses::cpu.data 1534260 # number of overall MSHR misses 1118system.cpu.dcache.overall_mshr_misses::total 1534260 # number of overall MSHR misses 1119system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9295842016 # number of ReadReq MSHR miss cycles 1120system.cpu.dcache.ReadReq_mshr_miss_latency::total 9295842016 # number of ReadReq MSHR miss cycles 1121system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles 1122system.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles 1123system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles 1124system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles 1125system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles 1126system.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles 1127system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles 1128system.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles | 792system.cpu.dcache.demand_mshr_misses::cpu.data 1534242 # number of demand (read+write) MSHR misses 793system.cpu.dcache.demand_mshr_misses::total 1534242 # number of demand (read+write) MSHR misses 794system.cpu.dcache.overall_mshr_misses::cpu.data 1534253 # number of overall MSHR misses 795system.cpu.dcache.overall_mshr_misses::total 1534253 # number of overall MSHR misses 796system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9313835285 # number of ReadReq MSHR miss cycles 797system.cpu.dcache.ReadReq_mshr_miss_latency::total 9313835285 # number of ReadReq MSHR miss cycles 798system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1599508327 # number of WriteReq MSHR miss cycles 799system.cpu.dcache.WriteReq_mshr_miss_latency::total 1599508327 # number of WriteReq MSHR miss cycles 800system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 613250 # number of SoftPFReq MSHR miss cycles 801system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 613250 # number of SoftPFReq MSHR miss cycles 802system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10913343612 # number of demand (read+write) MSHR miss cycles 803system.cpu.dcache.demand_mshr_miss_latency::total 10913343612 # number of demand (read+write) MSHR miss cycles 804system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10913956862 # number of overall MSHR miss cycles 805system.cpu.dcache.overall_mshr_miss_latency::total 10913956862 # number of overall MSHR miss cycles |
| 1129system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses 1130system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses 1131system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses 1132system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses 1133system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses 1134system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses 1135system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses 1136system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses 1137system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses 1138system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses | 806system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses 807system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses 808system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses 809system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses 810system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses 811system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses 812system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses 813system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses 814system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses 815system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses |
| 1139system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7075.748189 # average ReadReq mshr miss latency 1140system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7075.748189 # average ReadReq mshr miss latency 1141system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7220.442428 # average WriteReq mshr miss latency 1142system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7220.442428 # average WriteReq mshr miss latency 1143system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58022.727273 # average SoftPFReq mshr miss latency 1144system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58022.727273 # average SoftPFReq mshr miss latency 1145system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7096.542299 # average overall mshr miss latency 1146system.cpu.dcache.demand_avg_mshr_miss_latency::total 7096.542299 # average overall mshr miss latency 1147system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7096.907419 # average overall mshr miss latency 1148system.cpu.dcache.overall_avg_mshr_miss_latency::total 7096.907419 # average overall mshr miss latency | 816system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7089.487358 # average ReadReq mshr miss latency 817system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7089.487358 # average ReadReq mshr miss latency 818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7254.367914 # average WriteReq mshr miss latency 819system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7254.367914 # average WriteReq mshr miss latency 820system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 55750 # average SoftPFReq mshr miss latency 821system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 55750 # average SoftPFReq mshr miss latency 822system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7113.182674 # average overall mshr miss latency 823system.cpu.dcache.demand_avg_mshr_miss_latency::total 7113.182674 # average overall mshr miss latency 824system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7113.531381 # average overall mshr miss latency 825system.cpu.dcache.overall_avg_mshr_miss_latency::total 7113.531381 # average overall mshr miss latency |
| 1149system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 826system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 827system.cpu.icache.tags.replacements 715275 # number of replacements 828system.cpu.icache.tags.tagsinuse 511.840362 # Cycle average of tags in use 829system.cpu.icache.tags.total_refs 88389408 # Total number of references to valid blocks. 830system.cpu.icache.tags.sampled_refs 715787 # Sample count of references to valid blocks. 831system.cpu.icache.tags.avg_refs 123.485629 # Average number of references to valid blocks. 832system.cpu.icache.tags.warmup_cycle 315060000 # Cycle when the warmup percentage was hit. 833system.cpu.icache.tags.occ_blocks::cpu.inst 511.840362 # Average occupied blocks per requestor 834system.cpu.icache.tags.occ_percent::cpu.inst 0.999688 # Average percentage of cache occupancy 835system.cpu.icache.tags.occ_percent::total 0.999688 # Average percentage of cache occupancy 836system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id 840system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 841system.cpu.icache.tags.age_task_id_blocks_1024::4 68 # Occupied blocks per task id 842system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 843system.cpu.icache.tags.tag_accesses 178935006 # Number of tag accesses 844system.cpu.icache.tags.data_accesses 178935006 # Number of data accesses 845system.cpu.icache.ReadReq_hits::cpu.inst 88389408 # number of ReadReq hits 846system.cpu.icache.ReadReq_hits::total 88389408 # number of ReadReq hits 847system.cpu.icache.demand_hits::cpu.inst 88389408 # number of demand (read+write) hits 848system.cpu.icache.demand_hits::total 88389408 # number of demand (read+write) hits 849system.cpu.icache.overall_hits::cpu.inst 88389408 # number of overall hits 850system.cpu.icache.overall_hits::total 88389408 # number of overall hits 851system.cpu.icache.ReadReq_misses::cpu.inst 720201 # number of ReadReq misses 852system.cpu.icache.ReadReq_misses::total 720201 # number of ReadReq misses 853system.cpu.icache.demand_misses::cpu.inst 720201 # number of demand (read+write) misses 854system.cpu.icache.demand_misses::total 720201 # number of demand (read+write) misses 855system.cpu.icache.overall_misses::cpu.inst 720201 # number of overall misses 856system.cpu.icache.overall_misses::total 720201 # number of overall misses 857system.cpu.icache.ReadReq_miss_latency::cpu.inst 5943843584 # number of ReadReq miss cycles 858system.cpu.icache.ReadReq_miss_latency::total 5943843584 # number of ReadReq miss cycles 859system.cpu.icache.demand_miss_latency::cpu.inst 5943843584 # number of demand (read+write) miss cycles 860system.cpu.icache.demand_miss_latency::total 5943843584 # number of demand (read+write) miss cycles 861system.cpu.icache.overall_miss_latency::cpu.inst 5943843584 # number of overall miss cycles 862system.cpu.icache.overall_miss_latency::total 5943843584 # number of overall miss cycles 863system.cpu.icache.ReadReq_accesses::cpu.inst 89109609 # number of ReadReq accesses(hits+misses) 864system.cpu.icache.ReadReq_accesses::total 89109609 # number of ReadReq accesses(hits+misses) 865system.cpu.icache.demand_accesses::cpu.inst 89109609 # number of demand (read+write) accesses 866system.cpu.icache.demand_accesses::total 89109609 # number of demand (read+write) accesses 867system.cpu.icache.overall_accesses::cpu.inst 89109609 # number of overall (read+write) accesses 868system.cpu.icache.overall_accesses::total 89109609 # number of overall (read+write) accesses 869system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008082 # miss rate for ReadReq accesses 870system.cpu.icache.ReadReq_miss_rate::total 0.008082 # miss rate for ReadReq accesses 871system.cpu.icache.demand_miss_rate::cpu.inst 0.008082 # miss rate for demand accesses 872system.cpu.icache.demand_miss_rate::total 0.008082 # miss rate for demand accesses 873system.cpu.icache.overall_miss_rate::cpu.inst 0.008082 # miss rate for overall accesses 874system.cpu.icache.overall_miss_rate::total 0.008082 # miss rate for overall accesses 875system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8253.034339 # average ReadReq miss latency 876system.cpu.icache.ReadReq_avg_miss_latency::total 8253.034339 # average ReadReq miss latency 877system.cpu.icache.demand_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency 878system.cpu.icache.demand_avg_miss_latency::total 8253.034339 # average overall miss latency 879system.cpu.icache.overall_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency 880system.cpu.icache.overall_avg_miss_latency::total 8253.034339 # average overall miss latency 881system.cpu.icache.blocked_cycles::no_mshrs 51882 # number of cycles access was blocked 882system.cpu.icache.blocked_cycles::no_targets 52 # number of cycles access was blocked 883system.cpu.icache.blocked::no_mshrs 1935 # number of cycles access was blocked 884system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 885system.cpu.icache.avg_blocked_cycles::no_mshrs 26.812403 # average number of cycles each access was blocked 886system.cpu.icache.avg_blocked_cycles::no_targets 17.333333 # average number of cycles each access was blocked 887system.cpu.icache.fast_writes 0 # number of fast writes performed 888system.cpu.icache.cache_copies 0 # number of cache copies performed 889system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4413 # number of ReadReq MSHR hits 890system.cpu.icache.ReadReq_mshr_hits::total 4413 # number of ReadReq MSHR hits 891system.cpu.icache.demand_mshr_hits::cpu.inst 4413 # number of demand (read+write) MSHR hits 892system.cpu.icache.demand_mshr_hits::total 4413 # number of demand (read+write) MSHR hits 893system.cpu.icache.overall_mshr_hits::cpu.inst 4413 # number of overall MSHR hits 894system.cpu.icache.overall_mshr_hits::total 4413 # number of overall MSHR hits 895system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715788 # number of ReadReq MSHR misses 896system.cpu.icache.ReadReq_mshr_misses::total 715788 # number of ReadReq MSHR misses 897system.cpu.icache.demand_mshr_misses::cpu.inst 715788 # number of demand (read+write) MSHR misses 898system.cpu.icache.demand_mshr_misses::total 715788 # number of demand (read+write) MSHR misses 899system.cpu.icache.overall_mshr_misses::cpu.inst 715788 # number of overall MSHR misses 900system.cpu.icache.overall_mshr_misses::total 715788 # number of overall MSHR misses 901system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4812391061 # number of ReadReq MSHR miss cycles 902system.cpu.icache.ReadReq_mshr_miss_latency::total 4812391061 # number of ReadReq MSHR miss cycles 903system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4812391061 # number of demand (read+write) MSHR miss cycles 904system.cpu.icache.demand_mshr_miss_latency::total 4812391061 # number of demand (read+write) MSHR miss cycles 905system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4812391061 # number of overall MSHR miss cycles 906system.cpu.icache.overall_mshr_miss_latency::total 4812391061 # number of overall MSHR miss cycles 907system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for ReadReq accesses 908system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008033 # mshr miss rate for ReadReq accesses 909system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for demand accesses 910system.cpu.icache.demand_mshr_miss_rate::total 0.008033 # mshr miss rate for demand accesses 911system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for overall accesses 912system.cpu.icache.overall_mshr_miss_rate::total 0.008033 # mshr miss rate for overall accesses 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6723.207236 # average ReadReq mshr miss latency 914system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6723.207236 # average ReadReq mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6723.207236 # average overall mshr miss latency 916system.cpu.icache.demand_avg_mshr_miss_latency::total 6723.207236 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6723.207236 # average overall mshr miss latency 918system.cpu.icache.overall_avg_mshr_miss_latency::total 6723.207236 # average overall mshr miss latency 919system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 920system.cpu.l2cache.prefetcher.num_hwpf_issued 406270 # number of hwpf issued 921system.cpu.l2cache.prefetcher.pfIdentified 406521 # number of prefetch candidates identified 922system.cpu.l2cache.prefetcher.pfBufferHit 191 # number of redundant prefetches already in prefetch queue 923system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 924system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 925system.cpu.l2cache.prefetcher.pfSpanPage 28111 # number of prefetches not generated due to page crossing 926system.cpu.l2cache.tags.replacements 0 # number of replacements 927system.cpu.l2cache.tags.tagsinuse 5993.755359 # Cycle average of tags in use 928system.cpu.l2cache.tags.total_refs 2805980 # Total number of references to valid blocks. 929system.cpu.l2cache.tags.sampled_refs 7304 # Sample count of references to valid blocks. 930system.cpu.l2cache.tags.avg_refs 384.170318 # Average number of references to valid blocks. 931system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 932system.cpu.l2cache.tags.occ_blocks::writebacks 2575.357550 # Average occupied blocks per requestor 933system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.182450 # Average occupied blocks per requestor 934system.cpu.l2cache.tags.occ_blocks::cpu.data 614.569855 # Average occupied blocks per requestor 935system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 123.645504 # Average occupied blocks per requestor 936system.cpu.l2cache.tags.occ_percent::writebacks 0.157187 # Average percentage of cache occupancy 937system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163585 # Average percentage of cache occupancy 938system.cpu.l2cache.tags.occ_percent::cpu.data 0.037510 # Average percentage of cache occupancy 939system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007547 # Average percentage of cache occupancy 940system.cpu.l2cache.tags.occ_percent::total 0.365830 # Average percentage of cache occupancy 941system.cpu.l2cache.tags.occ_task_id_blocks::1022 515 # Occupied blocks per task id 942system.cpu.l2cache.tags.occ_task_id_blocks::1024 6789 # Occupied blocks per task id 943system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id 944system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id 945system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id 946system.cpu.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id 947system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 948system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id 949system.cpu.l2cache.tags.age_task_id_blocks_1024::2 775 # Occupied blocks per task id 950system.cpu.l2cache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id 951system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5746 # Occupied blocks per task id 952system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031433 # Percentage of cache occupancy per task id 953system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414368 # Percentage of cache occupancy per task id 954system.cpu.l2cache.tags.tag_accesses 51674481 # Number of tag accesses 955system.cpu.l2cache.tags.data_accesses 51674481 # Number of data accesses 956system.cpu.l2cache.ReadReq_hits::cpu.inst 711950 # number of ReadReq hits 957system.cpu.l2cache.ReadReq_hits::cpu.data 1312705 # number of ReadReq hits 958system.cpu.l2cache.ReadReq_hits::total 2024655 # number of ReadReq hits 959system.cpu.l2cache.Writeback_hits::writebacks 966281 # number of Writeback hits 960system.cpu.l2cache.Writeback_hits::total 966281 # number of Writeback hits 961system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 962system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 963system.cpu.l2cache.ReadExReq_hits::cpu.data 219662 # number of ReadExReq hits 964system.cpu.l2cache.ReadExReq_hits::total 219662 # number of ReadExReq hits 965system.cpu.l2cache.demand_hits::cpu.inst 711950 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.data 1532367 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::total 2244317 # number of demand (read+write) hits 968system.cpu.l2cache.overall_hits::cpu.inst 711950 # number of overall hits 969system.cpu.l2cache.overall_hits::cpu.data 1532367 # number of overall hits 970system.cpu.l2cache.overall_hits::total 2244317 # number of overall hits 971system.cpu.l2cache.ReadReq_misses::cpu.inst 2934 # number of ReadReq misses 972system.cpu.l2cache.ReadReq_misses::cpu.data 1059 # number of ReadReq misses 973system.cpu.l2cache.ReadReq_misses::total 3993 # number of ReadReq misses 974system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 975system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 976system.cpu.l2cache.ReadExReq_misses::cpu.data 825 # number of ReadExReq misses 977system.cpu.l2cache.ReadExReq_misses::total 825 # number of ReadExReq misses 978system.cpu.l2cache.demand_misses::cpu.inst 2934 # number of demand (read+write) misses 979system.cpu.l2cache.demand_misses::cpu.data 1884 # number of demand (read+write) misses 980system.cpu.l2cache.demand_misses::total 4818 # number of demand (read+write) misses 981system.cpu.l2cache.overall_misses::cpu.inst 2934 # number of overall misses 982system.cpu.l2cache.overall_misses::cpu.data 1884 # number of overall misses 983system.cpu.l2cache.overall_misses::total 4818 # number of overall misses 984system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 179619250 # number of ReadReq miss cycles 985system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70145000 # number of ReadReq miss cycles 986system.cpu.l2cache.ReadReq_miss_latency::total 249764250 # number of ReadReq miss cycles 987system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles 988system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles 989system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 50824468 # number of ReadExReq miss cycles 990system.cpu.l2cache.ReadExReq_miss_latency::total 50824468 # number of ReadExReq miss cycles 991system.cpu.l2cache.demand_miss_latency::cpu.inst 179619250 # number of demand (read+write) miss cycles 992system.cpu.l2cache.demand_miss_latency::cpu.data 120969468 # number of demand (read+write) miss cycles 993system.cpu.l2cache.demand_miss_latency::total 300588718 # number of demand (read+write) miss cycles 994system.cpu.l2cache.overall_miss_latency::cpu.inst 179619250 # number of overall miss cycles 995system.cpu.l2cache.overall_miss_latency::cpu.data 120969468 # number of overall miss cycles 996system.cpu.l2cache.overall_miss_latency::total 300588718 # number of overall miss cycles 997system.cpu.l2cache.ReadReq_accesses::cpu.inst 714884 # number of ReadReq accesses(hits+misses) 998system.cpu.l2cache.ReadReq_accesses::cpu.data 1313764 # number of ReadReq accesses(hits+misses) 999system.cpu.l2cache.ReadReq_accesses::total 2028648 # number of ReadReq accesses(hits+misses) 1000system.cpu.l2cache.Writeback_accesses::writebacks 966281 # number of Writeback accesses(hits+misses) 1001system.cpu.l2cache.Writeback_accesses::total 966281 # number of Writeback accesses(hits+misses) 1002system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 1003system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 1004system.cpu.l2cache.ReadExReq_accesses::cpu.data 220487 # number of ReadExReq accesses(hits+misses) 1005system.cpu.l2cache.ReadExReq_accesses::total 220487 # number of ReadExReq accesses(hits+misses) 1006system.cpu.l2cache.demand_accesses::cpu.inst 714884 # number of demand (read+write) accesses 1007system.cpu.l2cache.demand_accesses::cpu.data 1534251 # number of demand (read+write) accesses 1008system.cpu.l2cache.demand_accesses::total 2249135 # number of demand (read+write) accesses 1009system.cpu.l2cache.overall_accesses::cpu.inst 714884 # number of overall (read+write) accesses 1010system.cpu.l2cache.overall_accesses::cpu.data 1534251 # number of overall (read+write) accesses 1011system.cpu.l2cache.overall_accesses::total 2249135 # number of overall (read+write) accesses 1012system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004104 # miss rate for ReadReq accesses 1013system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000806 # miss rate for ReadReq accesses 1014system.cpu.l2cache.ReadReq_miss_rate::total 0.001968 # miss rate for ReadReq accesses 1015system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses 1016system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses 1017system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003742 # miss rate for ReadExReq accesses 1018system.cpu.l2cache.ReadExReq_miss_rate::total 0.003742 # miss rate for ReadExReq accesses 1019system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004104 # miss rate for demand accesses 1020system.cpu.l2cache.demand_miss_rate::cpu.data 0.001228 # miss rate for demand accesses 1021system.cpu.l2cache.demand_miss_rate::total 0.002142 # miss rate for demand accesses 1022system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004104 # miss rate for overall accesses 1023system.cpu.l2cache.overall_miss_rate::cpu.data 0.001228 # miss rate for overall accesses 1024system.cpu.l2cache.overall_miss_rate::total 0.002142 # miss rate for overall accesses 1025system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61219.921609 # average ReadReq miss latency 1026system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66237.016053 # average ReadReq miss latency 1027system.cpu.l2cache.ReadReq_avg_miss_latency::total 62550.525920 # average ReadReq miss latency 1028system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency 1029system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency 1030system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61605.415758 # average ReadExReq miss latency 1031system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61605.415758 # average ReadExReq miss latency 1032system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency 1033system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency 1034system.cpu.l2cache.demand_avg_miss_latency::total 62388.691988 # average overall miss latency 1035system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency 1036system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency 1037system.cpu.l2cache.overall_avg_miss_latency::total 62388.691988 # average overall miss latency 1038system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1039system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1040system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1041system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1042system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1043system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1044system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1045system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1046system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 1047system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits 1048system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits 1049system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 98 # number of ReadExReq MSHR hits 1050system.cpu.l2cache.ReadExReq_mshr_hits::total 98 # number of ReadExReq MSHR hits 1051system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 1052system.cpu.l2cache.demand_mshr_hits::cpu.data 131 # number of demand (read+write) MSHR hits 1053system.cpu.l2cache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits 1054system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 1055system.cpu.l2cache.overall_mshr_hits::cpu.data 131 # number of overall MSHR hits 1056system.cpu.l2cache.overall_mshr_hits::total 142 # number of overall MSHR hits 1057system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2923 # number of ReadReq MSHR misses 1058system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1026 # number of ReadReq MSHR misses 1059system.cpu.l2cache.ReadReq_mshr_misses::total 3949 # number of ReadReq MSHR misses 1060system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30530 # number of HardPFReq MSHR misses 1061system.cpu.l2cache.HardPFReq_mshr_misses::total 30530 # number of HardPFReq MSHR misses 1062system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 1063system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 1064system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 727 # number of ReadExReq MSHR misses 1065system.cpu.l2cache.ReadExReq_mshr_misses::total 727 # number of ReadExReq MSHR misses 1066system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses 1067system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses 1068system.cpu.l2cache.demand_mshr_misses::total 4676 # number of demand (read+write) MSHR misses 1069system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses 1070system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses 1071system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30530 # number of overall MSHR misses 1072system.cpu.l2cache.overall_mshr_misses::total 35206 # number of overall MSHR misses 1073system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 153898250 # number of ReadReq MSHR miss cycles 1074system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59960500 # number of ReadReq MSHR miss cycles 1075system.cpu.l2cache.ReadReq_mshr_miss_latency::total 213858750 # number of ReadReq MSHR miss cycles 1076system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of HardPFReq MSHR miss cycles 1077system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 204942291 # number of HardPFReq MSHR miss cycles 1078system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles 1079system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles 1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41351500 # number of ReadExReq MSHR miss cycles 1081system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41351500 # number of ReadExReq MSHR miss cycles 1082system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 153898250 # number of demand (read+write) MSHR miss cycles 1083system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101312000 # number of demand (read+write) MSHR miss cycles 1084system.cpu.l2cache.demand_mshr_miss_latency::total 255210250 # number of demand (read+write) MSHR miss cycles 1085system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 153898250 # number of overall MSHR miss cycles 1086system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101312000 # number of overall MSHR miss cycles 1087system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of overall MSHR miss cycles 1088system.cpu.l2cache.overall_mshr_miss_latency::total 460152541 # number of overall MSHR miss cycles 1089system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for ReadReq accesses 1090system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadReq accesses 1091system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001947 # mshr miss rate for ReadReq accesses 1092system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1093system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1094system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 1095system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 1096system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003297 # mshr miss rate for ReadExReq accesses 1097system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003297 # mshr miss rate for ReadExReq accesses 1098system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for demand accesses 1099system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for demand accesses 1100system.cpu.l2cache.demand_mshr_miss_rate::total 0.002079 # mshr miss rate for demand accesses 1101system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for overall accesses 1102system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for overall accesses 1103system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1104system.cpu.l2cache.overall_mshr_miss_rate::total 0.015653 # mshr miss rate for overall accesses 1105system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52650.786863 # average ReadReq mshr miss latency 1106system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58441.033138 # average ReadReq mshr miss latency 1107system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54155.165865 # average ReadReq mshr miss latency 1108system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average HardPFReq mshr miss latency 1109system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6712.816607 # average HardPFReq mshr miss latency 1110system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 1111system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency 1112system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56879.642366 # average ReadExReq mshr miss latency 1113system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56879.642366 # average ReadExReq mshr miss latency 1114system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency 1115system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency 1116system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54578.753208 # average overall mshr miss latency 1117system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency 1118system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency 1119system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average overall mshr miss latency 1120system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13070.287479 # average overall mshr miss latency 1121system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1122system.cpu.toL2Bus.trans_dist::ReadReq 2029552 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::ReadResp 2029552 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::Writeback 966281 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::HardPFReq 32098 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 1127system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 1128system.cpu.toL2Bus.trans_dist::ReadExReq 220487 # Transaction distribution 1129system.cpu.toL2Bus.trans_dist::ReadExResp 220487 # Transaction distribution 1130system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430672 # Packet count per connected master and slave (bytes) 1131system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034787 # Packet count per connected master and slave (bytes) 1132system.cpu.toL2Bus.pkt_count::total 5465459 # Packet count per connected master and slave (bytes) 1133system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45752576 # Cumulative packet size per connected master and slave (bytes) 1134system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034048 # Cumulative packet size per connected master and slave (bytes) 1135system.cpu.toL2Bus.pkt_size::total 205786624 # Cumulative packet size per connected master and slave (bytes) 1136system.cpu.toL2Bus.snoops 33002 # Total snoops (count) 1137system.cpu.toL2Bus.snoop_fanout::samples 3248420 # Request fanout histogram 1138system.cpu.toL2Bus.snoop_fanout::mean 5.009881 # Request fanout histogram 1139system.cpu.toL2Bus.snoop_fanout::stdev 0.098911 # Request fanout histogram 1140system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1141system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1142system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1143system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1144system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1145system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1146system.cpu.toL2Bus.snoop_fanout::5 3216322 99.01% 99.01% # Request fanout histogram 1147system.cpu.toL2Bus.snoop_fanout::6 32098 0.99% 100.00% # Request fanout histogram 1148system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1149system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1150system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1151system.cpu.toL2Bus.snoop_fanout::total 3248420 # Request fanout histogram 1152system.cpu.toL2Bus.reqLayer0.occupancy 2574443497 # Layer occupancy (ticks) 1153system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) 1154system.cpu.toL2Bus.respLayer0.occupancy 1074521893 # Layer occupancy (ticks) 1155system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 1156system.cpu.toL2Bus.respLayer1.occupancy 2301598998 # Layer occupancy (ticks) 1157system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) 1158system.membus.trans_dist::ReadReq 6603 # Transaction distribution 1159system.membus.trans_dist::ReadResp 6603 # Transaction distribution 1160system.membus.trans_dist::UpgradeReq 1 # Transaction distribution 1161system.membus.trans_dist::UpgradeResp 1 # Transaction distribution 1162system.membus.trans_dist::ReadExReq 727 # Transaction distribution 1163system.membus.trans_dist::ReadExResp 727 # Transaction distribution 1164system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14662 # Packet count per connected master and slave (bytes) 1165system.membus.pkt_count::total 14662 # Packet count per connected master and slave (bytes) 1166system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469120 # Cumulative packet size per connected master and slave (bytes) 1167system.membus.pkt_size::total 469120 # Cumulative packet size per connected master and slave (bytes) 1168system.membus.snoops 0 # Total snoops (count) 1169system.membus.snoop_fanout::samples 7331 # Request fanout histogram 1170system.membus.snoop_fanout::mean 0 # Request fanout histogram 1171system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1172system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1173system.membus.snoop_fanout::0 7331 100.00% 100.00% # Request fanout histogram 1174system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1175system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1176system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1177system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1178system.membus.snoop_fanout::total 7331 # Request fanout histogram 1179system.membus.reqLayer0.occupancy 9338317 # Layer occupancy (ticks) 1180system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1181system.membus.respLayer1.occupancy 68128868 # Layer occupancy (ticks) 1182system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
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| 1150 1151---------- End Simulation Statistics ---------- | 1183 1184---------- End Simulation Statistics ---------- |