| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.071775 # Number of seconds simulated 4sim_ticks 71774859500 # Number of ticks simulated 5final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 120484 # Simulator instruction rate (inst/s) 8host_op_rate 154032 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 31671128 # Simulator tick rate (ticks/s) 10host_mem_usage 240520 # Number of bytes of host memory used 11host_seconds 2266.26 # Real time elapsed on the host |
| 12sim_insts 273048474 # Number of instructions simulated 13sim_ops 349076199 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 199168 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 273728 # Number of bytes read from this memory 16system.physmem.bytes_read::total 472896 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 199168 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 199168 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3112 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4277 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 7389 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2774899 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 3813703 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 6588602 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2774899 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2774899 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2774899 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 3813703 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 6588602 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 332 unchanged lines hidden (view full) --- 370system.cpu.icache.overall_miss_latency::total 211050500 # number of overall miss cycles 371system.cpu.icache.ReadReq_accesses::cpu.inst 39951299 # number of ReadReq accesses(hits+misses) 372system.cpu.icache.ReadReq_accesses::total 39951299 # number of ReadReq accesses(hits+misses) 373system.cpu.icache.demand_accesses::cpu.inst 39951299 # number of demand (read+write) accesses 374system.cpu.icache.demand_accesses::total 39951299 # number of demand (read+write) accesses 375system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses 376system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses 377system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses |
| 378system.cpu.icache.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses |
| 379system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses |
| 380system.cpu.icache.demand_miss_rate::total 0.000426 # miss rate for demand accesses |
| 381system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses |
| 382system.cpu.icache.overall_miss_rate::total 0.000426 # miss rate for overall accesses |
| 383system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency |
| 384system.cpu.icache.ReadReq_avg_miss_latency::total 12404.519807 # average ReadReq miss latency |
| 385system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency |
| 386system.cpu.icache.demand_avg_miss_latency::total 12404.519807 # average overall miss latency |
| 387system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency |
| 388system.cpu.icache.overall_avg_miss_latency::total 12404.519807 # average overall miss latency |
| 389system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.icache.fast_writes 0 # number of fast writes performed 396system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 408system.cpu.icache.overall_mshr_misses::total 16114 # number of overall MSHR misses 409system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139714000 # number of ReadReq MSHR miss cycles 410system.cpu.icache.ReadReq_mshr_miss_latency::total 139714000 # number of ReadReq MSHR miss cycles 411system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139714000 # number of demand (read+write) MSHR miss cycles 412system.cpu.icache.demand_mshr_miss_latency::total 139714000 # number of demand (read+write) MSHR miss cycles 413system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles 414system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses |
| 416system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses |
| 417system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses |
| 418system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses |
| 419system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses |
| 420system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses |
| 421system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency |
| 422system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8670.348765 # average ReadReq mshr miss latency |
| 423system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency |
| 424system.cpu.icache.demand_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency |
| 425system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency |
| 426system.cpu.icache.overall_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency |
| 427system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 428system.cpu.dcache.replacements 1427 # number of replacements 429system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use 430system.cpu.dcache.total_refs 172501472 # Total number of references to valid blocks. 431system.cpu.dcache.sampled_refs 4641 # Sample count of references to valid blocks. 432system.cpu.dcache.avg_refs 37169.030812 # Average number of references to valid blocks. 433system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 434system.cpu.dcache.occ_blocks::cpu.data 3127.647604 # Average occupied blocks per requestor --- 39 unchanged lines hidden (view full) --- 474system.cpu.dcache.LoadLockedReq_accesses::total 14010 # number of LoadLockedReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses) 476system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses) 477system.cpu.dcache.demand_accesses::cpu.data 172497310 # number of demand (read+write) accesses 478system.cpu.dcache.demand_accesses::total 172497310 # number of demand (read+write) accesses 479system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses 480system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses 481system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses |
| 482system.cpu.dcache.ReadReq_miss_rate::total 0.000040 # miss rate for ReadReq accesses |
| 483system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses |
| 484system.cpu.dcache.WriteReq_miss_rate::total 0.000238 # miss rate for WriteReq accesses |
| 485system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses |
| 486system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000143 # miss rate for LoadLockedReq accesses |
| 487system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses |
| 488system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses |
| 489system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses |
| 490system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses |
| 491system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency |
| 492system.cpu.dcache.ReadReq_avg_miss_latency::total 32138.410228 # average ReadReq miss latency |
| 493system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency |
| 494system.cpu.dcache.WriteReq_avg_miss_latency::total 33299.569848 # average WriteReq miss latency |
| 495system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency |
| 496system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency |
| 497system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency |
| 498system.cpu.dcache.demand_avg_miss_latency::total 33118.913777 # average overall miss latency |
| 499system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency |
| 500system.cpu.dcache.overall_avg_miss_latency::total 33118.913777 # average overall miss latency |
| 501system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 502system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 504system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 506system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked 507system.cpu.dcache.fast_writes 0 # number of fast writes performed 508system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 530system.cpu.dcache.ReadReq_mshr_miss_latency::total 54896500 # number of ReadReq MSHR miss cycles 531system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101557000 # number of WriteReq MSHR miss cycles 532system.cpu.dcache.WriteReq_mshr_miss_latency::total 101557000 # number of WriteReq MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::cpu.data 156453500 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.demand_mshr_miss_latency::total 156453500 # number of demand (read+write) MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles 536system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles 537system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses |
| 538system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses |
| 539system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses |
| 540system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses |
| 541system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses |
| 542system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses |
| 543system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses |
| 544system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
| 545system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30396.733112 # average ReadReq mshr miss latency |
| 546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30396.733112 # average ReadReq mshr miss latency |
| 547system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35546.727336 # average WriteReq mshr miss latency |
| 548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35546.727336 # average WriteReq mshr miss latency |
| 549system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency |
| 550system.cpu.dcache.demand_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency |
| 551system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency |
| 552system.cpu.dcache.overall_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency |
| 553system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 554system.cpu.l2cache.replacements 69 # number of replacements 555system.cpu.l2cache.tagsinuse 4034.301662 # Cycle average of tags in use 556system.cpu.l2cache.total_refs 13357 # Total number of references to valid blocks. 557system.cpu.l2cache.sampled_refs 5499 # Sample count of references to valid blocks. 558system.cpu.l2cache.avg_refs 2.428987 # Average number of references to valid blocks. 559system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 560system.cpu.l2cache.occ_blocks::writebacks 380.580872 # Average occupied blocks per requestor --- 52 unchanged lines hidden (view full) --- 613system.cpu.l2cache.demand_accesses::cpu.inst 16092 # number of demand (read+write) accesses 614system.cpu.l2cache.demand_accesses::cpu.data 4641 # number of demand (read+write) accesses 615system.cpu.l2cache.demand_accesses::total 20733 # number of demand (read+write) accesses 616system.cpu.l2cache.overall_accesses::cpu.inst 16092 # number of overall (read+write) accesses 617system.cpu.l2cache.overall_accesses::cpu.data 4641 # number of overall (read+write) accesses 618system.cpu.l2cache.overall_accesses::total 20733 # number of overall (read+write) accesses 619system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.194009 # miss rate for ReadReq accesses 620system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834903 # miss rate for ReadReq accesses |
| 621system.cpu.l2cache.ReadReq_miss_rate::total 0.258647 # miss rate for ReadReq accesses |
| 622system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses |
| 623system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 624system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994006 # miss rate for ReadExReq accesses |
| 625system.cpu.l2cache.ReadExReq_miss_rate::total 0.994006 # miss rate for ReadExReq accesses |
| 626system.cpu.l2cache.demand_miss_rate::cpu.inst 0.194009 # miss rate for demand accesses 627system.cpu.l2cache.demand_miss_rate::cpu.data 0.932127 # miss rate for demand accesses |
| 628system.cpu.l2cache.demand_miss_rate::total 0.359234 # miss rate for demand accesses |
| 629system.cpu.l2cache.overall_miss_rate::cpu.inst 0.194009 # miss rate for overall accesses 630system.cpu.l2cache.overall_miss_rate::cpu.data 0.932127 # miss rate for overall accesses |
| 631system.cpu.l2cache.overall_miss_rate::total 0.359234 # miss rate for overall accesses |
| 632system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.136451 # average ReadReq miss latency 633system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34345.388188 # average ReadReq miss latency |
| 634system.cpu.l2cache.ReadReq_avg_miss_latency::total 34292.611795 # average ReadReq miss latency |
| 635system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.055339 # average ReadExReq miss latency |
| 636system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34476.055339 # average ReadExReq miss latency |
| 637system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency 638system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency |
| 639system.cpu.l2cache.demand_avg_miss_latency::total 34362.043502 # average overall miss latency |
| 640system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency 641system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency |
| 642system.cpu.l2cache.overall_avg_miss_latency::total 34362.043502 # average overall miss latency |
| 643system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 644system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 645system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 646system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 647system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 648system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 649system.cpu.l2cache.fast_writes 0 # number of fast writes performed 650system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 29 unchanged lines hidden (view full) --- 680system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96743500 # number of demand (read+write) MSHR miss cycles 681system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133876000 # number of demand (read+write) MSHR miss cycles 682system.cpu.l2cache.demand_mshr_miss_latency::total 230619500 # number of demand (read+write) MSHR miss cycles 683system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96743500 # number of overall MSHR miss cycles 684system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133876000 # number of overall MSHR miss cycles 685system.cpu.l2cache.overall_mshr_miss_latency::total 230619500 # number of overall MSHR miss cycles 686system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for ReadReq accesses 687system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807756 # mshr miss rate for ReadReq accesses |
| 688system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255350 # mshr miss rate for ReadReq accesses |
| 689system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses |
| 690system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 691system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994006 # mshr miss rate for ReadExReq accesses |
| 692system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994006 # mshr miss rate for ReadExReq accesses |
| 693system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for demand accesses 694system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for demand accesses |
| 695system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses |
| 696system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for overall accesses 697system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for overall accesses |
| 698system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses |
| 699system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931 # average ReadReq mshr miss latency 700system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396 # average ReadReq mshr miss latency |
| 701system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31162.253829 # average ReadReq mshr miss latency |
| 702system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency |
| 703system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency |
| 704system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556 # average ReadExReq mshr miss latency |
| 705system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31290.528556 # average ReadExReq mshr miss latency |
| 706system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency 707system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency |
| 708system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency |
| 709system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency 710system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency |
| 711system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency |
| 712system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 713 714---------- End Simulation Statistics ---------- |