7,11c7,11
< host_inst_rate 148173 # Simulator instruction rate (inst/s)
< host_op_rate 189432 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 37097000 # Simulator tick rate (ticks/s)
< host_mem_usage 250340 # Number of bytes of host memory used
< host_seconds 1842.69 # Real time elapsed on the host
---
> host_inst_rate 161957 # Simulator instruction rate (inst/s)
> host_op_rate 207054 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 40547923 # Simulator tick rate (ticks/s)
> host_mem_usage 250356 # Number of bytes of host memory used
> host_seconds 1685.86 # Real time elapsed on the host
81,100c81,87
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 0 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 2 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
---
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 0 # Categorize write packet sizes
133d119
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
166,168c152,153
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 46727256 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests
---
> system.physmem.totQLat 46720000 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 192175000 # Sum of mem lat for all requests
171c156
< system.physmem.avgQLat 6420.34 # Average queueing delay per request
---
> system.physmem.avgQLat 6419.35 # Average queueing delay per request
174c159
< system.physmem.avgMemAccLat 26405.92 # Average memory access latency
---
> system.physmem.avgMemAccLat 26404.92 # Average memory access latency
587c572
< system.cpu.l2cache.tagsinuse 3956.608159 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 3956.608160 # Cycle average of tags in use
705,707c690,692
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115050359 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62984754 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178035113 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115047807 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62983881 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178031688 # number of ReadReq MSHR miss cycles
710,717c695,702
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100922692 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100922692 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115050359 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163907446 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 278957805 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100921221 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100921221 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115047807 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163905102 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 278952909 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115047807 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163905102 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 278952909 # number of overall MSHR miss cycles
731,733c716,718
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38107.918847 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42933.797546 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.065091 # average ReadReq mshr miss latency
736,743c721,728
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36146.569126 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36146.569126 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency
< host_inst_rate 148173 # Simulator instruction rate (inst/s)
< host_op_rate 189432 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 37097000 # Simulator tick rate (ticks/s)
< host_mem_usage 250340 # Number of bytes of host memory used
< host_seconds 1842.69 # Real time elapsed on the host
---
> host_inst_rate 161957 # Simulator instruction rate (inst/s)
> host_op_rate 207054 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 40547923 # Simulator tick rate (ticks/s)
> host_mem_usage 250356 # Number of bytes of host memory used
> host_seconds 1685.86 # Real time elapsed on the host
81,100c81,87
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 0 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 2 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
---
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 0 # Categorize write packet sizes
133d119
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
166,168c152,153
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 46727256 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests
---
> system.physmem.totQLat 46720000 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 192175000 # Sum of mem lat for all requests
171c156
< system.physmem.avgQLat 6420.34 # Average queueing delay per request
---
> system.physmem.avgQLat 6419.35 # Average queueing delay per request
174c159
< system.physmem.avgMemAccLat 26405.92 # Average memory access latency
---
> system.physmem.avgMemAccLat 26404.92 # Average memory access latency
587c572
< system.cpu.l2cache.tagsinuse 3956.608159 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 3956.608160 # Cycle average of tags in use
705,707c690,692
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115050359 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62984754 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178035113 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115047807 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62983881 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178031688 # number of ReadReq MSHR miss cycles
710,717c695,702
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100922692 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100922692 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115050359 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163907446 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 278957805 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100921221 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100921221 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115047807 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163905102 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 278952909 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115047807 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163905102 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 278952909 # number of overall MSHR miss cycles
731,733c716,718
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38107.918847 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42933.797546 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.065091 # average ReadReq mshr miss latency
736,743c721,728
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36146.569126 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36146.569126 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency