7,11c7,11
< host_inst_rate 160764 # Simulator instruction rate (inst/s)
< host_op_rate 205527 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 40194170 # Simulator tick rate (ticks/s)
< host_mem_usage 285344 # Number of bytes of host memory used
< host_seconds 1698.44 # Real time elapsed on the host
---
> host_inst_rate 47859 # Simulator instruction rate (inst/s)
> host_op_rate 61184 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 11965597 # Simulator tick rate (ticks/s)
> host_mem_usage 240720 # Number of bytes of host memory used
> host_seconds 5705.31 # Real time elapsed on the host
73c73
< system.physmem.totGap 68267282000 # Total gap between requests
---
> system.physmem.totGap 68267283000 # Total gap between requests
187c187
< system.physmem.avgGap 9355527.20 # Average gap between requests
---
> system.physmem.avgGap 9355527.34 # Average gap between requests
242c242
< system.cpu.fetch.icacheStallCycles 38860071 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 38860072 # Number of cycles fetch is stalled on an Icache miss
248,249c248,249
< system.cpu.fetch.BlockedCycles 21559516 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.BlockedCycles 21559517 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
252,254c252,254
< system.cpu.fetch.CacheLines 37487912 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 519564 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 136324280 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 37487913 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 519565 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 136324281 # Number of instructions fetched each cycle (Total)
258c258
< system.cpu.fetch.rateDist::0 66156807 48.53% 48.53% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 66156808 48.53% 48.53% # Number of instructions fetched each cycle (Total)
270c270
< system.cpu.fetch.rateDist::total 136324280 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 136324281 # Number of instructions fetched each cycle (Total)
274c274
< system.cpu.decode.BlockedCycles 16729555 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 16729556 # Number of cycles decode is blocked
286c286
< system.cpu.rename.RunCycles 63595531 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 63595532 # Number of cycles rename is running
288c288
< system.cpu.rename.RenamedInsts 393365757 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 393365758 # Number of instructions processed by rename
293,295c293,295
< system.cpu.rename.RenamedOperands 431881386 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2329985493 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1257436076 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 431881387 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2329985497 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1257436080 # Number of integer rename lookups
298c298
< system.cpu.rename.UndoneMaps 47296553 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 47296554 # Number of HB maps that are undone due to squashing
313c313
< system.cpu.iq.issued_per_cycle::samples 136324280 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 136324281 # Number of insts issued each cycle
317c317
< system.cpu.iq.issued_per_cycle::0 24852306 18.23% 18.23% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 24852307 18.23% 18.23% # Number of insts issued each cycle
329c329
< system.cpu.iq.issued_per_cycle::total 136324280 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 136324281 # Number of insts issued each cycle
402c402
< system.cpu.iq.int_inst_queue_reads 653530496 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 653530497 # Number of integer instruction queue reads
425c425
< system.cpu.iew.iewDispSquashedInsts 951525 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 951526 # Number of squashed instructions skipped by dispatch
487c487
< system.cpu.idleCycles 210652 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 210651 # Total number of cycles that the CPU has spent unscheduled due to idling
516,533c516,533
< system.cpu.icache.ReadReq_misses::cpu.inst 17049 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 17049 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 17049 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 17049 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 17049 # number of overall misses
< system.cpu.icache.overall_misses::total 17049 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 356549497 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 356549497 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 356549497 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 356549497 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 356549497 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 356549497 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 37487911 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 37487911 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 37487911 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 37487911 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 37487911 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 37487911 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 17050 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 17050 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 17050 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 17050 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 17050 # number of overall misses
> system.cpu.icache.overall_misses::total 17050 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 356620497 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 356620497 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 356620497 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 356620497 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 356620497 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 356620497 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 37487912 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 37487912 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 37487912 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 37487912 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 37487912 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 37487912 # number of overall (read+write) accesses
540,545c540,545
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20913.220541 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20913.220541 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20916.158182 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20916.158182 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20916.158182 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20916.158182 # average overall miss latency
554,559c554,559
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1254 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 1254 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 1254 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 1254 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 1254 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 1254 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1255 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 1255 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 1255 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 1255 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 1255 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 1255 # number of overall MSHR hits
585,710d584
< system.cpu.dcache.replacements 1414 # number of replacements
< system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use
< system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
< system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
< system.cpu.dcache.overall_misses::total 25149 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
< system.cpu.dcache.writebacks::total 1040 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
712c586
< system.cpu.l2cache.tagsinuse 3959.582107 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 3959.582108 # Cycle average of tags in use
718c592
< system.cpu.l2cache.occ_blocks::cpu.inst 2774.541574 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 2774.541575 # Average occupied blocks per requestor
749,750c623,624
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74801500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 223133500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74802000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 223134000 # number of ReadReq miss cycles
754,755c628,629
< system.cpu.l2cache.demand_miss_latency::cpu.data 203757000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 352089000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 203757500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 352089500 # number of demand (read+write) miss cycles
757,758c631,632
< system.cpu.l2cache.overall_miss_latency::cpu.data 203757000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 352089000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 203757500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 352089500 # number of overall miss cycles
784,785c658,659
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49471.891534 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.255160 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49472.222222 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.364954 # average ReadReq miss latency
789,790c663,664
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 47909.783644 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 47909.851681 # average overall miss latency
792,793c666,667
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 47909.783644 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 47909.851681 # average overall miss latency
855a730,855
> system.cpu.dcache.replacements 1414 # number of replacements
> system.cpu.dcache.tagsinuse 3122.405384 # Cycle average of tags in use
> system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 3122.405384 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
> system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
> system.cpu.dcache.overall_misses::total 25149 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 164690500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 996644664 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 996644664 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 996644664 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 996644664 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.522986 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.522986 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 39629.594179 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 39629.594179 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
> system.cpu.dcache.writebacks::total 1040 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211724000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 211724000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211724000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 211724000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.280353 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.280353 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< host_inst_rate 160764 # Simulator instruction rate (inst/s)
< host_op_rate 205527 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 40194170 # Simulator tick rate (ticks/s)
< host_mem_usage 285344 # Number of bytes of host memory used
< host_seconds 1698.44 # Real time elapsed on the host
---
> host_inst_rate 47859 # Simulator instruction rate (inst/s)
> host_op_rate 61184 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 11965597 # Simulator tick rate (ticks/s)
> host_mem_usage 240720 # Number of bytes of host memory used
> host_seconds 5705.31 # Real time elapsed on the host
73c73
< system.physmem.totGap 68267282000 # Total gap between requests
---
> system.physmem.totGap 68267283000 # Total gap between requests
187c187
< system.physmem.avgGap 9355527.20 # Average gap between requests
---
> system.physmem.avgGap 9355527.34 # Average gap between requests
242c242
< system.cpu.fetch.icacheStallCycles 38860071 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 38860072 # Number of cycles fetch is stalled on an Icache miss
248,249c248,249
< system.cpu.fetch.BlockedCycles 21559516 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.BlockedCycles 21559517 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
252,254c252,254
< system.cpu.fetch.CacheLines 37487912 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 519564 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 136324280 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 37487913 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 519565 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 136324281 # Number of instructions fetched each cycle (Total)
258c258
< system.cpu.fetch.rateDist::0 66156807 48.53% 48.53% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 66156808 48.53% 48.53% # Number of instructions fetched each cycle (Total)
270c270
< system.cpu.fetch.rateDist::total 136324280 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 136324281 # Number of instructions fetched each cycle (Total)
274c274
< system.cpu.decode.BlockedCycles 16729555 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 16729556 # Number of cycles decode is blocked
286c286
< system.cpu.rename.RunCycles 63595531 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 63595532 # Number of cycles rename is running
288c288
< system.cpu.rename.RenamedInsts 393365757 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 393365758 # Number of instructions processed by rename
293,295c293,295
< system.cpu.rename.RenamedOperands 431881386 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2329985493 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1257436076 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 431881387 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2329985497 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1257436080 # Number of integer rename lookups
298c298
< system.cpu.rename.UndoneMaps 47296553 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 47296554 # Number of HB maps that are undone due to squashing
313c313
< system.cpu.iq.issued_per_cycle::samples 136324280 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 136324281 # Number of insts issued each cycle
317c317
< system.cpu.iq.issued_per_cycle::0 24852306 18.23% 18.23% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 24852307 18.23% 18.23% # Number of insts issued each cycle
329c329
< system.cpu.iq.issued_per_cycle::total 136324280 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 136324281 # Number of insts issued each cycle
402c402
< system.cpu.iq.int_inst_queue_reads 653530496 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 653530497 # Number of integer instruction queue reads
425c425
< system.cpu.iew.iewDispSquashedInsts 951525 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 951526 # Number of squashed instructions skipped by dispatch
487c487
< system.cpu.idleCycles 210652 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 210651 # Total number of cycles that the CPU has spent unscheduled due to idling
516,533c516,533
< system.cpu.icache.ReadReq_misses::cpu.inst 17049 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 17049 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 17049 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 17049 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 17049 # number of overall misses
< system.cpu.icache.overall_misses::total 17049 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 356549497 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 356549497 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 356549497 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 356549497 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 356549497 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 356549497 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 37487911 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 37487911 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 37487911 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 37487911 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 37487911 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 37487911 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 17050 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 17050 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 17050 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 17050 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 17050 # number of overall misses
> system.cpu.icache.overall_misses::total 17050 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 356620497 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 356620497 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 356620497 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 356620497 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 356620497 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 356620497 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 37487912 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 37487912 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 37487912 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 37487912 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 37487912 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 37487912 # number of overall (read+write) accesses
540,545c540,545
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20913.220541 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20913.220541 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20916.158182 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20916.158182 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20916.158182 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20916.158182 # average overall miss latency
554,559c554,559
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1254 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 1254 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 1254 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 1254 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 1254 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 1254 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1255 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 1255 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 1255 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 1255 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 1255 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 1255 # number of overall MSHR hits
585,710d584
< system.cpu.dcache.replacements 1414 # number of replacements
< system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use
< system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
< system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
< system.cpu.dcache.overall_misses::total 25149 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
< system.cpu.dcache.writebacks::total 1040 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
712c586
< system.cpu.l2cache.tagsinuse 3959.582107 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 3959.582108 # Cycle average of tags in use
718c592
< system.cpu.l2cache.occ_blocks::cpu.inst 2774.541574 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 2774.541575 # Average occupied blocks per requestor
749,750c623,624
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74801500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 223133500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74802000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 223134000 # number of ReadReq miss cycles
754,755c628,629
< system.cpu.l2cache.demand_miss_latency::cpu.data 203757000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 352089000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 203757500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 352089500 # number of demand (read+write) miss cycles
757,758c631,632
< system.cpu.l2cache.overall_miss_latency::cpu.data 203757000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 352089000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 203757500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 352089500 # number of overall miss cycles
784,785c658,659
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49471.891534 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.255160 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49472.222222 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.364954 # average ReadReq miss latency
789,790c663,664
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 47909.783644 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 47909.851681 # average overall miss latency
792,793c666,667
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 47909.783644 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 47909.851681 # average overall miss latency
855a730,855
> system.cpu.dcache.replacements 1414 # number of replacements
> system.cpu.dcache.tagsinuse 3122.405384 # Cycle average of tags in use
> system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 3122.405384 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
> system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
> system.cpu.dcache.overall_misses::total 25149 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 164690500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 996644664 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 996644664 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 996644664 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 996644664 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.522986 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.522986 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 39629.594179 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 39629.594179 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
> system.cpu.dcache.writebacks::total 1040 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211724000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 211724000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211724000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 211724000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.280353 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.280353 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate